CN1913742A - 印刷电路板布线架构 - Google Patents

印刷电路板布线架构 Download PDF

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CN1913742A
CN1913742A CN200510036572.6A CN200510036572A CN1913742A CN 1913742 A CN1913742 A CN 1913742A CN 200510036572 A CN200510036572 A CN 200510036572A CN 1913742 A CN1913742 A CN 1913742A
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circuit board
printed circuit
differential
integrated chip
signal
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CN100574552C (zh
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舒生云
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Priority to US11/309,266 priority patent/US7679168B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/114—Pad being close to via, but not surrounding the via
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09236—Parallel layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09772—Conductors directly under a component but not electrically connected to the component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

一种印刷电路板布线架构，包括一集成芯片安装区域、若干焊盘、若干过孔以及若干差分导线对，所述若干焊盘分别位于所述集成芯片安装区域的两侧，所述集成芯片的引脚可对应焊接于所述焊盘上，所述若干过孔用以使信号线在印刷电路板的不同布线层间穿越，其中，邻近所述集成芯片安装区域其中一侧的焊盘处设有若干过孔；所述差分导线对中，每一对差分导线分别经过对应所述焊盘后再穿越对应过孔。所述印刷电路板布线架构能使差分导线对的走线接入集成芯片时使得差分导线对中两差分线等长，从而降低差分信号之间的串扰，提高信号传输品质。

Description

印刷电路板布线架构
【技术领域】
本发明涉及一种印刷电路板布线架构，尤指一种能够降低差分信号之间的串扰，提高信号传输品质的印刷电路板布线架构。
【技术背景】
在印刷电路板信号线路设计中，差分信号在高速电路设计中的应用越来越广泛，电路中最关键的信号往往都要采用差分结构设计，差分信号和普通的单端信号相比，其优势体现在以下三个方面：
a)抗干扰能力强，外界共模信号可以在具有良好耦合性能的差分线上被完全抵消；
b)能有效的抑制电磁干扰，极性相反的两信号对外辐射的电磁场可以完全抵消，耦合的越紧密，释放到外界的电磁能量就越少。
c)时序定位精确，由于差分信号的开关变化位于两个信号的交点，而不像普通单端信号依靠两个域值电压判断，因而工艺受温度影响小，能降低时序的误差，更适合低幅度信号的电路。
在布线设计中，差分导线对的布线一般要求差分导线对长度相等，这是为了保证差分线之间的耦合阻抗沿整个差分导线对都为一常数。然而在差分导线对接入集成芯片IC时，参阅图1，现以差分导线对接入静电防护集成芯片IP4220CZ6(Philips)为例，其布线架构包括一长条矩形的集成芯片安装区域10’，四个过孔1’、2’、3’、4’设于所述长条矩形的集成芯片的安装区域10’之中，六个焊盘IC01’～IC06’位于所述集成芯片安装区域长边的两侧，用于焊接集成芯片所对应的引脚。其中，所述第一差分导线对100’中，第一差分线101’先经过所述焊盘IC06’，然后穿越所述过孔1’从元件层(component layer)接入焊接层(solder layer)，第二差分线102’经过所述焊盘IC01’，且穿越所述过孔2’从元件层接入焊接层；所述第二差分导线对200’中，第三差分线202’先经过所述焊盘IC04’，然后穿越所述过孔3’从元件层接入焊接层，第四差分线201’经过焊盘IC03’，且穿越所述过孔4’从元件层接入焊接层。可见，依上述布线架构，所述焊盘IC01’到过孔2’的走线将导致所述第一差分线101’与所述第二差分线102’的走线长度存在较大差异，与此类似，所述焊盘IC03’到过孔3’的走线将导致所述第三差分线202’与所述第四差分线201’的走线长度存在较大差异，这种走线长度上的差异将会导致差分导线对中差分信号间的共模干扰信号增强，严重影响信号的传输品质。
因此，有必要对现有的布线架构进行改进，以消除上述缺点。
【发明内容】
鉴于上述技术内容，有必要提供一种在差分导线对接入集成芯片时可以降低差分信号之间的串扰，又能提高信号传输品质的印刷电路板布线架构。
一种印刷电路板布线架构，包括一集成芯片安装区域、若干焊盘、若干过孔以及若干差分导线对，所述若干焊盘分别位于所述集成芯片安装区域两侧，所述集成芯片的引脚可对应焊接于所述焊盘上，所述若干过孔用以使信号线在印刷电路板的不同布线层间穿越，其中，邻近所述集成芯片安装区域其中一侧的焊盘处设有若干过孔；所述差分导线对中，每一对差分导线分别经过对应所述焊盘后再穿越对应过孔。
所述印刷电路板布线架构能使差分导线对的走线接入集成芯片时使得差分导线对走线路径中各差分线等长，从而降低差分信号之间的串扰，提高信号传输品质。
【附图说明】
图1是现有技术的布线图；
图2是本发明印刷电路板布线架构较佳实施例的布线图。
【具体实施方式】
下面参照附图结合实施例对本发明作进一步的说明。
参阅图2，本发明印刷电路板布线架构较佳实施例，本发明以差分导线对接入静电防护集成芯片IP4220CZ6(Philips)的印刷电路板布线架构为例，所述印刷电路板布线架构，包括一长条矩形的集成芯片安装区域10，六个焊盘IC01～IC06，四个过孔1、2、3、4以及两差分导线对100与200。所述焊盘IC01～IC06分别位于所述集成芯片安装区域10长边的两侧，其中，所述焊盘IC01～IC03位于所述集成芯片安装区域一侧，所述焊盘IC04～IC06位于其另一侧；所述集成芯片信号引脚可分别对应焊接于所述焊盘IC01、IC03、IC04、IC06，所述集成芯片的电源引脚和接地引脚可分别对应所述焊盘IC02和IC05。所述四个过孔1、2、3、4用以使信号走线在印刷电路板的不同布线层间穿越，其中，所述过孔1、2、3、4置于邻近所述焊盘IC01～IC03的位置。所述差分导线对100中，第一差分线101先经过所述焊盘IC06然后穿越所述过孔1从印刷电路板的元件层接入焊接层，第二差分线102先经过所述焊盘IC01，然后穿越所述过孔2从印刷电路板的元件层接入焊接层；所述差分导线对200中，第三差分线202先经过所述焊盘IC04，然后穿越所述过孔3从印刷电路板的元件层接入焊接层，第四差分线201先经过所述焊盘IC03，然后穿越所述过孔4从印刷电路板的元件层接入焊接层。
应用上述印刷电路板布线架构，可消除现有技术中所述第一差分线101’与所述第二差分线102’的走线长度的差异；亦可消除现有技术中所述第三差分线202’与所述第四差分线201’的走线长度的差异，又因差分导线对中，两差分导线中的信号极性相反，故相同长度的差分导线对走线可完全抵消所述差分导线对100、200中的共模干扰信号，从而减小差分导线对之间的串扰，提高信号的传输品质。

Claims (3)

1.一种印刷电路板布线架构，包括一集成芯片安装区域、若干焊盘、若干过孔以及若干差分导线对，所述若干焊盘分别位于所述集成芯片安装区域的两侧，所述集成芯片的引脚可对应焊接于所述焊盘上，所述若干过孔用以使信号线在印刷电路板的不同布线层间穿越，其特征在于：邻近所述集成芯片安装区域其中一侧的焊盘处设有若干过孔；所述差分导线对中，每一对差分导线分别经过对应所述焊盘后再穿越对应过孔。
2.如权利要求1所述印刷电路板布线架构，其特征在于：所述差分导线对穿越所述过孔从印刷电路板的元件层接入焊接层。
3.如权利要求1所述印刷电路板布线架构，其特征在于：所述集成芯片为静电防护集成芯片。
CN200510036572.6A 2005-08-12 2005-08-12 印刷电路板 Expired - Fee Related CN100574552C (zh)

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US11/309,266 US7679168B2 (en) 2005-08-12 2006-07-21 Printed circuit board with differential pair arrangement

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CN115119401A (zh) * 2022-07-28 2022-09-27 苏州浪潮智能科技有限公司 一种印刷电路板及电子设备
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WO2024045803A1 (zh) * 2022-08-30 2024-03-07 中兴通讯股份有限公司 印制电路板、电子设备及控制差分对的传播延迟差的方法

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