WO2022105416A1 - 一种印制电路板 - Google Patents

一种印制电路板 Download PDF

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Publication number
WO2022105416A1
WO2022105416A1 PCT/CN2021/119921 CN2021119921W WO2022105416A1 WO 2022105416 A1 WO2022105416 A1 WO 2022105416A1 CN 2021119921 W CN2021119921 W CN 2021119921W WO 2022105416 A1 WO2022105416 A1 WO 2022105416A1
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WO
WIPO (PCT)
Prior art keywords
differential signal
hole
main body
printed circuit
circuit board
Prior art date
Application number
PCT/CN2021/119921
Other languages
English (en)
French (fr)
Inventor
尹昌刚
魏仲民
易毕
任永会
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Priority to EP21893567.4A priority Critical patent/EP4243577A4/en
Publication of WO2022105416A1 publication Critical patent/WO2022105416A1/zh
Priority to US18/315,589 priority patent/US20230284375A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H05K1/0222—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09236—Parallel layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09636—Details of adjacent, not connected vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09645—Patterning on via walls; Plural lands around one hole
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09718—Clearance holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09727—Varying width along a single conductor; Conductors or pads having different widths
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09854—Hole or via having special cross-section, e.g. elliptical

Definitions

  • the embodiments of the present application relate to the technical field of circuits, and in particular, to a printed circuit board.
  • Gbps GigaBit Per Second: Gigabyte per second
  • BGA Ball Grid array package
  • the dielectric constant of the printed circuit board is selected to be less than 3.0, and the packaging pitch of the BGA chip, that is, two The center distance of each BGA pad is also developing towards small spacing. At this time, in order to ensure the differential outlet, only differential signal holes with small apertures can be used.
  • the impedance of the differential signal hole is much larger than that of the differential line connected to it, resulting in discontinuous impedance between the differential signal hole and the differential line, which in turn leads to the insertion loss and return of the differential signal hole.
  • the loss deteriorates and the insertion loss fluctuation becomes larger.
  • Embodiments of the present application provide a printed circuit board, comprising: a plate-shaped main body, with a plurality of core boards and a plurality of dielectric layers that are parallel to each other and alternately laid, wherein the plurality of core boards includes a plurality of conductor layers , the plurality of conductor layers include a differential signal transmission layer located on the surface layer of the plate-shaped main body portion, and a differential signal outlet layer located in the inner layer of the plate-shaped main body portion;
  • the holes pass through at least part of the core board sequentially from the differential signal transmission layer to the differential signal outlet layer, and connect the differential signal transmission layer and the differential signal outlet layer; two slotted conductive posts located between the two differential signal holes, two slotted The conductive pillars are respectively adjacent to one of the two differential signal holes, and both of the two slotted conductive pillars extend from the differential signal transmission layer to the differential signal outlet layer.
  • FIG. 1 is a schematic three-dimensional structural diagram of a printed circuit board provided in Embodiment 1 of the present application;
  • FIG. 2 is a schematic diagram of the remaining structure after removing the core board and the dielectric layer from the printed circuit board structure shown in FIG. 1;
  • FIG. 3 is a top view of the remaining structure after removing two first signal hole pads, two connecting parts and two BGA pads from the printed circuit board structure shown in FIG. 2;
  • FIG. 4 is a test data diagram of the impedance change effect of a printed circuit board provided with a slotted conductive post compared to a printed circuit board not provided with a slotted conductive post according to Embodiment 1 of the present application;
  • FIG. 5 is a partial schematic diagram of the surface layer of the plate-shaped main body provided in the second embodiment of the present application.
  • FIG. 6 is a graph of experimental data of the impedance change effect of a printed circuit board provided with a slotted conductive post compared to a printed circuit board not provided with a slotted conductive post according to Embodiment 2 of the present application.
  • the main purpose of the embodiments of the present application is to provide a printed circuit board, which can make the impedance of the differential signal hole approach the impedance of the differential line connected to it, improve the impedance continuity between the differential signal hole and the differential line, and further reduce the Insertion loss, return loss deterioration and insertion loss fluctuation of differential signal holes.
  • the first embodiment of the present application relates to a printed circuit board.
  • the two slotted conductive pillars are respectively adjacent to one of the two differential signal holes, and Both the two slotted conductive pillars extend from the differential signal transmission layer to the differential signal outlet layer to increase the aperture of the differential signal hole perpendicular to the thickness direction of the plate-shaped main body, reduce the inductance of the differential signal hole, and then reduce the differential signal hole.
  • the impedance of the differential signal hole is close to the impedance of the differential line connected to it, which improves the impedance continuity between the differential signal hole and the differential line, thereby reducing the insertion loss, return loss deterioration and insertion loss fluctuation of the differential signal hole.
  • the printed circuit board in this embodiment includes a plate-shaped main body 10 , and the plate-shaped main body 10 has core boards and a plurality of dielectric layers 12 that are parallel to each other and alternately laid, wherein the core boards include a plurality of The conductor layers include a differential signal transmission layer located on the surface layer of the plate-shaped main body 10 and a differential signal outlet layer located in the inner layer of the plate-shaped main body 10 .
  • Each of the plurality of dielectric layers 12 includes a dielectric filled therein, and the dielectric constant of the dielectric is less than 3.0.
  • each core board includes two conductor layers and an intermediate medium between the two conductor layers, the two conductor layers are a signal layer and a plane layer 11 respectively, a differential signal transmission layer and Differential signal outlet layers are all signal layers.
  • the above printed circuit board is applied to high-speed products of Gbps and above, which are packaged with BGA chips and whose pitch is less than 1.0mm and require differential outgoing lines.
  • the printed circuit board is a rigid board with a thickness of 4 mm (mm: millimeter), and is made of a stack of twelve layers of core boards and thirteen layers of dielectric layers 12 that are parallel and alternately laid.
  • the plate-shaped main body 10 is composed of twenty-six conductor layers, the dielectric layer 12 is used to maintain the insulation between the printed circuit board circuit and each core board, and the differential signal transmission layer (ie, the signal layer of the first core board) , that is, the first conductor layer) is located on the surface layer of the plate-shaped main body 10, and the differential signal outlet layer (that is, the signal layer of the twelfth layer of the core board) is the twenty-third conductor layer, which is filled in the dielectric layer 12.
  • the dielectric constant is 2.5.
  • the plate-shaped body portion is not limited to the above-mentioned plate-shaped body portion with twenty-six conductor layers stacked, and the dielectric constant of the dielectric filled in the dielectric layer may also be other values.
  • the above-mentioned printed circuit board further includes a first differential signal hole 131 and a second differential signal hole 132 oppositely disposed on the plate-shaped main body 10 .
  • the first differential signal hole 131 and the second differential signal hole 132 sequentially penetrate ten layers of the core board from the differential signal transmission layer to the differential signal outlet layer, and are connected to the differential signal transmission layer and the differential signal outlet layer.
  • the hole diameters of the first differential signal hole 131 and the second differential signal hole 132 are 0.15 mm, and then copper is deposited in the hole diameter of 0.15 mm to form the first differential signal hole 131 surrounded by copper walls and
  • the center-to-center distance between the second differential signal hole 132 , the first differential signal hole 131 and the second differential signal hole 132 is 0.8 mm.
  • the above printed circuit board further includes a first slotted conductive column 141 and a second slotted conductive column 142 located between the first differential signal hole 131 and the second differential signal hole 132 .
  • the first slotted conductive pillar 141 is adjacent to the first differential signal hole 131
  • the second slotted conductive pillar 142 is adjacent to the second differential signal hole 132 .
  • the first slotted conductive pillars 141 and the second slotted conductive pillars 142 both extend from the differential signal transmission layer to the differential signal outlet layer.
  • the parasitic inductance L of the first differential signal hole 131 and the second differential signal hole 132 can be calculated by the following formula (1):
  • the impedance Z of the first differential signal hole 131 and the second differential signal hole 132 can be calculated by formula (2):
  • H is the via length of the first differential signal hole 131 and the second differential signal hole 132
  • d is the aperture of the first differential signal hole 131 and the second differential signal hole 132
  • C is Parasitic capacitances of the first differential signal hole 131 and the second differential signal hole 132 .
  • the first slotted conductive post 141 is adjacent to the first differential signal hole 131
  • the second slotted conductive post 142 is adjacent to the second differential signal hole 132
  • the first slotted conductive post 141 and the second slotted conductive column 142 both extend from the differential signal transmission layer to the differential signal outlet layer, so that the value of "d" in the above formula (1) needs to be perpendicular to the thickness direction of the plate-shaped main body 10 (ie, Fig.
  • the cross-sectional area of the first slotted conductive pillar 141 adjacent to the first differential signal hole 131 and the cross-sectional area of the second slotted conductive pillar 142 adjacent to the second differential signal hole 132 in the Z direction) are calculated, thereby causing the " The value of d" increases, so that the parasitic inductance "L” of the first differential signal hole 131 and the second differential signal hole 132 increases, and the parasitic capacitance C of the first differential signal hole 131 and the second differential signal hole 132 remains unchanged.
  • the impedance Z of the first differential signal hole 131 and the second differential signal hole 132 is reduced, so that the impedance of the first differential signal hole 131 and the second differential signal hole 132 is close to the impedance of the differential line connected to them, reducing the The insertion loss, return loss deterioration and insertion loss fluctuation of the first differential signal hole 131 and the second differential signal hole 132 .
  • the shapes and sizes of the cross-sections of the first slotted conductive pillars 141 and the second slotted conductive pillars 142 in the direction perpendicular to the thickness of the plate-shaped main body 10 are the same. In this way, the impedance of the first differential signal hole 131 and the second differential signal hole 132 in the extending direction of the hole body is made the same, and the stability of the first differential signal hole 131 and the second differential signal hole 132 during data transmission is improved. sex.
  • first slotted conductive column 141 and the second slotted conductive column 142 are both rectangular parallelepipeds; the first differential signal hole 131 and the second differential signal hole are perpendicular to the thickness direction of the plate-shaped main body 10 .
  • the cross-sectional shapes of 132 are all round holes.
  • the first differential signal hole 131 points to the second differential signal hole 132 in the first direction (ie, the Y direction in the figure), in the thickness direction of the plate-shaped main body 10 , the first slotted conductive column 141 and the second slotted conductive column
  • the cross-section of 142 is a rectangle, that is to say, the cross-sections of the first slotted conductive pillar 141 and the second slotted conductive pillar 142 include long straight sides 143 parallel to the first direction and short straight sides perpendicular to the first direction. Side 144.
  • the length of the long straight side 143 is equal to half of the difference between the center distance between the first differential signal hole 131 and the second differential signal hole 132 and the distance between the first slotted conductive pillar 141 and the second slotted conductive pillar 142 .
  • a differential signal hole 131 and the second differential signal hole 132 have the same outer diameter, and the length of the short straight side 144 is not larger than the circle located in the inner layer of the printed circuit board and surrounding the first differential signal hole 131 or the second differential signal hole 132 In this embodiment, the length of the short straight side 144 is equal to the diameter of the outer diameter of the first differential signal hole 131 .
  • the center-to-center distance between the first differential signal hole 131 and the second differential signal hole 132 is 0.8 mm, and the distance between the first slotted conductive post 141 and the second slotted conductive post 142 is 17 mil (mil: mil, one thousandth of an inch); the length of the short straight side 144 (ie, the outer diameter of the first differential signal hole 131 or the outer diameter of the second differential signal hole 132 ) is 6 mil.
  • the distance between the two second slotted conductive pillars and the length of the short straight side 144 can be adjusted by adjusting size, reduce the impedance difference between the BGA fan-out differential signal hole and the differential line to a preset interval, thereby reducing the insertion loss, return loss and insertion loss fluctuation of the differential signal hole, and improving the stability of the entire printed circuit board signal transmission.
  • the above-mentioned printed circuit board in this embodiment additionally includes: disposed on the surface layer (ie, the differential signal transmission layer) of the plate-shaped main body portion 10 and connected to the first differential signal hole 131 and the second differential signal hole 132 respectively. Two first signal hole pads 15 , and two BGA pads 16 respectively connected to the two first signal hole pads 15 .
  • each of the first signal via pads 15 includes a body portion 15a connected to the BGA pad 16 and an extension portion 15b connected to the body portion 15a.
  • One end of the first differential signal hole 131 penetrates through one main body portion 15a and is connected to the main body portion 15a through which it penetrates.
  • the pillars 141 and the second slotted conductive pillars 142 are respectively connected to an extension portion 15b at the ends adjacent to the differential signal transmission layer.
  • two connecting parts 161 are further included, and each first signal hole pad 15 is connected to the BGA pad 16 through one connecting part 161 .
  • both the first differential signal hole 131 and the second differential signal hole 132 include a hole 13a formed on the plate-shaped body portion 10 and a conductive copper plating layer 13b disposed on the hole wall of the hole 13a , the first slotted conductive column 141 and the second slotted conductive column 142 are respectively connected to a conductive copper plating layer 13b.
  • the first slotted conductive post 141 and the second slotted conductive post 142 are respectively plated with a conductive copper plating layer 13b, so that the first slotted conductive post 141 and the first differential signal hole 131 are connected as a whole , the second slotted conductive column 142 is connected to the second differential signal hole 132 as a whole.
  • the above-mentioned printed circuit board in this embodiment further includes: two oppositely arranged first differential lines 171 and second differential lines 172 arranged on the differential signal outlet layer, and arranged on the differential signal outlet layer
  • the first impedance transition portion 181 and the second impedance transition portion 182 arranged oppositely, and the two oppositely arranged third pads 19 arranged on the differential signal outlet layer; the first differential line 171 and the first impedance transition portion 181 pass through a
  • the third pad 19 is connected to the first differential signal hole 131 and the first slotted conductive post 141 ; the second differential line 172 and the second impedance transition portion 182 are connected to the second differential signal hole 132 and The second slotted conductive pillars 142 are connected.
  • the thicknesses of the first differential line 171 , the second differential line 172 , the first impedance transition portion 181 and the second impedance transition portion 182 are all the same; the thickness of the first impedance transition portion 181 is close to the first differential signal hole 131 .
  • the width in the direction that is, the Z direction in the figure
  • the width of the second impedance transition portion 182 in the direction close to the second differential signal hole 132 that is, the X direction in the figure) (also in the X direction in the figure) increases gradually. That is, W) in the figure increases gradually.
  • the first impedance transition portion 181 and the second impedance transition portion 182 reduce the impedance of the two third pads 19 , thereby ensuring the continuity of the impedance and enhancing the structural strength thereof.
  • the distance between the first impedance transition portion 181 and the second impedance transition portion 182 in the direction close to the first differential signal hole 131 and the second differential signal hole 132 ie, the Z direction in the figure
  • the distance between the first differential line 171 and the second differential line 172 can be reduced, so that the line widths of the first differential line 171 and the second differential line 172 are not too narrow, while ensuring the first differential line
  • the line 171 and the second differential line 172 can bypass the single-side back-drilled hole in the BGA via array, thereby increasing the density of traces on the printed circuit board.
  • the distance between the first differential line 171 and the second differential line 172 is 3 mil
  • the line width of the first differential line 171 and the second differential line 172 is 3 mil.
  • the dotted line in the figure is the impedance variation curve of the printed circuit board without the slotted conductive column when transmitting data, and when the time is 2.005ns (ns: nanosecond), the differential signal hole The impedance begins to rise, and the impedance reaches a maximum of 135ohm (ohm: ohm), which differs from the impedance value before 2.005ns and after 2.1ns by a maximum of 35ohm;
  • the solid line in the figure is the setting of the first slotted conductive column 141 and The impedance variation curve of the printed circuit board after the second slotted conductive pillar 142 when transmitting data, when the time is 2.005ns, the impedances of the first differential signal hole 131 and the second differential signal hole 132 begin to decrease
  • the range fluctuates, and the minimum impedance reaches 90ohm, which is only 10ohm different from the impedance value before the time of 2.005ns and after the time of 2.1ns, and
  • the plate-shaped main body 20 of the printed circuit board provided in the second embodiment of the present application is substantially the same as the above-mentioned first embodiment, and the difference lies in that the first slotted conductive column 241 and the second slotted conductive column 242 are Cylindrical body; the cross-sectional shapes of the first differential signal hole 231 and the second differential signal hole 232 in the direction perpendicular to the thickness of the plate-shaped main body portion 20 are circular holes.
  • the above printed circuit board further includes: two first signal hole pads 25 arranged on the surface layer of the plate-shaped main body and connected to the first differential signal hole 231 and the second differential signal hole 232 respectively;
  • the cross-sectional shape of a signal hole pad 25 in a direction perpendicular to the thickness direction of the plate-shaped main body is a circular hole, and the diameters of the first slotted conductive column 241 and the second slotted conductive column 242 are not larger than the first signal hole pad 25 the outer diameter.
  • the diameters of the first slotted conductive pillars 241 and the second slotted conductive pillars 242 are the same as the diameters of the outer diameters of the first differential signal holes 231 and the second differential signal holes 232 .
  • the dotted line in the figure is the impedance change curve of the printed circuit board without slotted conductive pillars when transmitting data, and it can be seen that when the time is 2.005ns, the impedance of the differential signal hole begins to increase , the impedance is up to 135ohm, and the maximum difference from the impedance value before 2.005ns and after 2.1ns is 35ohm; When the printed circuit board transmits data, the impedance change curve with time can be obtained. When the time is 2.005ns, the impedance of the first differential signal hole 231 and the second differential signal hole 232 begin to increase, and the impedance is up to 121ohm. The difference in impedance values before 2.005ns and after 2.1ns is only 21ohm.
  • the above slotted conductive column is not limited to the rectangular parallelepiped mentioned in the first embodiment of the present application and the volume cylinder of the second embodiment, for example, the slotted conductive column is a semi-cylindrical body.
  • the above-mentioned embodiments are specific embodiments for realizing the present application, and in practical applications, various changes in form and details may be made without departing from the spirit and scope of the present application.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本申请实施例涉及电路技术领域，提供了一种印制电路板，包括：板状主体部，具有相互平行且交替铺设的若干芯板和若干介质层，其中，所述若干芯板中包括有多个导体层，多个导体层包括位于板状主体部表层的差分信号传输层、以及位于板状主体部内层的差分信号出线层；相对设置在板状主体部上的两个差分信号孔，两个差分信号孔自差分信号传输层至差分信号出线层依次贯穿至少部分芯板、并连接差分信号传输层以及差分信号出线层；位于两个差分信号孔之间的两个开槽导电柱，两个开槽导电柱分别与两个差分信号孔的一者邻接，两个开槽导电柱均从差分信号传输层延伸至差分信号出线层。

Description

一种印制电路板
相关申请的交叉引用
本申请基于申请号为“202011303587.5”、申请日为2020年11月19日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以引入方式并入本申请。
技术领域
本申请的实施例涉及电路技术领域，特别涉及一种印制电路板。
背景技术
随着科学技术的快速发展，高速系统信号速率已经达到Gbps(Gbps：GigaBit Per Second：千兆字节每秒)，与此同时，G+的研究也已经启动。随着信号速率提高到Gbps及以上时，系统链路中的每个无源部件的性能都变得至关重要。球栅阵列封装(Ball Grid Array Package，简称：BGA)差分信号孔作为高速互连通道中关键的无源部件，其性能能直接影响整个链路的无源性能。
为了在信号速率提高到Gbps及以上时、降低印制电路板的损耗以及提升印制电路板的容量，选用制造印制电路板的板材介电常数小于3.0，而且BGA芯片的封装pitch，即两个BGA焊盘的中心距，也向小间距发展，此时，为保证差分出线，只能采用小孔径的差分信号孔。
然而，由于差分信号孔的孔径较小，导致差分信号孔的阻抗远大于与其连接的差分线的阻抗，造成差分信号孔与差分线间的阻抗不连续，进而导致差分信号孔的插损、回损恶化及插损波动变大。
发明内容
本申请的实施例提供了一种印制电路板，包括：板状主体部，具有相互平行且交替铺设的若干芯板和若干介质层，其中，所述若干芯板中包括有多个导体层，多个导体层包括位于板状主体部表层的差分信号传输层、以及位于板状主体部内层的差分信号出线层；相对设置在板状主体部上的两个差分信号孔，两个差分信号孔自差分信号传输层至差分信号出线层依次贯穿至少部分芯板、并连接差分信号传输层以及差分信号出线层；位于两个差分信号孔之间的两个开槽导电柱，两个开槽导电柱分别与两个差分信号孔的一者邻接，两个开槽导电柱均从差分信号传输层延伸至差分信号出线层。
附图说明
图1是本申请实施例一提供的印制电路板的立体结构示意图；
图2是从图1所示的印制电路板结构中去除芯板以及介质层后的剩余结构示意图；
图3是从图2所示的印制电路板结构中去除两个第一信号孔焊盘、两个连接部以及两个BGA焊盘后的剩余结构俯视图；
图4为本申请实施例一提供印制电路板设置开槽导电柱相较未设置开槽导电柱的阻抗改变效果试验数据图；
图5为本申请实施例二提供的板状主体部表层的局部示意图；
图6为本申请实施例二提供印制电路板设置开槽导电柱相较未设置开槽导电柱的阻抗改变效果试验数据图。
具体实施方式
本申请的实施例的主要目的在于提出一种印制电路板，能够使得差分信号孔的阻抗趋近于与其连接的差分线的阻抗，提升差分信号孔与差分线间的阻抗连续性，进而降低差分信号孔的插损、回损恶化及插损波动。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合相互引用。
本申请实施例一涉及一种印制电路板，通过将两个开槽导电柱设置在两个差分信号孔之间，两个开槽导电柱分别与两个差分信号孔的一者邻接，且两个开槽导电柱均从差分信号传输层延伸至差分信号出线层，以增加差分信号孔垂直于在板状主体部厚度方向上的孔径，降低差分信号孔的感性，进而降低差分信号孔的阻抗，使得差分信号孔的阻抗趋近于与其连接的差分线的阻抗，提升差分信号孔与差分线间的阻抗连续性，进而降低差分信号孔的插损、回损恶化及插损波动。
下面对本实施例的印制电路板的实现细节进行具体的说明，以下内容仅为方便理解提供的实现细节，并非实施本方案的必须。
参见图1，本实施例中的印制电路板包括板状主体部10，板状主体部10具有相互平行且交替铺设的芯板和若干介质层12，其中，若干芯板中包括有多个导体层，多个导体层包括位于板状主体部10表层的差分信号传输层、以及位于板状主体部10内层的差分信号出线层。若干介质层12中均包括填充在其内部的介质，介质的介电常数小于3.0。在本实施例中，每个芯板均包括两层导体层以及位于两层导体层之间的中间介质，两层导体层分别为一层信号层以及一层平面层11，差分信号传输层以及差分信号出线层均为信号层。
上述印制电路板应用于Gbps及以上、采用BGA芯片封装且pitch小于1.0mm并需要差分出线的高速产品。进一步的，在本实施例中，印制电路板为刚性板，其厚度为4mm(mm：毫米)，由相互平行且交替铺设的十二层芯板和十三层介质层12制成的叠层为二十六层导体层的板状主体部10，介质层12用于保持印制电路板线路以及各个芯板之间的绝缘性，差分信号传输层(即第一层芯板的信号层，也即第一层导体层)位于板状主体部10表层，差分信号出线层(即第十二层芯板的信号层)为第二十三层导体层，填充在介质层12中介质的介电常数为2.5。
需要说明的是，板状主体部并不限于上述提及的叠层为二十六层导体层的板状主体部，其填充在介质层中介质的介电常数也可为其他数值。
参见图2与图3，上述印制电路板还包括相对设置在板状主体部10上的第一差分信号孔131以及第二差分信号孔132。第一差分信号孔131以及第二差分信号孔132自差分信号传输层至差分信号出线层依次贯穿十层芯板、并连接差分信号传输层以及差分信号出线层。在本实施例中，第一差分信号孔131以及第二差分信号孔132的钻孔孔径为0.15mm，进而在 0.15mm的孔径中沉积铜以形成由铜壁围城的第一差分信号孔131以及第二差分信号孔132，第一差分信号孔131以及第二差分信号孔132的中心间距为0.8mm。
上述印制电路板还包括位于第一差分信号孔131以及第二差分信号孔132之间的第一开槽导电柱141以及第二开槽导电柱142。第一开槽导电柱141与第一差分信号孔131邻接，第二开槽导电柱142与第二差分信号孔132邻接。第一开槽导电柱141以及第二开槽导电柱142均从差分信号传输层延伸至差分信号出线层。
具体的说，第一差分信号孔131以及第二差分信号孔132的寄生电感L可以用下面公式(1)计算得出：
L＝5.08H[ln(4H/d)+1]......................................................................................................(1)
第一差分信号孔131以及第二差分信号孔132的阻抗Z可由公式(2)计算得出：
Figure PCTCN2021119921-appb-000001
上述公式(1)、(2)中H为第一差分信号孔131以及第二差分信号孔132的过孔长度，d为第一差分信号孔131以及第二差分信号孔132的孔径，C为第一差分信号孔131以及第二差分信号孔132的寄生电容。
本实施例提供的印制电路板通过将第一开槽导电柱141与第一差分信号孔131邻接、第二开槽导电柱142与第二差分信号孔132邻接、且第一开槽导电柱141以及第二开槽导电柱142均从差分信号传输层延伸至差分信号出线层，使得上述公式(1)中“d”值需将在垂直于在板状主体部10的厚度方向(即图示Z方向)上、与第一差分信号孔131邻接的第一开槽导电柱141以及与第二差分信号孔132邻接的第二开槽导电柱142的横截面积计算在内，进而引起“d”值变大，使得第一差分信号孔131以及第二差分信号孔132的寄生电感“L”变大，在第一差分信号孔131以及第二差分信号孔132的寄生电容C不变的情况下，降低第一差分信号孔131以及第二差分信号孔132的阻抗Z，以使第一差分信号孔131以及第二差分信号孔132的阻抗趋近于与其连接的差分线的阻抗，降低第一差分信号孔131以及第二差分信号孔132的插损、回损恶化及插损波动。
在一个例子中，在垂直于在板状主体部10的厚度方向上、第一开槽导电柱141以及第二开槽导电柱142各处横截面的形状及大小均相同。这样一来，使得第一差分信号孔131以及第二差分信号孔132的其孔体延伸方向上的各处阻抗相同，提升第一差分信号孔131以及第二差分信号孔132传输数据时的稳定性。
在一个例子中，第一开槽导电柱141以及第二开槽导电柱142均为长方体；在垂直于在板状主体部10的厚度方向上、第一差分信号孔131以及第二差分信号孔132的截面形状均为圆孔。第一差分信号孔131指向第二差分信号孔132为第一方向(即图示Y方向)，在板状主体部10的厚度方向上、第一开槽导电柱141以及第二开槽导电柱142的横截面为长方形，也就是说，第一开槽导电柱141以及第二开槽导电柱142的横截面均包括与第一方向平行的长直边143以及与第一方向垂直的短直边144。其中，长直边143的长度等于第一差分信号孔131以及第二差分信号孔132的中心间距与第一开槽导电柱141以及第二开槽导电柱142之间的距离差的一半，第一差分信号孔131与第二差分信号孔132外径相同，短直边144的长度尺寸不大于位于印制电路板内层且环绕第一差分信号孔131或者第二差分信号孔132设置的圆形焊盘的外径；在本实施例中，短直边144的长度等于第一差分信号孔131外径的直径。
在本实施例中，第一差分信号孔131以及第二差分信号孔132的中心间距为0.8mm，第一开槽导电柱141以及第二开槽导电柱142之间的距离为17mil(mil：密尔，千分之一英寸)；短直边144的长度(也即第一差分信号孔131的外径或者第二差分信号孔132的外径)为6mil。
需要说明的是，由于不同印制电路板差分信号孔和与其连接的差分线的阻抗差值不同，因此，可通过调节两个第二开槽导电柱之间的间距以及短直边144的长度尺寸，将BGA扇出差分信号孔与差分线阻抗差异降低至预设的区间内，从而降低差分信号孔插损、回损和插损波动，提高整个印制电路板信号传输时的稳定性。
具体的，本实施例中的上述印制电路板还额外包括：设置在板状主体部10表层(即差分信号传输层)、并分别连接第一差分信号孔131与第二差分信号孔132的两个第一信号孔焊盘15，以及分别与两个第一信号孔焊盘15连接的两个BGA焊盘16。
在一个例子中，每个第一信号孔焊盘15均包括与BGA焊盘16相连的主体部15a以及与主体部15a相连的延伸部15b。第一差分信号孔131的一端贯通一个主体部15a并与其贯穿的主体部15a相连，第二差分信号孔132的一端贯通另一个主体部15a并与其贯穿的主体部15a相连，第一开槽导电柱141以及第二开槽导电柱142在邻近差分信号传输层的端部分别与一个延伸部15b相连。在本实施例中，还包括两个连接部161，每个第一信号孔焊盘15通过一个连接部161连接BGA焊盘16。
在另一可变更的实施例中，第一差分信号孔131与第二差分信号孔132均包括开设在板状主体部10上的孔13a以及设置在孔13a的孔壁上的导电铜镀层13b，第一开槽导电柱141以及第二开槽导电柱142分别与一个导电铜镀层13b相接。在本实施例中，第一开槽导电柱141以及第二开槽导电柱142分别与一个导电铜镀层13b电镀连接，使得第一开槽导电柱141与第一差分信号孔131连接为一个整体，第二开槽导电柱142与第二差分信号孔132连接为一个整体。
在一个例子中，本实施例中的上述印制电路板还包括：设置在差分信号出线层上的两个相对设置的第一差分线171以及第二差分线172、设置在差分信号出线层上相对设置的第一阻抗过渡部181以及第二阻抗过渡部182、设置在差分信号出线层上的两个相对设置的第三焊盘19；第一差分线171以及第一阻抗过渡部181通过一个第三焊盘19与第一差分信号孔131以及第一开槽导电柱141连接；第二差分线172以及第二阻抗过渡部182通过另一个第三焊盘19与第二差分信号孔132以及第二开槽导电柱142连接。
在一个例子中，第一差分线171、第二差分线172、第一阻抗过渡部181以及第二阻抗过渡部182的厚度均相同；第一阻抗过渡部181在靠近第一差分信号孔131方向(也即图示Z方向)上的宽度(也即图示W)逐渐增大，第二阻抗过渡部182在靠近第二差分信号孔132方向(也即图示X方向)上的宽度(也即图示W)逐渐增大。这样一来，第一阻抗过渡部181以及第二阻抗过渡部182降低了两个第三焊盘19的阻抗，保证阻抗连续性的同时增强其结构强度。
在一个例子中，第一阻抗过渡部181以及第二阻抗过渡部182在靠近第一差分信号孔131以及第二差分信号孔132方向(也即图示Z方向)上的间距(也即图示D)逐渐增大。这样一来，可通过减小第一差分线171与第二差分线172之间的间距、使得第一差分线171与第二差分线172的线宽不至于过窄的同时、确保第一差分线171与第二差分线172在BGA过孔阵列中能够绕过单侧背钻孔出线，进而增加印制电路板的走线密集度。在本实施例中，第一 差分线171与第二差分线172之间的间距为3mil，第一差分线171与第二差分线172的线宽为3mil。
进一步参见图4，图中虚线为未设置开槽导电柱的印制电路板在传输数据时、随时间变化的阻抗变化曲线，在时间为2.005ns(ns：纳秒)时，差分信号孔的阻抗开始升高，阻抗最高达到135ohm(ohm：欧姆)，与时间在2.005ns之前以及时间在2.1ns之后的阻抗值相差最大值高达35ohm；图中实线为设置第一开槽导电柱141以及第二开槽导电柱142之后的印制电路板在传输数据时、随时间变化的阻抗变化曲线，在时间为2.005ns时，第一差分信号孔131以及第二差分信号孔132的阻抗开始小范围波动，阻抗最小达到90ohm，与时间在2.005ns之前以及时间在2.1ns之后的阻抗值相差值仅为10ohm，而且在数据通过第一差分信号孔131以及第二差分信号孔132传输时、阻抗值波动变化较小，尤其是在2.35ns至2.55ns时阻抗值相差不到4ohm。
参见图5，本申请实施例二提供印制电路板的板状主体部20与上述实施例一大致相同，其不同之处在于，第一开槽导电柱241以及第二开槽导电柱242为圆柱体；在垂直于在板状主体部20的厚度方向上、第一差分信号孔231以及第二差分信号孔232的截面形状为圆孔。
在一个例子中，上述印制电路板中还包括：设置在板状主体部表层、并分别连接第一差分信号孔231以及第二差分信号孔232的两个第一信号孔焊盘25；第一信号孔焊盘25在垂直于在板状主体部厚度方向上的截面形状为圆孔，第一开槽导电柱241以及第二开槽导电柱242的直径不大于第一信号孔焊盘25的外径。在本实施例中，第一开槽导电柱241以及第二开槽导电柱242的直径与第一差分信号孔231以及第二差分信号孔232外径的直径相同。
进一步参见图6，图中虚线为未设置开槽导电柱的印制电路板在传输数据时、随时间变化的阻抗变化曲线，可得在时间为2.005ns时，差分信号孔的阻抗开始升高，阻抗最高达到135ohm，与时间在2.005ns之前以及时间在2.1ns之后的阻抗值相差最大值达到35ohm；图中实线为设置第一开槽导电柱241以及第二开槽导电柱242之后的印制电路板在传输数据时、随时间变化的阻抗变化曲线，可得在时间为2.005ns时，第一差分信号孔231以及第二差分信号孔232的阻抗开始增加，阻抗最高达到121ohm，与时间在2.005ns之前以及时间在2.1ns之后的阻抗值相差值仅为21ohm。
本领域的普通技术人员可以理解，上述开槽导电柱并于限于本申请实施例一提及的长方体以及实施例二体积的圆柱体，如：开槽导电柱为半圆柱体等。此外，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (11)

  1. 一种印制电路板，包括：
    板状主体部，具有相互平行且交替铺设的若干芯板和若干介质层，其中，所述若干芯板中包括有多个导体层，所述多个导体层包括位于所述板状主体部表层的差分信号传输层、以及位于所述板状主体部内层的差分信号出线层；
    相对设置在所述板状主体部上的两个差分信号孔，所述两个差分信号孔自所述差分信号传输层至所述差分信号出线层依次贯穿至少部分所述芯板、并连接所述差分信号传输层以及所述差分信号出线层；
    位于所述两个差分信号孔之间的两个开槽导电柱，所述两个开槽导电柱分别与所述两个差分信号孔的一者邻接，所述两个开槽导电柱均从所述差分信号传输层延伸至所述差分信号出线层。
  2. 根据权利要求1所述的印制电路板，其中，在垂直于在所述板状主体部的厚度方向上，所述两个开槽导电柱各处横截面的形状及大小均相同。
  3. 根据权利要求1或2所述的印制电路板，其中，所述开槽导电柱为长方体；在垂直于在所述板状主体部的厚度方向上，所述差分信号孔的截面形状为圆孔。
  4. 根据权利要求3所述的印制电路板，其中，所述两个差分信号孔中的一者指向另一者的方向为第一方向，在垂直于所述板状主体部的厚度方向上、所述开槽导电柱的横截面包括与所述第一方向平行的长直边以及与所述第一方向垂直的短直边；所述长直边的长度等于所述两个差分信号孔的中心间距与所述两个开槽导电柱之间的距离差的一半，所述短直边的长度等于所述差分信号孔外径的直径。
  5. 根据权利要求1或2所述的印制电路板，其中，所述开槽导电柱为圆柱体；在垂直于在所述板状主体部的厚度方向上，所述差分信号孔的截面形状为圆孔。
  6. 根据权利要求5所述的印制电路板，其中，还包括：设置在所述板状主体部表层、并分别连接所述两个差分信号孔的两个第一信号孔焊盘；所述第一信号孔焊盘在垂直于在所述板状主体部厚度方向上的截面形状为圆孔，所述开槽导电柱的直径不大于所述第一信号孔焊盘的外径。
  7. 根据权利要求1-6任一项所述的印制电路板，其中，还包括：设置在所述板状主体部表层、并分别连接所述两个差分信号孔的两个第一信号孔焊盘，以及分别与所述两个第一信号孔焊盘连接的两个BGA焊盘，其中，每个所述第一信号孔焊盘均包括与所述BGA焊盘相连的主体部以及与所述主体部相连的延伸部，所述差分信号孔的一端贯通所述主体部并与所述主体部相连，所述开槽导电柱邻近所述差分信号传输层的端部与所述延伸部相连。
  8. 根据权利要求1-7任一项所述的印制电路板，其中，还包括：所述差分信号孔包括开设在所述板状主体部上的孔以及设置在所述孔的孔壁上的导电铜镀层，所述开槽导电柱与所述导电铜镀层相接。
  9. 根据权利要求1-8任一项所述的印制电路板，其中，还包括：设置在所述差分信号出线层上的两个相对设置的差分线、设置在所述差分信号出线层上的两个相对设置的阻抗过渡部以及设置在所述差分信号出线层上的两个相对设置的第三焊盘；每个所述差分线均通过一个所述阻抗过渡部与一个所述第三焊盘连接；每个所述第三焊盘均与一个所述差分信号孔以及一个所述开槽导电柱连接。
  10. 根据权利要求9所述的印制电路板，其中，所述阻抗过渡部的厚度与所述差分线的厚度相同；所述阻抗过渡部在靠近与其连接的所述差分信号孔方向上的宽度逐渐增大。
  11. 根据权利要求9或10所述的印制电路板，其中，所述两个阻抗过渡部在靠近所述两个差分信号孔方向上的间距逐渐增大。
PCT/CN2021/119921 2020-11-19 2021-09-23 一种印制电路板 WO2022105416A1 (zh)

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