CN1898795A - 具有薄膜电容器结构的集成电路封装衬底 - Google Patents

具有薄膜电容器结构的集成电路封装衬底 Download PDF

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CN1898795A
CN1898795A CNA2004800384561A CN200480038456A CN1898795A CN 1898795 A CN1898795 A CN 1898795A CN A2004800384561 A CNA2004800384561 A CN A2004800384561A CN 200480038456 A CN200480038456 A CN 200480038456A CN 1898795 A CN1898795 A CN 1898795A
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C·帕兰杜兹
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Abstract

本发明涉及集成电路封装的衬底诸如封装衬底或插入衬底的制造。使用其中具有多个通路孔的绿色材料形成基底结构。随后烧结该绿色材料，使得绿色材料变成烧结陶瓷材料且该基底结构变成具有通路孔的烧结陶瓷基底结构。在烧结陶瓷基底结构的每个通路孔内形成导电通路。在该烧结陶瓷基底结构上形成电容器结构。该电容器结构的电源层和接地层连接到该通路。这样可形成电容器结构，且无需在诸如硅衬底的脆性衬底中钻出通路孔而将该电容器结构连接到通路。烧结陶瓷材料还具有低的热膨胀系数，可承受制造该电容器结构时的高温加工条件，且制造成本不昂贵。

Description

具有薄膜电容器结构的集成电路封装衬底
技术领域
本发明涉及一种电容器结构，其中该电容器结构被包括在集成电路封装衬底内。
背景技术
集成电路通常制造在晶片衬底上。晶片衬底随后被“切割”或“划分”成单个芯片，每个芯片承载各自的集成电路。经常使用中间插入衬底将芯片随后安装在封装衬底上。该一个或多个衬底为最终的集成电路封装提供了结构刚度。封装衬底还提供了从芯片接触到承载衬底上接触的x-y变换，其中该集成电路安装在该承载衬底上。
可通过该一个或多个衬底内的导体向/从芯片内的集成电路提供信号。当通过这些导体发送信号时，经常会出现称为电阻-电容-电感延迟的信号延迟。为了降低电阻-电容-电感延迟，经常将电容器设成靠近该芯片。该电容器起着靠近集成电路的功率贮存器的作用。
离散电容器相对较大，因此在衬底上占据大量固定位置。已经了解到，薄膜电容器会占据较少的固定位置，这使得可以形成更多的电容器。与将离散电容器安装到衬底上的情形相比，这还会使得在制造衬底时薄膜电容器的制造更为简单。
需要在衬底的基底结构中制造通路孔(via opening)，在该通路孔内形成导电通路，其中薄膜电容器结构的电源层和接地层应连接到该导电通路。这种通路孔的制备已经成为半导体行业许多年来的研究重点。迄今为止，所有的努力都是针对在诸如硅的低k值材料中钻孔。硅为脆性材料，使得难以在该材料内钻孔。此外还必须分别钻出每个孔，这降低了生产能力。
附图说明
通过示例的方式参考附图描述本发明，其中：
图1为根据本发明实施例制造的插入衬底的截面侧视图；
图2为包括图1的插入衬底的集成电路封装的截面侧视图；
图3为根据本发明实施例制造的封装衬底的截面侧视图；以及
图4为包括图3的封装衬底的集成电路封装的截面侧视图。
发明详述
现在描述集成电路封装的衬底诸如封装衬底或插入衬底的制造。使用其中具有多个通路孔的绿色材料(green material)形成基底结构。随后烧结该绿色材料，使得绿色材料变成烧结陶瓷材料且该基底结构变成具有通路孔的烧结陶瓷基底结构。在烧结陶瓷基底结构的每个通路孔内形成导电通路。在该烧结陶瓷基底结构上形成电容器结构。该电容器结构的电源层和接地层连接到该通路。这样可形成电容器结构，且无需在诸如硅衬底的脆性衬底中钻出通路孔而将该电容器结构连接到该通路。烧结陶瓷材料还具有低的热膨胀系数，可承受制造该电容器结构时的高温加工条件，且制造成本不昂贵。
附图的图1阐述了根据本发明实施例的方法进行构造的插入衬底10。插入衬底10包括基底结构12、导电通路14、具有高k值电介质材料的电容器结构16、低k值电介质材料18、以及接触焊盘20。
基底结构12最初是由未经烧结的绿色材料制成的。绿色材料被封装成基底结构12的形状，随后将通路孔22冲孔穿过该绿色材料。绿色材料的加工、封装、和冲孔在本领域中是已知的。通过冲孔在绿色材料中形成孔洞的优点在于，该绿色材料不像诸如硅衬底的其它衬底那么脆。随后烧结该绿色材料，使得该绿色材料变成烧结陶瓷材料且该基底结构12变成烧结陶瓷基底结构12。烧结陶瓷基底结构12随后具有通路孔22。通路孔22包括电源通路孔22P、接地通路孔22G、以及信号通路孔22S。每一个通路孔22从水平烧结陶瓷基底结构12的下表面延伸到上表面。
随后在烧结陶瓷基底结构12的整个上表面上形成低k值电介质材料18。该低k值电介质材料18因此覆盖电源通路孔22P、接地通路孔22G、以及信号通路孔22S。通常由介电常数介于3和4之间的二氧化硅形成该低k值电介质材料18。
随后图形化该低k值电介质材料18。例如可以先覆盖该低k值电介质材料18的一部分并随后将暴露部分烧掉，由此图形化该低k值电介质材料18。被烧掉(或腐蚀掉)的部分为该低k值电介质材料18位于电源通路孔22P和接地通路孔22G上的部分。低k值电介质材料18中的通路孔也被烧掉(或腐蚀掉)，使得信号通路孔22S垂直地延伸穿过该低k值电介质材料18。
随后在低k值电介质材料18已经被烧掉(或腐蚀掉)的烧结陶瓷基底结构12上形成电容器结构16。也就是说，在烧结陶瓷基底结构12上表面的具有电源通路孔22P和接地通路孔22G的区域上形成电容器结构16。电容器结构16包括电源层24和接地层26以及电介质层28。通常由铜或铂制成该电源层和接地层。电介质层28是由介电常数介于300和900之间的高k值电介质材料制成，尽管该介电常数可高达3000。在接地层26的顶部上形成绝缘层30以增加第二电容，该绝缘层由和电介质层28相同的材料制成。可以为额外的电容增加更多的层。各层及平面24、26、28和30都被图形化，使得电源通路孔22P和接地通路孔22G垂直地延伸穿过整个电容器结构16。诸如电容器结构16的薄膜电容器结构的制造在本领域中是已知的。
接着使用导电通路14填充所有的通路孔22。导电通路14通常是由诸如铜、银、或钨钼合金的导电金属制成。例如在通路孔22内可以溅射沉积、电镀或印刷导电通路。导电通路14包括分别位于电源通路孔22P、接地通路孔22G、以及信号通路孔22S内的电源导电通路14P、接地导电通路14G、以及信号导电通路14S。电源导电通路14P和电源层24接触，但不连接到接地层26。接地导电通路14G和接地层26接触，但不连接到电源层24。每个信号导电通路14S与所有其它导电通路14P、14G及14S电学断开。
随后在电容器结构16和低k值电介质材料18上形成接触焊盘20。每个接触焊盘20位于各自的导电通路14上并电连接到各自的导电通路14。
图2阐述了根据本发明实施例的位于集成电路封装34内的插入衬底10。该集成电路封装34还包括承载衬底36、封装衬底38、芯片40、以及各组导电互连部件42、44和46。
封装衬底38具有基底结构48、基底结构48内的多个导电线50、位于基底结构48的下表面上的多个接触焊盘52、以及位于该基底结构48的上表面上的多个接触焊盘54。基底结构48是由低k值电介质材料制成。在给定示例中，每一个导电线50将各自的接触焊盘52和各自的接触焊盘54互连。部分导电线50具有通过水平线60互连的两个垂直通路56和58。包括了水平线60后，使得可以相对于接触焊盘52而偏移接触焊盘54。导电线50因此可实现从接触焊盘52到接触焊盘54的x-y变换。
如图所示，插入衬底10进一步具有位于烧结陶瓷基底结构12下表面上的多个接触焊盘62。位于插入衬底10下侧的接触焊盘62与位于插入衬底10上侧的接触焊盘20之间没有x-y变换。每一个接触焊盘62和各自的接触焊盘54相匹配，各自的导电互连部件44将各自的接触焊盘62与各自的接触焊盘54互连。
芯片40具有形成于其下表面内的集成电路。多个接触焊盘64形成于芯片40下表面上，并电连接到该集成电路。每个接触焊盘64和各自的接触焊盘20相匹配，并通过各自的导电互连部件46连接到各自的接触焊盘20。因此可以看出，从接触焊盘64到接触焊盘54没有x-y变换，从接触焊盘54到接触焊盘52存在x-y变换。
承载衬底36具有各自的基底结构66以及形成于基底结构66上表面上的多个接触焊盘68。每一个接触焊盘52和各自的接触焊盘68对齐，并通过各自的导电互连部件42连接到接触焊盘68。
图3阐述了使用根据本发明另一个实施例的方法制造的封装衬底138。封装衬底138包括和图1插入衬底10的烧结陶瓷基底结构12、电容器结构16、和接触焊盘20相同的烧结陶瓷基底结构112、电容器结构116、低k值电介质材料118、和接触焊盘120。封装衬底138与插入衬底10不同之处在于提供了导电线150而非导电通路14。
每一个导电线包括两个垂直通路156和158以及互连垂直通路156和158的水平线160。分阶段形成烧结陶瓷基底结构112，使得水平线160被掩埋在烧结陶瓷基底结构112上表面之下。水平线160使得垂直通路156和158相互之间可发生水平偏移。水平线160因此可实现垂直通路156到垂直通路158的x-y变换。
图4阐述了包括封装衬底138、承载衬底136、和芯片140的集成电路封装。芯片140和承载衬底136和图2的集成电路封装34的芯片40及承载衬底36相同。集成电路封装134与集成电路封装34的不同之处在于，芯片140和封装衬底138之间没有中间插入衬底。在图2的集成电路封装34中，插入衬底10提供了靠近芯片40的电容器结构16，封装衬底38提供了x-y变换。相反，在图4的集成电路封装134中，封装衬底138提供了靠近芯片140的电容器结构116并提供了x-y变换。
尽管已经描述并在附图中示出了特定的示例实施例，但应该了解到，这些实施例纯粹是阐述性的而非限制本发明，本发明不限于所示和所描述的具体构造和排列，因为本领域技术人员可想到对本发明的各种调整。

Claims (22)

1.一种构造至少部分集成电路封装的方法，包括：
使用其中具有多个通路孔的绿色材料形成基底结构；
烧结该绿色材料，使得绿色材料变成烧结陶瓷材料，该基底结构变成具有通路孔的烧结陶瓷基底结构；
在烧结陶瓷基底结构的每个通路孔内形成导电通路，所述导电通路包括至少电源通孔和接地通孔；以及
在该烧结陶瓷基底结构上形成电容器结构，该电容器结构包括导电的电源层和接地层以及介于该电源层和接地层之间的电介质层，该电源层和接地层分别电连接到至少一个电源通路和一个接地通路。
2.权利要求1的方法，其中该通路包括信号通路，每个信号通路和电源层及接地层电学断开。
3.权利要求2的方法，其中该电容器结构的电介质层是由具有高k值的电介质材料制成，该衬底具有第一部分和第二部分，第一部分具有高k值电介质材料，第二部分没有该高k值电介质材料，信号通路形成于该第二部分内。
4.权利要求1的方法，进一步包括：
将电容器结构安装在该基底结构上，共同地在封装衬底上形成插入衬底；以及
将其中形成了微电子电路的芯片安装到该插入衬底。
5.权利要求4的方法，进一步包括：
在该封装衬底上形成多个导电部件从而与承载衬底互连。
6.一种集成电路封装的衬底，包括：
其中形成了多个通路孔的烧结陶瓷基底结构；
每个通路孔中的导电通路，该导电通路至少包括电源通路和接地通路；以及
该烧结陶瓷基底结构上的电容器结构，该电容器结构包括导电的电源层和接地层以及介于该电源层和接地层之间的电介质层，该电源层和接地层分别电连接到至少一个电源通路和接地通路。
7.权利要求6的衬底，其中该通路包括信号通路，每个信号通路和电源层及接地层电学断开。
8.权利要求7的衬底，其中该电容器结构的电介质层是由具有高k值的电介质材料制成，该衬底具有第一部分和第二部分，第一部分具有高k值电介质材料，第二部分没有该高k值电介质材料，信号通路形成于该第二部分内。
9.用于集成电路芯片的封装衬底，包括：
具有水平电介质层以及介于两个电介质层之间的至少一个水平金属导体层的基底结构，该基底结构中具有多个垂直延伸的通路孔；
每个通路孔中的导电通路，该导电通路至少包括电源导电通路和接地导电通路；以及
基底结构上的电容器结构，该电容器结构包括水平电源层和接地层以及介于该电源层和接地层之间的水平电介质层，该电源层和接地层分别电连接到至少一个电源通路和接地通路。
10.权利要求9的封装衬底，其中该基底结构由烧结陶瓷材料制成。
11.权利要求9的封装衬底，其中该通路包括信号通路，每个信号通路和电源层及接地层电学断开。
12.权利要求11的封装衬底，其中电源通路、接地通路、和信号通路分别连接电容器结构的电源导体、接地导体、和信号导体。
13.权利要求9的封装衬底，进一步包括：
基底结构上的多个第一接触；以及
该电容器结构上的多个第二接触，该金属导体形成了从多个第一接触到多个第二接触的x-y变换。
14.一种集成电路封装，包括：
包括烧结陶瓷基底结构的衬底，该烧结陶瓷基底结构中形成了多个通路孔；
每个通路孔中的导电通路，该导电通路至少包括电源通路和接地通路；以及
该烧结陶瓷基底结构上的电容器结构，该电容器结构包括导电的电源层和接地层以及介于该电源层和接地层之间的电介质层，该电源层和接地层分别电连接到至少一个电源通路和接地通路；以及
安装到该衬底上的芯片，该芯片中形成了集成电路。
15.权利要求14的集成电路封装，其中该衬底为插入衬底，该集成电路封装进一步包括：
封装衬底，该插入衬底被安装到该封装衬底。
16.权利要求15的集成电路封装，其中在没有x-y变换的情况下通路连接到该封装衬底上的接触。
17.权利要求14的集成电路封装，其中该通路包括信号通路，每个信号通路和电源层及接地层电学断开。
18.一种集成电路封装，包括：
包括基底结构的衬底，该基底结构具有水平电介质层以及介于两个电介质层之间的至少一个水平金属导体层，该基底结构中具有多个垂直延伸的通路孔；
每个通路孔中的导电通路，该导电通路至少包括电源通路和接地通路；
该基底结构上的电容器结构，该电容器结构包括水平的电源层和接地层以及介于该电源层和接地层之间的水平电介质层，该电源层和接地层分别电连接到至少一个电源通路和接地通路；以及
安装到该衬底上的芯片，该芯片中形成了集成电路。
19.权利要求18的集成电路封装，其中该基底结构由烧结陶瓷材料制成。
20.权利要求18的集成电路封装，其中通路包括信号通路，每个信号通路和电源层及接地层电学断开。
21.权利要求20的集成电路封装，其中电源通路、接地通路、和信号通路分别连接到由金属导体制成的电源导体、接地导体、和信号导体。
22.权利要求18的集成电路封装，其中在没有介入插入衬底的情况下将芯片安装到衬底上。
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