CN111293044A - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
CN111293044A
CN111293044A CN201910227977.XA CN201910227977A CN111293044A CN 111293044 A CN111293044 A CN 111293044A CN 201910227977 A CN201910227977 A CN 201910227977A CN 111293044 A CN111293044 A CN 111293044A
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conductor
semiconductor
semiconductor layer
electronic circuit
circuit structure
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蔡宏奇
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本申请涉及一种半导体结构及其制造方法。该半导体结构包括一第一第二半导体层与一第二半导体层、以及一第一连结导体、一第二连结导体与一第三连结导体。该第二半导体层设于该第一半导体层之上。该第一连结导体设于该第一半导体层之上。该第二连结导体设于该第二半导体层之上。该第三连结导体包括由该第一连结导体与该第二连结导体形成的一硅化物材料。

Description

半导体结构及其制造方法
本申请主张享有于2018年12月6日申请的美国临时申请案第62/776,174号及于2019年1月17日申请的美国正式申请案第16/250,676号的优先权及益处，该美国临时申请案及该美国正式申请案的内容以全文引用的方式并入本文中
技术领域
本发明涉及一种半导体结构及其制造方法，特别涉及一种具有堆叠结构的半导体结构及其制造方法。
背景技术
在许多现代设备中，半导体装置为必备的装置。随着科技的进步，半导体装置逐渐微小化，同时各类电子元件(例如晶体管、二极管、电阻、电容等)的集成密度也逐渐改善。鉴于半导体装置的尺寸逐渐微小化，堆叠的半导体结构被广泛应用于例如封装堆叠(POP)结构、系统级封装(SiP)结构等。
传统半导体结构可包括一第一半导体层与一第二半导体层，第一半导体层与第二半导体层透过两金属导体结合在一起。然而，传统半导体结构的配置也会导致一些问题。例如金属接触电阻具有缺陷、而造成能源耗损增加。
以上关于“现有技术”的说明仅为了提供背景技术，并未承认上述“现有技术”揭示了本发明的目的，且其不构成本发明的现有技术，并且以上关于“现有技术”的任何说明均不应作为本申请的任一部分。
发明内容
本发明提供一种半导体结构的制造方法。该制造方法包括：形成一第一连结导体于一第一半导体层的一第一上表面之上，其中该第一连结导体耦接形成于该第一半导体层中的一第一电子线路结构；形成一第二连结导体于一第二半导体层的一第二上表面上，其中该第二连结导体耦接形成于该第二半导体层中的一第二电子线路结构；以及结合该第一连结导体与该第二连结导体，其中一第三连结导体形成于该第一连结导体与该第二连结导体之间，且该第三连结导体接触该第一连结导体与该第二连结导体。
在一些实施例中，该制造方法包括：形成一第一半导体穿孔于该第一半导体层中，其中该第一半导体穿孔耦接该第一连结导体。
在一些实施例中，该制造方法包括：形成一第二半导体穿孔于该第二半导体层中，其中该第二半导体穿孔耦接该第二连结导体。
在一些实施例中，去除该第一半导体层的一部分，从该第一半导体层的一第一下表面，显露该第一半导体穿孔。
在一些实施例中，该第一电子线路结构包括一第一电子元件以及耦接该第一电子元件的一第一内连接线路，且该第二电子线路结构包括一第二电子元件以及耦接该第二电子元件的一第二内连接线路。
在一些实施例中，该第一电子元件为形成于该第一半导体层的一第一基材上的一第一晶体管，且该第二电子元件包括形成于该第二半导体层的一第二基材上的一第二晶体管。
在一些实施例中，该制造方法包括：形成一第一半导体穿孔，接触该第一内连接线路，其中该第一半导体穿孔由该第一内连接线路朝向该第一半导体层的一第一下表面延伸。
在一些实施例中，该制造方法包括：形成一第一导电接垫以及该第一内连接线路的一第一导电插塞，其中该第一半导体穿孔由该第一导电接垫朝该第一下表面延伸，且该第一导电插塞接触该第一电子元件与该第一导电接垫。
在一些实施例中，该第一连结导体不同于该第二连结导体，该第三连结导体包括由该第一连结导体与该第二连结导体形成的一硅化物材料，该第一连结导体与该第二连结导体的其中一者包括一硅材料、另一者包括一金属材料，且该第三连结导体通过一热处理工艺或一电处理工艺来形成。
在一些实施例中，该制造方法包括：形成一第一介电材料于该第一上表面之上以及形成一第二介电材料于该第二上表面之上，其中，其中该第一连结导体嵌设于该第一介电材料中，该第二连结导体嵌设于该第二介电材料中。
本发明还提供一半导体结构，该半导体结构包括：一第一半导体层，包括一第一上表面与一第一电子线路结构；一第二半导体层，设于该第一半导体层之上，其中该第二半导体层包括一第二上表面以及一第二电子线路结构；一第一连结导体，设于该第一上表面之上，其中该第一连结导体耦接该第一电子线路结构；一第二连结导体，设于该第二上表面之上，其中该第二连结导体耦接该第二电子线路结构；以及一第三连结导体，设于该第一连结导体与该第二连结导体之间，其中该第三连结导体接触该第一连结导体与该第二连结导体。
在一些实施例中，该半导体结构包括一第一半导体穿孔，设于该第一半导体层中，其中该第一半导体穿孔接触该第一电子线路结构，且该第一半导体穿孔由该第一电子线路结构朝向该第一半导体层的一第一下表面延伸。
在一些实施例中，该半导体结构包括一第二半导体穿孔，设于该第二半导体层中，其中该第二半导体穿孔接触该第二电子线路结构，且该第二半导体穿孔由该第二电子线路结构朝向该第二半导体层的一第二下表面延伸。
在一些实施例中，该第一连结导体不同于该第二连结导体，且该第三连结导体包括一硅化物材料，该第一连结导体与该第二连结导体的其中一者包括一硅材料、另一者包括一金属材料。
在一些实施例中，该第一电子线路结构包括一第一电子元件与耦接该第一电子元件的一第一内连接线路，且该第二电子线路结构包括一第二电子元件以及耦接该第二电子元件的一第二内连接线路。
在一些实施例中，该第一电子元件为形成于该第一半导体层的一第一基材上的一第一晶体管，该第二电子元件包括形成于该第二半导体层的一第二基材上的一第二晶体管。
在一些实施例中，该半导体结构包括一第一半导体穿孔，接触该第一内连接线路，其中该第一半导体穿孔由该第一内连接线路朝向该第一半导体层的一第一下表面延伸。
在一些实施例中，该第一内连接线路包括一第一导电接垫与接触该第一导电接垫的一第一导电插塞，其中该第一半导体穿孔由该第一导电接垫朝向该第一下表面延伸，且该第一导电插塞接触该第一电子元件。
在一些实施例中，该第二内连接线路包括一第二导电接垫与接触该第二导电接垫的一第二导电插塞，其中该第二导电插塞接触该第二电子元件。
在一些实施例中，该半导体结构包括一第一介电材料以及一第二介电材料，该第一介电材料设于该第一上表面之上，该第一连结导体嵌设于该第一介电材料中，该第二介电材料设于该第二上表面之上，该第二连结导体嵌设于该第二介电材料中。
通过上述半导体结构，结合的导体可包括至少一硅化物材料。此种设计可有效减少两半导体层之间的接触电阻，进而消耗较少能量。此外，硅化物材料具有较佳的热稳定性。
上文已相当广泛地概述本发明的技术特征及优点，俾使下文的本发明详细描述得以获得较佳了解。构成本发明的申请专利范围目的的其它技术特征及优点将描述于下文。本发明所属技术领域中具有通常知识者应了解，可相当容易地利用下文揭示的概念与特定实施例可作为修改或设计其它结构或工艺而实现与本发明相同的目的。本发明所属技术领域中具有通常知识者亦应了解，这类等效建构无法脱离后附的申请专利范围所界定的本发明的精神和范围。
附图说明
参阅实施方式与申请专利范围合并考量图式时，可得以更全面了解本申请案的揭示内容，图式中相同的元件符号指相同的元件。
图1为流程图，例示本发明一些实施例的半导体结构的制造方法；以及图2至图4为剖面图，例示本发明一些实施例的半导体结构制造方法的过程。
附图标记说明：
100 制造方法
102 操作
104 操作
106 操作
108 操作
200 半导体结构
300 第一半导体层
301 第一上表面
302 第一下表面
304 第一电子线路结构
305 第一电子元件
306 第一内连接线路
307 第一导电接垫
308 第一导电插塞
310 第一半导体穿孔
312 第一基材
350 第一连结导体
352 第一介电材料
400 第二半导体层
401 第二上表面
402 第二下表面
404 第二电子线路结构
405 第二电子元件
406 第二内连接线路
407 第二导电接垫
408 第二导电插塞
410 第二半导体穿孔
412 第二基材
450 第二连结导体
452 第二介电材料
550 第三连结导体
具体实施方式
本发明的以下说明伴随并入且组成说明书的一部分的附图，说明本发明实施例，然而本发明并不受限于该实施例。此外，以下的实施例可适当整合以下实施例以完成另一实施例。
“一实施例”、“实施例”、“例示实施例”、“其他实施例”、“另一实施例”等指的是本发明所描述的实施例可包含特定特征、结构或特性，然而并非每一实施例必须包含该特定特征、结构或是特性。再者，重复使用“在实施例中”一语并非必须指相同实施例，然而可为相同实施例。
本文所使用的术语，仅用于描述特定实施例，并非用于限制本发明概念。如本文中使用的，单数形式“一个(种)”和“所述(该)”也意图包括复数形式，除非上下文清楚地另外指明。可进一步理解的是，当用在本说明书中时，术语“包含”和/或“包括”表明存在所陈述的特征、整体、步骤、操作、元件和/或组成，但是不排除存在或增加一个或多个其它特征、整体、步骤、操作、元件、组成、和/或其集合。
可理解的是，尽管本文可以使用术语“第一”、“第二”、“第三”等来描述各种元件、层、区域、或区段等，但是这些元件、层、区域、或区段等不应该被这些术语所限制。因为这些术语仅是用来区隔不同元件、层、区域、或区段等。所以，在不脱离本发明概念的教示的情况下，举例而言，第一元件、层、区域、或区段亦可以被称为第二元件、层、区域、或区段。
为了使得本发明可被完全理解，以下说明提供详细的步骤与结构。显然，本发明的实施不会限制该技艺中的技术人士已知的特定细节。此外，已知的结构与步骤不再详述，以免不必要地限制本发明。本发明的较佳实施例详述如下。然而，除了实施方式之外，本发明亦可广泛实施于其他实施例中。本发明的范围不限于实施方式的内容，而是由申请专利范围定义。
图1为流程图，例示本发明一些实施例的半导体结构200的制造方法100。图2至图4为剖面图，例示本发明一些实施例的半导体结构200的制造方法100的过程。在一些实施例，制造方法100包括一连串操作(102、104、106与108)，但以下描述或说明并非用以限制操作的顺序。
如图2所示，提供第一半导体层300与第二半导体层400。第一半导体层300具有第一上表面301与第一下表面302。第二半导体层400具有第二上表面401与第二下表面402。
根据制造方法100的操作102，如图2所示，第一连结导体350形成于第一上表面301之上。第一连结导体350耦接形成于第一半导体层300中的第一电子线路结构304。在一些实施例，第一连结导体350可以被扩散阻挡层围绕。
在一些实施例，第一介电材料352形成于第一上表面301之上。第一连结导体350嵌设于第一介电材料352中。在一些实施例，第一介电材料352例如为氧化硅的氧化物。
在一些实施例，第一半导体穿孔310(Through Semiconductor Via,TSV)形成于第一半导体层300中。第一半导体穿孔310耦接第一连结导体350。在一些实施例，第一半导体穿孔310包括填充有导电材料与围绕导电材料的扩散阻挡层的穿孔。
在一些实施例，第一电子线路结构304包括第一电子元件305以及耦接第一电子元件305的第一内连接线路306。在一些实施例，第一电子元件305为形成于第一半导体层300的第一基材312上的第一晶体管。在一些实施例，第一电子元件305可以为其他元件，例如二极管、电阻、电容等。
在一些实施例，第一半导体穿孔310接触第一内连接线路306。第一半导体穿孔310从第一内连接线路306朝向第一下表面302延伸。在一些实施例，第一内连接线路306包括第一导电接垫307与形成于第一半导体层300中的第一导电插塞308。
在一些实施例，第一半导体穿孔310由第一导电接垫307朝向第一下表面302延伸。第一导电插塞308接触第一电子元件305与第一导电接垫307。在一些实施例，第一半导体穿孔310可通过蚀刻、而后沉积等工艺来形成。
根据制造方法100的操作104，如图2所示，第二连结导体450形成于第二半导体层400的第二上表面401。第二连结导体450耦接形成于第二半导体层400中的第二电子线路结构404。
在一些实施例，第二介电材料452形成于第二上表面401之上。第二连结导体450嵌设于第二介电材料452中。在一些实施例，第二介电材料452为氧化硅或其他适合的氧化物。
在一些实施例，第二电子线路结构404包括第二电子元件405及耦接第二电子元件405的第二内连接线路406。在一些实施例，第二半导体穿孔410形成于第二半导体层400中。第二半导体穿孔410耦接第二连结导体450。在一些实施例，第二半导体穿孔410从第二内连接线路406朝向第二下表面402延伸。
在一些实施例，第二电子元件405包括形成于第二半导体层400的第二基材412上的第二晶体管。在一些实施例，第二电子元件405可包括电阻、二极管、电容等。
在一些实施例，第二内连接线路406包括第二导电接垫407与接触第二导电接垫407的第二导电插塞408。第二导电插塞408接触第二电子元件405。在一些实施例，第二导电接垫407以及第二导电插塞408由导电材料形成，例如由铜、硅化物、铝合金、或其他导电材料形成。
根据制造方法100的操作106，如图3所示，结合第一连结导体350与第二连结导体450。第三连结导体550形成于第一连结导体350与第二连结导体450之间。第三连结导体550接触第一连结导体350与第二连结导体450。在一些实施例，结合第一连结导体350与第二连结导体450之前，第一连结导体350与第二连结导体450需对准。
在一些实施例，第一连结导体350不同于第二连结导体450。通过热处理工艺或电处理工艺，第三连结导体550包括由第一连结导体350与第二连结导体450形成的硅化物材料。
在一些实施例，硅化物材料可以为硅化钨、硅化钴、硅化钛、硅化镍、硅化钼、或其组合。在一些实施例，第一连结导体350与第二连结导体450其中一者包括硅材料、另一者包括金属材料，例如钨、钴、钛、镍、钼等。在一些实施例，第一连结导体350与第二连结导体450亦可包括不同的硅化物材料。
根据制造方法100的操作108，如图4所示，从第一半导体层300的第一下表面302去除第一半导体层300的一部分，显露第一半导体穿孔310。在一些实施例，从第二半导体层400的第二下表面402去除第二半导体层400的一部分，显露第二半导体穿孔410。
在一些实施例，制造方法100的操作108可以包括适当的去除工艺，例如磨削工艺、研磨工艺(例如化学机械研磨工艺)、蚀刻工艺等。
在一些实施例，第一半导体穿孔310还可电性连接设于第一下表面302之上的线路重布层(redistribution layer)。在一些实施例，第二半导体穿孔410可另外电性连接金属接垫或设于第二下表面402之上的电路板的锡垫。
如图2-图4所示，本发明提供一种半导体结构200。半导体结构200包括第一半导体层300、第二半导体层400、第一连结导体350、第二连结导体450以及第三连结导体550。第一半导体层300包括第一上表面301与第一电子线路结构304。第二半导体层400设于第一半导体层300之上。第二半导体层400包括第二上表面401与第二电子线路结构404。第一连结导体350设于第一上表面301之上。第一连结导体350耦接第一电子线路结构304。第二连结导体450设于第二上表面401之上。第二连结导体450耦接第二电子线路结构404。第三连结导体550设于第一连结导体350与第二连结导体450之间。第三连结导体550接触第一连结导体350与第二连结导体450。第一连结导体350不同于第二连结导体450。第三连结导体550包括硅化物材料。第一半导体穿孔310设于第一半导体层300中。第一半导体穿孔310接触第一电子线路结构304。第一半导体穿孔310由第一电子线路结构304朝第一下表面302延伸。第二半导体穿孔410设于第二半导体层400中。第二半导体穿孔410接触第二电子线路结构404。第二半导体穿孔410由第二电子线路结构404朝第二下表面402延伸。第一连结导体350与第二连结导体450的其中一者包括硅材料、另一者包括金属材料。第一电子线路结构304包括第一电子元件305与耦接第一电子元件305的第一内连接线路306。第二电子线路结构404包括第二电子元件405与耦接第二电子元件405的第二内连接线路406。第一电子元件305为形成于第一基材312上的第一晶体管，第二电子元件405包括形成于第二基材412上的第二晶体管。第一半导体穿孔310接触第一内连接线路306。第一半导体穿孔310由第一内连接线路306朝向第一下表面302延伸。第一内连接线路306包括第一导电接垫307与接触第一导电接垫307的第一导电插塞308。第一半导体穿孔310从第一导电接垫307朝向第一下表面302延伸。第一导电插塞308接触第一电子元件305。第二内连接线路406包括第二导电接垫407与接触第二导电接垫407的第二导电插塞408。第二导电插塞408接触第二电子元件405。第一介电材料352设于第一上表面301之上。第一连结导体350嵌设于第一介电材料352。第二介电材料452设于第二上表面401之上。第二连结导体450嵌设于第二介电材料452。
总之，通过上述半导体结构，结合的导体可包括至少一硅化物材料。此种设计可有效减少两半导体层之间的接触电阻，进而消耗较少能量。此外，硅化物材料具有较佳的热稳定性。
虽然已详述本发明及其优点，然而应理解可进行各种变化、取代与替代而不脱离本申请权利要求范围所定义的本发明的精神与范围。例如，可用不同的方法实施上述的许多工艺，并且以其他工艺或其组合替代上述的许多工艺。
本发明一方面提供一种半导体结构的制造方法。该制造方法包括：形成一第一连结导体于一第一半导体层的一第一上表面之上，其中该第一连结导体耦接形成于该第一半导体层中的一第一电子线路结构；形成一第二连结导体于一第二半导体层的一第二上表面上，其中该第二连结导体耦接形成于该第二半导体层中的一第二电子线路结构；以及结合该第一连结导体与该第二连结导体，其中一第三连结导体形成于该第一连结导体与该第二连结导体之间，且该第三连结导体接触该第一连结导体与该第二连结导体。
本发明另一方面提供一半导体结构，该半导体结构包括一第一半导体层，包括一第一上表面与一第一电子线路结构；一第二半导体层，设于该第一半导体层之上，其中该第二半导体层包括一第二上表面以及一第二电子线路结构；一第一连结导体，设于该第一上表面之上，其中该第一连结导体耦接该第一电子线路结构；一第二连结导体，设于该第二上表面之上，其中该第二连结导体耦接该第二电子线路结构；以及一第三连结导体，设于该第一连结导体与该第二连结导体之间，其中该第三连结导体接触该第一连结导体与该第二连结导体。
再者，本发明的范围并不受限于说明书中所述的工艺、机械、制造、物质组成物、手段、方法与步骤的特定实施例。本领域技术人员可从本发明所公开的内容理解可根据本发明来使用与本文所述的对应实施例具有相同功能或达到实质相同结果的现有的或未来开发出的工艺、机械、制造、物质组成物、手段、方法、或步骤。据此，这类工艺、机械、制造、物质组成物、手段、方法、或步骤理应被包含于本申请的权利要求的范围内。

Claims (20)

1.一种半导体结构的制造方法，包括：
形成一第一连结导体于一第一半导体层的一第一上表面之上，其中该第一连结导体耦接形成于该第一半导体层中的一第一电子线路结构；
形成一第二连结导体于一第二半导体层的一第二上表面上，其中该第二连结导体耦接形成于该第二半导体层中的一第二电子线路结构；以及
结合该第一连结导体与该第二连结导体，其中一第三连结导体形成于该第一连结导体与该第二连结导体之间，且该第三连结导体接触该第一连结导体与该第二连结导体。
2.如权利要求1所述的制造方法，还包括：
形成一第一半导体穿孔于该第一半导体层中，其中该第一半导体穿孔耦接该第一连结导体。
3.如权利要求2所述的制造方法，还包括：
形成一第二半导体穿孔于该第二半导体层中，其中该第二半导体穿孔耦接该第二连结导体。
4.如权利要求2所述的制造方法，还包括：
去除该第一半导体层的一部分，从该第一半导体层的一第一下表面，显露该第一半导体穿孔。
5.如权利要求1所述的制造方法，其中该第一电子线路结构包括一第一电子元件以及耦接该第一电子元件的一第一内连接线路，且该第二电子线路结构包括一第二电子元件以及耦接该第二电子元件的一第二内连接线路。
6.如权利要求5所述的制造方法，其中该第一电子元件为形成于该第一半导体层的一第一基材上的一第一晶体管，且该第二电子元件包括形成于该第二半导体层的一第二基材上的一第二晶体管。
7.如权利要求5所述的制造方法，还包括：
形成一第一半导体穿孔，接触该第一内连接线路，其中该第一半导体穿孔由该第一内连接线路朝向该第一半导体层的一第一下表面延伸。
8.如权利要求7所述的制造方法，还包括：
形成一第一导电接垫以及该第一内连接线路的一第一导电插塞，其中该第一半导体穿孔由该第一导电接垫朝该第一下表面延伸，且该第一导电插塞接触该第一电子元件与该第一导电接垫。
9.如权利要求1所述的制造方法，其中该第一连结导体不同于该第二连结导体，该第三连结导体包括由该第一连结导体与该第二连结导体形成的一硅化物材料，该第一连结导体与该第二连结导体的其中一者包括一硅材料、另一者包括一金属材料，且该第三连结导体通过一热处理工艺或一电处理工艺来形成。
10.如权利要求1所述的制造方法，还包括：
形成一第一介电材料于该第一上表面之上，其中该第一连结导体嵌设于该第一介电材料中；以及
形成一第二介电材料于该第二上表面之上，其中该第二连结导体嵌设于该第二介电材料中。
11.一种半导体结构，包括：
一第一半导体层，包括一第一上表面与一第一电子线路结构；
一第二半导体层，设于该第一半导体层之上，其中该第二半导体层包括一第二上表面以及一第二电子线路结构；
一第一连结导体，设于该第一上表面之上，其中该第一连结导体耦接该第一电子线路结构；
一第二连结导体，设于该第二上表面之上，其中该第二连结导体耦接该第二电子线路结构；以及
一第三连结导体，设于该第一连结导体与该第二连结导体之间，其中该第三连结导体接触该第一连结导体与该第二连结导体。
12.如权利要求11所述的半导体结构，还包括：
一第一半导体穿孔，设于该第一半导体层中，其中该第一半导体穿孔接触该第一电子线路结构，且该第一半导体穿孔由该第一电子线路结构朝向该第一半导体层的一第一下表面延伸。
13.如权利要求12所述的半导体结构，还包括：
一第二半导体穿孔，设于该第二半导体层中，其中该第二半导体穿孔接触该第二电子线路结构，且该第二半导体穿孔由该第二电子线路结构朝向该第二半导体层的一第二下表面延伸。
14.如权利要求11所述的半导体结构，其中该第一连结导体不同于该第二连结导体，且该第三连结导体包括一硅化物材料，该第一连结导体与该第二连结导体的其中一者包括一硅材料、另一者包括一金属材料。
15.如权利要求11所述的半导体结构，其中该第一电子线路结构包括一第一电子元件与耦接该第一电子元件的一第一内连接线路，且该第二电子线路结构包括一第二电子元件以及耦接该第二电子元件的一第二内连接线路。
16.如权利要求15所述的半导体结构，其中该第一电子元件为形成于该第一半导体层的一第一基材上的一第一晶体管，该第二电子元件包括形成于该第二半导体层的一第二基材上的一第二晶体管。
17.如权利要求15所述的半导体结构，还包括：
一第一半导体穿孔，接触该第一内连接线路，其中该第一半导体穿孔由该第一内连接线路朝向该第一半导体层的一第一下表面延伸。
18.如权利要求17所述的半导体结构，其中该第一内连接线路包括一第一导电接垫与接触该第一导电接垫的一第一导电插塞，其中该第一半导体穿孔由该第一导电接垫朝向该第一下表面延伸，且该第一导电插塞接触该第一电子元件。
19.如权利要求15所述的半导体结构，其中该第二内连接线路包括一第二导电接垫与接触该第二导电接垫的一第二导电插塞，其中该第二导电插塞接触该第二电子元件。
20.如权利要求11所述的半导体结构，还包括：
一第一介电材料，设于该第一上表面之上，其中该第一连结导体嵌设于该第一介电材料中；以及
一第二介电材料，设于该第二上表面之上，其中该第二连结导体嵌设于该第二介电材料中。
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