CN1894783A - 形成半导体装置的矩形间隔物的方法 - Google Patents

形成半导体装置的矩形间隔物的方法 Download PDF

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Publication number
CN1894783A
CN1894783A CNA2004800375007A CN200480037500A CN1894783A CN 1894783 A CN1894783 A CN 1894783A CN A2004800375007 A CNA2004800375007 A CN A2004800375007A CN 200480037500 A CN200480037500 A CN 200480037500A CN 1894783 A CN1894783 A CN 1894783A
Authority
CN
China
Prior art keywords
gate electrode
spacer layer
protective layer
layer
spacer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2004800375007A
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English (en)
Chinese (zh)
Inventor
H·钟
S·达克希纳－穆尔蒂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of CN1894783A publication Critical patent/CN1894783A/zh
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks

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  • Insulated Gate Type Field-Effect Transistor (AREA)
CNA2004800375007A 2003-12-30 2004-10-26 形成半导体装置的矩形间隔物的方法 Pending CN1894783A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/747,680 2003-12-30
US10/747,680 US7022596B2 (en) 2003-12-30 2003-12-30 Method for forming rectangular-shaped spacers for semiconductor devices

Publications (1)

Publication Number Publication Date
CN1894783A true CN1894783A (zh) 2007-01-10

Family

ID=34710826

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2004800375007A Pending CN1894783A (zh) 2003-12-30 2004-10-26 形成半导体装置的矩形间隔物的方法

Country Status (8)

Country Link
US (1) US7022596B2 (https=)
EP (1) EP1704588B1 (https=)
JP (1) JP2007517398A (https=)
KR (1) KR101129712B1 (https=)
CN (1) CN1894783A (https=)
DE (1) DE602004024234D1 (https=)
TW (1) TWI366886B (https=)
WO (1) WO2005069362A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050156229A1 (en) * 2003-12-16 2005-07-21 Yeap Geoffrey C. Integrated circuit device and method therefor
DE102005020133B4 (de) * 2005-04-29 2012-03-29 Advanced Micro Devices, Inc. Verfahren zur Herstellung eines Transistorelements mit Technik zur Herstellung einer Kontaktisolationsschicht mit verbesserter Spannungsübertragungseffizienz
US9111746B2 (en) * 2012-03-22 2015-08-18 Tokyo Electron Limited Method for reducing damage to low-k gate spacer during etching
KR101986538B1 (ko) 2012-09-21 2019-06-07 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9378975B2 (en) 2014-02-10 2016-06-28 Tokyo Electron Limited Etching method to form spacers having multiple film layers
KR102394938B1 (ko) * 2015-05-21 2022-05-09 삼성전자주식회사 반도체 소자 및 반도체 소자의 제조 방법

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59138379A (ja) * 1983-01-27 1984-08-08 Toshiba Corp 半導体装置の製造方法
JPH02265250A (ja) * 1989-04-05 1990-10-30 Nec Corp 半導体装置の製造方法
JP3360480B2 (ja) * 1995-04-06 2002-12-24 ソニー株式会社 半導体装置の製造方法
TW332316B (en) * 1997-07-22 1998-05-21 Holtek Microelectronics Inc Manufacturing method of MOS transistor with adjustable source/drain extension area
JPH1187703A (ja) * 1997-09-10 1999-03-30 Toshiba Corp 半導体装置の製造方法
JPH11204784A (ja) * 1998-01-09 1999-07-30 Toshiba Corp 半導体装置の製造方法
US6323519B1 (en) * 1998-10-23 2001-11-27 Advanced Micro Devices, Inc. Ultrathin, nitrogen-containing MOSFET sidewall spacers using low-temperature semiconductor fabrication process
US6190961B1 (en) * 1999-09-22 2001-02-20 International Business Machines Corporation Fabricating a square spacer
JP4771607B2 (ja) * 2001-03-30 2011-09-14 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US6440875B1 (en) * 2001-05-02 2002-08-27 Taiwan Semiconductor Manufacturing Co., Ltd Masking layer method for forming a spacer layer with enhanced linewidth control
KR100395878B1 (ko) * 2001-08-31 2003-08-25 삼성전자주식회사 스페이서 형성 방법
JP2004014875A (ja) * 2002-06-07 2004-01-15 Fujitsu Ltd 半導体装置及びその製造方法

Also Published As

Publication number Publication date
JP2007517398A (ja) 2007-06-28
TWI366886B (en) 2012-06-21
WO2005069362A1 (en) 2005-07-28
KR101129712B1 (ko) 2012-03-28
US7022596B2 (en) 2006-04-04
US20050146059A1 (en) 2005-07-07
DE602004024234D1 (de) 2009-12-31
TW200525693A (en) 2005-08-01
EP1704588A1 (en) 2006-09-27
EP1704588B1 (en) 2009-11-18
KR20060112676A (ko) 2006-11-01

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Open date: 20070110