CN1415116A - 消除隔离沟槽拐角晶体管器件的间隔层工艺 - Google Patents
消除隔离沟槽拐角晶体管器件的间隔层工艺 Download PDFInfo
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Abstract
一种用于形成防止在晶体管中形成寄生拐角器件的间隔层的方法,所述方法包括:在半导体衬底中蚀刻一些沟槽以便形成有源区;用第一介质材料给所述沟槽和有源区加衬面;用第二介质材料填充所述沟槽以便形成邻近有源区的浅沟槽隔离区。从有源区上去除第一介质材料,并且在有源区和浅沟槽隔离区之间形成有小区的有源区上形成栅极氧化物层。向有源区注入掺杂物形成晶体管的源极和漏极。在注入工序之后,在栅极氧化物层上淀积由第三介质材料形成的间隔层以便填入小区。各向异性地蚀刻间隔层以便在小区中形成间隔层,从而防止栅极导体材料进入小区,并且通过间隔层将栅极导体材料与有源区的拐角分隔开,从而防止形成寄生拐角器件。
Description
背景
1.技术领域
本发明涉及消除在半导体器件的有源区拐角处形成的寄生拐角器件的方法,更具体地说,涉及形成间隔层以提高寄生拐角器件阈值电压的方法。
2.有关技术说明
半导体器件的场效应晶体管(FET)通常包括掺杂的有源区10,在这里FET的源极8和漏极12之间形成沟道14,如图1A和1B所示。当栅极12在适当条件下被激活时,通过栅极12下方的沟道14(以虚线表示)发生源极和漏极之间的电流导通。许多晶体管结构包括这样的有源区10,后者处在相对于邻近该有源区10的隔离区16的不同的高度。由于加工的控制缘故,这些隔离区16可以高于或低于有源区10。
由于有源区10和隔离区16之间的高度差的缘故,在有源区的拐角和在邻近该拐角的小区(divot)20中形成的栅极导体的一部分之间形成了寄生拐角器件18。小区20是在把邻近有源区10的浅沟槽中形成的氮化硅衬层22去除掉时造成的。形成栅极氧化物时,小区20依然存在并充填了栅极12的多晶硅。由拐角器件造成的这种寄生漏电降低了FET的性能,并导致数据错误或FET的误动作。
因此,需要有一种间隔层来充填所述小区,以防止栅极导体进入小区。还需要这种间隔层是在注入有源区而进一步降低了寄生拐角器件的阈值电压之后形成的。
发明概述
根据本发明,一种用于形成防止晶体管中形成寄生拐角器件的间隔层的方法包括:在半导体衬底中蚀刻一些沟槽形成有源区;在沟槽和有源区衬以第一介质材料,并通过在沟槽中填充第二介质材料而形成邻近所述有源区的浅沟槽隔离区。从有源区去除第一介质材料,在有源区和浅沟槽隔离区之间形成小区的有源区上方形成栅极氧化物。把掺杂物注入有源区以形成晶体管的源极和漏极。在注入工序之后,在栅极氧化物上用第三种介质材料形成间隔层以充填小区,然后各向异性地蚀刻所述间隔层以形成小区中的间隔层,以便防止栅极导体材料进入小区,并且靠这些间隔层把栅极导体材料与有源区的拐角隔离,以防止形成寄生拐角器件。
用于形成防止在场效应晶体管中形成寄生拐角器件的间隔层的方法包括以下各步骤:在硅衬底中蚀刻一些沟槽形成有源区;在沟槽和有源区衬以氮化硅,通过在沟槽中填充二氧化硅形成邻近有源区的浅沟槽隔离区;以及从有源区去除氮化硅。在有源区和浅沟槽隔离区之间形成小区的有源区上方形成栅极氧化物。把掺杂物注入有源区以形成场效应晶体管的源极和漏极。在注入工序之后,在栅极氧化物上用第三种介质材料形成间隔层以充填小区,然后各向异性地蚀刻所述间隔层以形成小区中的间隔层,以便防止栅极导体材料进入小区,并且靠这些间隔层把栅极导体材料与有源区的拐角隔离,以防止形成寄生拐角器件。
在另一方法中,可以相对于栅极氧化物对第三种介质材料作选择性的蚀刻。第三种介质材料可以包括氮化物或氧化物。第三种介质材料可以用化学汽相淀积工艺淀积。所述第一种介质材料可以包括氮化硅。所述第二种介质材料可以包括氧化硅。通过在沟槽中填充第二种介质材料形成邻近有源区的浅沟槽隔离区的步骤可以包括以下步骤:这样形成邻近有源区的浅沟槽隔离区、使得有源区配置在第二种介质材料的上表面上。在沟槽中填充第二种介质材料形成邻近有源区的浅沟槽隔离区的步骤可以包括这样形成邻近有源区的浅沟槽隔离区、使得所述有源区配置在所述第二种介质材料的上表面之下的步骤。所述沟槽中可以填充以二氧化硅。所述间隔层的厚度大约为所述有源区宽度的1-3%。
从以下结合附图对说明性的实施例的详细描述可以明白本发明的这些和其他目的、特征和优点。
附图简要说明
本公开将结合以下附图对优选实施例作详细说明,附图中:
图1A是按现有技术具有寄生拐角器件的传统晶体管的截面图;
图1B是在图1A的传统晶体管的截面线1B-1B所取的截面图;
图2是部分制造的半导体器件的截面图,表示本发明的在衬底上形成的掩模层;
图3是图2的半导体器件的截面图,表示本发明的构成图案的掩模层;
图4是图3的半导体器件的截面图,表示在衬底中形成的本发明的浅沟槽隔离区的沟槽;
图5是图4的半导体器件的截面图,表示本发明的淀积的衬层;
图6A和6B是图5的半导体器件的截面图,表示按照本发明填充所述沟槽而分别在有源区之下或有源区之上形成浅沟槽隔离区;
图7A和7B是图6A和6B的半导体器件的截面图,分别表示按照本发明从所述有源区去除所述衬层;
图8A和8B是图7A和7B的半导体器件的截面图,分别表示按照本发明形成的栅极氧化物;
图9A和9B是图8A和8B的半导体器件的截面图,分别表示按照本发明的所述有源区的注入;
图10A和10B是图9A和9B的半导体器件的截面图,分别表示按照本发明形成的充填小区的间隔层;
图11A和11B是图10A和10B的半导体器件的截面图,分别表示按照本发明在所述小区中形成的间隔层;
图12A和12B是图11A和11B的半导体器件的截面图,分别表示按照本发明淀积的栅极导体,后者通过间隔层与所述有源区的拐角隔离;以及
图13是图12A和12B的按照本发明的场效应晶体管的俯视图。
优选实施例的详细说明
本发明涉及防止场效应晶体管中由寄生拐角器件引起的寄生漏电。通过填充在FET的有源区附近形成的小区,避免栅极导电材料进入小区。这导致FET寄生拐角器件的阈值电压急剧增加。按本发明通过在形成充填小区的间隔层之前进行有源区的注入还可以实现进一步的改善。这可进一步提高寄生拐角器件的阈值电压。
现详细参考附图,图中同样的标号在这几个图中代表类似或同一元件,先参阅图2,这是部分制造的半导体器件100的截面图。衬底102最好用单晶硅制成,当然也可采用其他衬底材料。在衬底102上形成掩模层104。掩模层104可包括光致抗蚀剂或介质掩模层。
参阅图3和4,将掩模层104构成图案,以便在衬底102上确定有源区106。在有源区106的相对两侧形成沟槽108。最好用诸如反应离子蚀刻等各向异性蚀刻法蚀刻沟槽。参阅图5,去除掩模层104的余留部分,淀积衬层110以便给沟槽108和有源区106加衬面。衬层110最好包括氮化硅材料。
参阅图6A,沟槽108充填以隔离材料112。隔离材料112最好包括二氧化硅,当然也可用其他介质材料。图6A示出与有源区106大约同等高度的隔离材料112。但隔离材料112也可以低于或高于有源区106,如分别在图6B和6C中示出的。有利的是,本发明可应用于任一种情况。隔离材料112形成浅沟槽隔离区113。
参阅图7A和7B,从有源区106剥去衬层110。于是在有源区106和浅沟槽隔离区113之间形成小区114。
参阅图8A和8B,在有源区106和浅沟槽隔离区113上热生长栅极氧化物层116。这一层填充进了小区114的一部分,但小区118仍留在栅极氧化物层中。传统上,小区116填充有栅极导体材料,形成了寄生拐角器件。
参阅图9A和9B,进行有源区106的注入。有利的是,在引入间隔层(图10A和10B中的120)之前注入掺杂物,这在以后的步骤中作说明。掺杂物注入最好采用本专业的技术人员熟悉的离子注入技术进行。进行注入形成晶体管器件的源极和漏极,还要在沟道区中进行注入(见图1B)。注入掺杂物后形成包括源极124和漏极126的有源区122(图13)。源极和漏极区掺杂物的注入最好在栅极结构形成之后进行以便使源极区和漏极区自对准。
参阅图10A和10B,在浅沟槽隔离区113上的栅极氧化物层上淀积间隔层120。间隔层120可包括氮化物或氧化物。在优选的实施例中,通过化学汽相淀积(CVD)过程淀积间隔层120,当然也可采用其他工艺过程。间隔层120最好是氮化物,例如氮化硅,因为该隔离层可相对于下面的栅极氧化物层116作选择性的蚀刻。如果用氧化物作间隔层120,形成氧化物层的过程(例如CVD)对于相对于栅极氧化物层116蚀刻间隔层120提供了一定的选择性。虽然如果采用氮化物“栅极氧化物”,则二氧化硅作隔离层还是比较好些。间隔层120最好一致地加在栅极氧化物层116上。在优选实施例中,间隔层120的淀积厚度是有源区宽度的大约1%到3%之间以便对小区118有足够的填充。有利的是,在注入有源区106之后淀积间隔层120。这样,间隔层120基本上没有掺杂物,后者会因降低拐角器件的阈值电压而助长寄生拐角器件的形成。
参阅图11A和11B,选择性地蚀刻间隔层120,从栅极氧化物层116上去除材料。蚀刻过程最好是一种各向异性的蚀刻工艺,例如反应离子蚀刻工艺等。按照本发明,通过各向异性地蚀刻间隔层120,在小区118中形成间隔层128。
参阅图12A和12B,在有源区106上淀积与栅极氧化物116和间隔层128接触的一个(一些)栅极导体层130。栅极导体材料最好包括多晶硅。有利的是,本发明不使栅极导体材料层130的任何栅极导体材料进入小区118,而且,增加了有源区106拐角处有源区106和栅极导体层130之间的距离。这样由于栅极导体层130和有源区间的距离增加,寄生拐角器件的生成就会受阻。由于间隔层128是在掺杂物注入之后形成的,所以间隔层128基本上没有掺杂物,这进一步提高拐角器件阈值电压。而且,在间隔层128形成之前注入掺杂物,有源区106就可掺杂得更为均匀,而使有源区的拐角和中间部分之间具有均一的掺杂密度。这种均一性进一步降低了拐角器件的阈值电压。
参阅图13,其中示出场效应晶体管(FET)的俯视图。有源区106包括源极124和漏极126。衬层110将有源区106和浅沟槽隔离区113分隔开。栅极导体层形成FET的栅极。形成寄生器件的拐角以132表示。图2-12B的截面图都是在图13的截面线13-13处截取的。
以上描述了消除拐角晶体管器件的一种新的间隔层工艺的优选实施例(用以说明,而不是限制),应当指出,本专业的技术人员可以根据上述说明作各种修改和变化。因此,显然,在本发明所附的权利要求书的范围和精神之内可对本发明的实施例进行改变。现已按照专利法要求的细节对本发明作了说明,所要求的和希望通过专利证书保护的权利列于所附的权利要求书中。
Claims (16)
1.一种用于形成防止在晶体管中形成寄生拐角器件的间隔层的方法,所述方法包括以下步骤:
在半导体衬底中蚀刻一些沟槽以便形成有源区;
用第一介质材料给所述沟槽和所述有源区加衬面;
通过用第二介质材料填充所述沟槽而形成邻近所述有源区的浅沟槽隔离区;
从所述有源区去除所述第一介质材料;
在所述有源区和所述浅沟槽隔离区之间形成有小区的所述有源区上形成栅极氧化物层;
向所述有源区注入掺杂物以便形成所述晶体管的源极和漏极;
所述注入工序之后,在所述栅极氧化物层上淀积由第三介质材料形成的间隔层以便填充所述小区;
各向异性蚀刻所述间隔层以便在小区中形成间隔层,从而防止栅极导体材料进入所述小区,通过所述间隔层把所述栅极导体材料与所述有源区的拐角分隔开,从而防止形成寄生拐角器件。
2.如权利要求1所述的方法,其特征在于:相对于所述栅极氧化物选择性地蚀刻所述第三介质材料。
3.如权利要求1所述的方法,其特征在于:所述第三介质材料包括氮化物和氧化物中的一种。
4.如权利要求1所述的方法,其特征在于:用化学汽相淀积工艺淀积所述第三介质材料。
5.如权利要求1所述的方法,其特征在于:所述第一介质材料包括氮化硅。
6.如权利要求1所述的方法,其特征在于:所述第二介质材料包括氧化硅。
7.如权利要求1所述的方法,其特征在于:通过在所述沟槽中填充第二种介质材料而形成邻近所述有源区的浅沟槽隔离区的所述步骤包括在所述有源区附近这样形成浅沟槽隔离区、使得所述有源区配置在所述第二介质材料的上表面上方的步骤。
8.如权利要求1所述的方法,其特征在于:通过在所述沟槽中填充第二种介质材料而形成邻近所述有源区的浅沟槽隔离区的所述步骤包括在所述有源区附近这样形成浅沟槽隔离区、使得所述有源区配置在所述第二介质材料的上表面下方的步骤。
9.如权利要求1所述的方法,其特征在于:所述淀积间隔层的步骤包括淀积厚度为所述有源区宽度的约1%至约3%之间的间隔层。
10.一种用于形成防止在场效应晶体管中形成寄生拐角器件的介质间隔层的方法,所述方法包括以下步骤:
在硅衬底中蚀刻一些沟槽以便形成有源区;
用氮化硅给所述沟槽和所述有源区加衬面;
通过用二氧化硅填充所述沟槽而形成邻近所述有源区的浅沟槽隔离区;
从所述有源区去除所述氮化硅;
在所述有源区和所述浅沟槽隔离区之间形成有小区的所述有源区上形成栅极氧化物;
向所述有源区注入掺杂物以便形成所述晶体管的源极和漏极;
在所述注入工序之后,在所述栅极氧化物层上淀积由第三介质材料形成的间隔层、以便填充所述小区;以及
各向异性地蚀刻所述间隔层以便在所述小区中形成间隔层,从而防止栅极导体材料进入所述小区,并且通过所述间隔层将所述栅极导体材料与所述有源区的拐角分隔开,从而防止形成寄生拐角器件。
11.如权利要求10所述的方法,其特征在于:相对于所述栅极氧化物选择性地蚀刻所述第三介质材料。
12.如权利要求10所述的方法,其特征在于:所述第三介质材料包括氮化物和氧化物中的一种。
13.如权利要求10所述的方法,其特征在于:用化学汽相淀积工艺淀积所述第三介质材料。
14.如权利要求10所述的方法,其特征在于:通过在所述沟槽中填充二氧化硅而形成邻近所述有源区的浅沟槽隔离区的所述步骤包括在所述有源区附近这样形成浅沟槽隔离区、使得所述有源区配置在所述二氧化硅的上表面上方的步骤。
15.如权利要求10所述的方法,其特征在于:通过在所述沟槽中填充二氧化硅而形成邻近所述有源区的浅沟槽隔离区的所述步骤包括在所述有源区附近这样形成浅沟槽隔离区、使得所述有源区配置在所述二氧化硅的上表面下方的步骤。
16.如权利要求10所述的方法,其特征在于:所述淀积间隔层的步骤包括淀积厚度为所述有源区宽度的约1%至约3%之间的间隔层。
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US09/432,063 US6207513B1 (en) | 1999-11-02 | 1999-11-02 | Spacer process to eliminate corner transistor device |
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Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
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DE10131710B4 (de) * | 2001-06-29 | 2006-05-18 | Infineon Technologies Ag | Verfahren zur gezielten Einstellung der Stufenhöhe bei der STI-Technik zur Herstellung von integrierten Schaltungen |
US6524938B1 (en) | 2002-02-13 | 2003-02-25 | Taiwan Semiconductor Manufacturing Company | Method for gate formation with improved spacer profile control |
US6909152B2 (en) * | 2002-11-14 | 2005-06-21 | Infineon Technologies, Ag | High density DRAM with reduced peripheral device area and method of manufacture |
US6750117B1 (en) * | 2002-12-23 | 2004-06-15 | Macronix International Co., Ltd. | Shallow trench isolation process |
JP2010034468A (ja) * | 2008-07-31 | 2010-02-12 | Renesas Technology Corp | 半導体装置及びその製造方法 |
KR200457825Y1 (ko) * | 2009-03-18 | 2012-01-05 | 김통일 | 자외선 살균기 |
US8105893B2 (en) * | 2009-11-18 | 2012-01-31 | International Business Machines Corporation | Diffusion sidewall for a semiconductor structure |
CN103681271B (zh) * | 2012-09-04 | 2016-05-25 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件结构及其制作方法 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02113548A (ja) * | 1988-10-21 | 1990-04-25 | Mitsubishi Electric Corp | 半導体装置 |
JP2946920B2 (ja) * | 1992-03-09 | 1999-09-13 | 日本電気株式会社 | 半導体装置の製造方法 |
JPH05259450A (ja) * | 1992-03-12 | 1993-10-08 | Mitsubishi Electric Corp | 半導体装置及び製造方法 |
US5433794A (en) * | 1992-12-10 | 1995-07-18 | Micron Technology, Inc. | Spacers used to form isolation trenches with improved corners |
JPH06342846A (ja) * | 1993-04-07 | 1994-12-13 | Mitsubishi Electric Corp | トレンチ分離構造を有する半導体装置およびその製造方法 |
US5358891A (en) * | 1993-06-29 | 1994-10-25 | Intel Corporation | Trench isolation with planar topography and method of fabrication |
US5387540A (en) * | 1993-09-30 | 1995-02-07 | Motorola Inc. | Method of forming trench isolation structure in an integrated circuit |
US5447884A (en) * | 1994-06-29 | 1995-09-05 | International Business Machines Corporation | Shallow trench isolation with thin nitride liner |
US5436190A (en) | 1994-11-23 | 1995-07-25 | United Microelectronics Corporation | Method for fabricating semiconductor device isolation using double oxide spacers |
US5521422A (en) | 1994-12-02 | 1996-05-28 | International Business Machines Corporation | Corner protected shallow trench isolation device |
JPH08330410A (ja) * | 1995-05-31 | 1996-12-13 | Sony Corp | 素子分離方法、素子分離構造、及び半導体装置 |
US5899727A (en) | 1996-05-02 | 1999-05-04 | Advanced Micro Devices, Inc. | Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization |
US5777370A (en) * | 1996-06-12 | 1998-07-07 | Advanced Micro Devices, Inc. | Trench isolation of field effect transistors |
US5923991A (en) | 1996-11-05 | 1999-07-13 | International Business Machines Corporation | Methods to prevent divot formation in shallow trench isolation areas |
US5763315A (en) | 1997-01-28 | 1998-06-09 | International Business Machines Corporation | Shallow trench isolation with oxide-nitride/oxynitride liner |
US5741740A (en) | 1997-06-12 | 1998-04-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Shallow trench isolation (STI) method employing gap filling silicon oxide dielectric layer |
JPH1187490A (ja) * | 1997-07-14 | 1999-03-30 | Sony Corp | 半導体装置およびその製造方法 |
US6093619A (en) * | 1998-06-18 | 2000-07-25 | Taiwan Semiconductor Manufaturing Company | Method to form trench-free buried contact in process with STI technology |
TW444333B (en) * | 1998-07-02 | 2001-07-01 | United Microelectronics Corp | Method for forming corner rounding of shallow trench isolation |
US5950090A (en) * | 1998-11-16 | 1999-09-07 | United Microelectronics Corp. | Method for fabricating a metal-oxide semiconductor transistor |
JP2000223704A (ja) * | 1999-01-29 | 2000-08-11 | Sony Corp | 半導体装置およびその製造方法 |
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