DE602004024234D1 - Verfahren zur bildung rechteckförmiger abstandselemente für halbleiterbauelemente - Google Patents

Verfahren zur bildung rechteckförmiger abstandselemente für halbleiterbauelemente

Info

Publication number
DE602004024234D1
DE602004024234D1 DE602004024234T DE602004024234T DE602004024234D1 DE 602004024234 D1 DE602004024234 D1 DE 602004024234D1 DE 602004024234 T DE602004024234 T DE 602004024234T DE 602004024234 T DE602004024234 T DE 602004024234T DE 602004024234 D1 DE602004024234 D1 DE 602004024234D1
Authority
DE
Germany
Prior art keywords
semiconductor components
spacer elements
forming rectangular
rectangular spacer
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602004024234T
Other languages
German (de)
English (en)
Inventor
Huicai Zhong
Srikanteswara Dakshina-Murthy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE602004024234D1 publication Critical patent/DE602004024234D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00Bonding of wafers, substrates or parts of devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/021Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00Ion implantation into wafers, substrates or parts of devices
    • H10P30/20Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
DE602004024234T 2003-12-30 2004-10-26 Verfahren zur bildung rechteckförmiger abstandselemente für halbleiterbauelemente Expired - Lifetime DE602004024234D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/747,680 US7022596B2 (en) 2003-12-30 2003-12-30 Method for forming rectangular-shaped spacers for semiconductor devices
PCT/US2004/035407 WO2005069362A1 (en) 2003-12-30 2004-10-26 A method for forming rectangular-shape spacers for semiconductor devices

Publications (1)

Publication Number Publication Date
DE602004024234D1 true DE602004024234D1 (de) 2009-12-31

Family

ID=34710826

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004024234T Expired - Lifetime DE602004024234D1 (de) 2003-12-30 2004-10-26 Verfahren zur bildung rechteckförmiger abstandselemente für halbleiterbauelemente

Country Status (8)

Country Link
US (1) US7022596B2 (https=)
EP (1) EP1704588B1 (https=)
JP (1) JP2007517398A (https=)
KR (1) KR101129712B1 (https=)
CN (1) CN1894783A (https=)
DE (1) DE602004024234D1 (https=)
TW (1) TWI366886B (https=)
WO (1) WO2005069362A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050156229A1 (en) * 2003-12-16 2005-07-21 Yeap Geoffrey C. Integrated circuit device and method therefor
DE102005020133B4 (de) * 2005-04-29 2012-03-29 Advanced Micro Devices, Inc. Verfahren zur Herstellung eines Transistorelements mit Technik zur Herstellung einer Kontaktisolationsschicht mit verbesserter Spannungsübertragungseffizienz
US9111746B2 (en) * 2012-03-22 2015-08-18 Tokyo Electron Limited Method for reducing damage to low-k gate spacer during etching
KR101986538B1 (ko) 2012-09-21 2019-06-07 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9378975B2 (en) 2014-02-10 2016-06-28 Tokyo Electron Limited Etching method to form spacers having multiple film layers
KR102394938B1 (ko) * 2015-05-21 2022-05-09 삼성전자주식회사 반도체 소자 및 반도체 소자의 제조 방법

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59138379A (ja) * 1983-01-27 1984-08-08 Toshiba Corp 半導体装置の製造方法
JPH02265250A (ja) * 1989-04-05 1990-10-30 Nec Corp 半導体装置の製造方法
JP3360480B2 (ja) * 1995-04-06 2002-12-24 ソニー株式会社 半導体装置の製造方法
TW332316B (en) * 1997-07-22 1998-05-21 Holtek Microelectronics Inc Manufacturing method of MOS transistor with adjustable source/drain extension area
JPH1187703A (ja) * 1997-09-10 1999-03-30 Toshiba Corp 半導体装置の製造方法
JPH11204784A (ja) * 1998-01-09 1999-07-30 Toshiba Corp 半導体装置の製造方法
US6323519B1 (en) * 1998-10-23 2001-11-27 Advanced Micro Devices, Inc. Ultrathin, nitrogen-containing MOSFET sidewall spacers using low-temperature semiconductor fabrication process
US6190961B1 (en) * 1999-09-22 2001-02-20 International Business Machines Corporation Fabricating a square spacer
JP4771607B2 (ja) * 2001-03-30 2011-09-14 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US6440875B1 (en) * 2001-05-02 2002-08-27 Taiwan Semiconductor Manufacturing Co., Ltd Masking layer method for forming a spacer layer with enhanced linewidth control
KR100395878B1 (ko) * 2001-08-31 2003-08-25 삼성전자주식회사 스페이서 형성 방법
JP2004014875A (ja) * 2002-06-07 2004-01-15 Fujitsu Ltd 半導体装置及びその製造方法

Also Published As

Publication number Publication date
JP2007517398A (ja) 2007-06-28
TWI366886B (en) 2012-06-21
WO2005069362A1 (en) 2005-07-28
KR101129712B1 (ko) 2012-03-28
US7022596B2 (en) 2006-04-04
US20050146059A1 (en) 2005-07-07
CN1894783A (zh) 2007-01-10
TW200525693A (en) 2005-08-01
EP1704588A1 (en) 2006-09-27
EP1704588B1 (en) 2009-11-18
KR20060112676A (ko) 2006-11-01

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