CN1716562A - 单元晶体管的制造方法 - Google Patents

单元晶体管的制造方法 Download PDF

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CN1716562A
CN1716562A CNA2005100080261A CN200510008026A CN1716562A CN 1716562 A CN1716562 A CN 1716562A CN A2005100080261 A CNA2005100080261 A CN A2005100080261A CN 200510008026 A CN200510008026 A CN 200510008026A CN 1716562 A CN1716562 A CN 1716562A
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郑泰旿
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SK Hynix Inc
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Abstract

公开了一种与高集成度的DRAM存储器单元有关的单元晶体管的制造方法，该方法改善了单元晶体管的短沟道效应，同时改进了所述晶体管的刷新特性，还能够防止晶体管阈值电压的下降。该方法包括以下步骤：在硅衬底上形成界定器件分离区的器件隔离区；在形成有器件隔离区的衬底上形成阻挡层；在形成有阻挡层的衬底上形成界定栅极形成区的硬掩模；通过构成衬底表面的硅的选择性外延生长，在形成有硬掩模和阻挡层的衬底的表面上形成硅外延层；以及，去除硬掩模。

Description

单元晶体管的制造方法
技术领域
本发明涉及一种单元晶体管的制造方法，尤其涉及一种与高集成度的DRAM存储器单元有关的单元晶体管的制造方法，该方法改善了单元晶体管的短沟道效应，同时改进了所述晶体管的刷新特性，还防止了晶体管阈值电压的下降。
背景技术
在由高集成度的DRAM存储器单元引起的半导体器件设计规则减小的趋势下，单元晶体管的尺寸和沟道长度不断减小。减小的沟道长度使得晶体管的短沟道效应恶化，因此导致了DRAM存储器单元阈值电压的降低和刷新特性的恶化。
最近，为了解决以上问题，研究了一种具有凹槽栅极(recess gate)的晶体管。
考虑具有凹槽栅极的晶体管的传统制造方法，首先，在硅衬底上形成器件隔离区(device isolation region)，其中所述衬底被分为有源区和器件隔离区。然后，界定栅极形成区的掩模形成在有源区中的衬底上。利用所述掩模作为蚀刻掩模，硅衬底被蚀刻预设厚度以形成沟槽。在蚀刻完成后，在衬底的沟槽上执行常规的栅极形成工艺，由此获得栅极图案。此处，栅极图案包括栅极氧化膜、栅电极和硬掩模。为了在如蚀刻、清洗等后续工艺中保护所得栅极图案，最后在栅极图案的侧壁形成绝缘间隔壁。
如上所述，在根据现有技术所制造的具有凹槽栅极的晶体管中，作为在位于有源区的栅极形成区内的硅衬底上形成具有预设深度的沟槽的结果，获得了沿沟槽的剖面(profile)变长的沟道，因此使半导体器件的高集成度所致的短沟道效应最小化。
然而，以上所述的沟槽形成方法具有难点，由于所述沟槽的蚀刻必须在对应于硅衬底有源区中的栅极形成区的特定部分上选择性地执行，而不能损害将硅衬底分为器件分离区(device separating region)和有源区的器件隔离区。结果，在与器件隔离区相邻的衬底上形成了尖的硅突起(siliconprotrusion)。硅突起扩展了电场，导致DRAM存储器单元的刷新特性恶化。
发明内容
因此，鉴于以上问题而提出本发明，本发明的一个目的是提供一种单元晶体管的制造方法，该方法可以改善由高集成度引起的单元晶体管的短沟道效应，同时改进晶体管的刷新特性，还能防止晶体管阈值电压的下降。
依照本发明的一个方面，上述和其它目的可通过提供一种单元晶体管的制造方法来实现，该方法包括以下步骤：a)在硅衬底上形成器件隔离区；b)在形成有器件隔离区的衬底上形成阻挡层(barrier layer)；c)在形成有阻挡层的衬底上形成界定栅极形成区的硬掩模；d)通过构成衬底表面的硅的选择性外延生长，在形成有硬掩模和阻挡层的衬底的表面上形成硅外延层；以及e)去除硬掩模。
当通过选择性外延生长形成厚度为100至2000埃的硅外延层时，为了限制硅外延层的横向生长，优选的是，阻挡层由基于氧化物材料制成并且厚度为100至2000埃，硬掩模由基于氮化物的材料制成并且厚度为100至2000埃。
附图说明
通过以下结合附图的详细描述，本发明的上述和其它目的、特性以及优点将变得更加清楚，附图中：
图1a至1g是根据本发明一实施例的单元晶体管制造方法的顺序步骤的前剖面图；以及
图2是根据本发明实施例的方法所制造的单元晶体管结构的示意性前剖面图。
具体实施方式
以下，将参照附图对本发明的优选实施例进行详细解释以使得本领域技术人员较容易地实现本发明。然而，应理解的是，本发明可通过多种不同方式实施，而不限于在此描述的实施例。
在附图中，根据本发明的晶体管单元的各层以放大的尺寸表示从而清楚地描述其区域，在整个说明书中，类似的部分用相同的附图标记表示。
下面将参照附图详细解释根据本发明实施例的单元晶体管的制造方法。
图1a至1g是根据本发明实施例的晶体管单元制造方法的顺序工序的前剖面图。
首先参照图1a，利用器件隔离区形成工艺，例如，浅沟槽隔离(STI)工艺，在衬底100中形成器件隔离区110。器件隔离区110将衬底100分为器件分离区和有源区。
接下来，如图1b所示，基于氧化物的材料，例如，LP-TEOS、HDP和USG，以100至2000埃的厚度被淀积在衬底100的整个顶表面上，从而形成氧化膜120。
接着，在氧化膜120上形成第一感光膜图案130，其界定用于保护器件分离区的阻挡层形成区。通过利用第一感光膜图案130作为蚀刻掩模，氧化膜120被选择性蚀刻，从而形成由基于氧化物的材料构成的阻挡层125。这种情况下，阻挡层125位于器件隔离区110上，器件隔离区110界定了衬底100的器件分离区，并用于防止在以下将描述的硅的选择性外延生长工艺中朝向器件分离区的硅的横向生长。
参照图1d，在形成有阻挡层125的硅衬底100的整个表面，基于氮化物的材料被淀积到100至2000埃的厚度，从而形成氮化物膜140，并且又在氮化物膜140上，形成界定栅极形成区的第二感光膜图案150。
之后，如图1e所示，通过利用第二感光膜图案150作为蚀刻掩模，选择性蚀刻氮化物膜140以形成硬掩模145。这种情况下，硬掩模145位于衬底上器件隔离区和有源区两者的上方，并界定了栅极形成区。特别地，位于有源区上的部分硬掩模145成形为界定确保栅极沟道长度的沟槽的外形。更具体地，衬底100顶表面上的硬掩模145的厚度为100至2000埃。这使得将在后续工艺中形成的沟槽具有100至2000埃的深度。
参照图1f，通过构成衬底表面的硅的选择性外延生长，形成有硬掩模145的衬底100的表面形成了硅外延层160。这种情况下，由于保护器件分离区的阻挡层125和屏蔽栅极形成区的硬掩模145，限制了硅外延层160的横向生长，因而只向上生长到100至2000埃的厚度。
如图1g所示，由于硬掩模145被去除，在衬底100的有源区中形成深度为100至2000埃的沟槽170。
接着，在衬底100的器件隔离区110和沟槽170上执行常规的栅极形成工艺，由此形成栅极图案180。这里，栅极图案180包括栅极氧化膜、栅电极和硬掩模。为了在例如蚀刻和清洗等后续工艺中保护所得的栅极图案180，最后在栅极图案180的侧壁形成绝缘间隔壁190(见图2)。
如上所述，在本发明的沟槽形成工艺中，使用选择性外延生长方法来取代蚀刻方法。这具有避免由蚀刻方法引起的在邻近器件隔离区的衬底上产生尖的硅突起的效果，实现了DRAM存储器单元刷新特性的提高。
从上述描述中可以清楚的看到，本发明提供了一种晶体管单元的制造方法，其中利用选择性外延生长工艺而不是蚀刻工艺，来形成确保栅极沟道长度的沟槽，改善了DRAM存储器单元的刷新特性和短沟道效应。
此外，根据本发明，通过改善短沟道效应，阈值电压的降低被最小化。
尽管为了说明的目的公开了参照本发明的优选实施例，但本领域技术人员应当理解，在不脱离由所附权利要求所公开的本发明的精神和范围的前提下，可以对本发明进行各种修改、添加和替换。

Claims (4)

1.一种单元晶体管的制造方法，包括下列步骤：
a)在硅衬底上形成器件隔离区；
b)在形成有器件隔离区的所述衬底上形成阻挡层；
c)在形成有所述阻挡层的所述衬底上形成界定栅极形成区的硬掩模；
d)通过构成所述衬底的表面的硅的选择性外延生长，在形成有所述硬掩模和所述阻挡层的衬底的表面上形成硅外延层；以及
e)去除所述硬掩模。
2.如权利要求1所述的方法，其中所述阻挡层由基于氧化物的材料制成并具有100至2000埃的厚度。
3.如权利要求1所述的方法，其中所述硬掩模由基于氮化物的材料制成并具有100至2000埃的厚度。
4.如权利要求1所述的方法，其中通过选择性外延生长将所述硅外延层形成为100至2000埃的厚度。
CNB2005100080261A 2004-06-14 2005-02-07 单元晶体管的制造方法 Expired - Fee Related CN100370594C (zh)

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Publication number Priority date Publication date Assignee Title
CN101685793A (zh) * 2008-09-22 2010-03-31 海力士半导体有限公司 制造半导体器件的方法
CN105551969A (zh) * 2016-02-05 2016-05-04 杭州士兰集成电路有限公司 一种恒流二极管结构及其形成方法
CN105551969B (zh) * 2016-02-05 2018-12-11 成都士兰半导体制造有限公司 一种恒流二极管结构及其形成方法

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