CN1889192A - 半导体存储器和半导体存储器的预烧测试方法 - Google Patents
半导体存储器和半导体存储器的预烧测试方法 Download PDFInfo
- Publication number
- CN1889192A CN1889192A CNA2005101237091A CN200510123709A CN1889192A CN 1889192 A CN1889192 A CN 1889192A CN A2005101237091 A CNA2005101237091 A CN A2005101237091A CN 200510123709 A CN200510123709 A CN 200510123709A CN 1889192 A CN1889192 A CN 1889192A
- Authority
- CN
- China
- Prior art keywords
- burn
- bit line
- testing
- signal
- test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/06—Acceleration testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0405—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals comprising complete test loop
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1204—Bit line control
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/36—Data generation devices, e.g. data inverters
- G11C2029/3602—Pattern generator
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
Description
Claims (10)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005187389A JP4261515B2 (ja) | 2005-06-27 | 2005-06-27 | 半導体メモリのバーンイン試験方法 |
JP2005187389 | 2005-06-27 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1889192A true CN1889192A (zh) | 2007-01-03 |
CN100570750C CN100570750C (zh) | 2009-12-16 |
Family
ID=37567164
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2005101237091A Expired - Fee Related CN100570750C (zh) | 2005-06-27 | 2005-11-18 | 半导体存储器和半导体存储器的预烧测试方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7200059B2 (zh) |
JP (1) | JP4261515B2 (zh) |
KR (1) | KR100750576B1 (zh) |
CN (1) | CN100570750C (zh) |
TW (1) | TWI287231B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114076889A (zh) * | 2021-11-18 | 2022-02-22 | 长江存储科技有限责任公司 | 测试系统和测试方法 |
WO2024060405A1 (zh) * | 2022-09-23 | 2024-03-28 | 长鑫存储技术有限公司 | 动态随机存储器测试方法及装置 |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7587645B2 (en) * | 2005-01-24 | 2009-09-08 | Samsung Electronics Co., Ltd. | Input circuit of semiconductor memory device and test system having the same |
KR100655085B1 (ko) * | 2006-01-27 | 2006-12-08 | 삼성전자주식회사 | 비트라인 전압 커플링 감소기능을 갖는 반도체 메모리 장치 |
KR100916009B1 (ko) | 2007-06-26 | 2009-09-10 | 삼성전자주식회사 | 반도체 메모리 장치의 테스트 회로 및 테스트 방법 |
JP5629962B2 (ja) * | 2008-01-30 | 2014-11-26 | 富士通セミコンダクター株式会社 | 半導体記憶装置 |
KR20100097228A (ko) * | 2008-01-30 | 2010-09-02 | 쿄세라 코포레이션 | 무선 통신 시스템, 무선 통신 장치 및 통신 제어 방법 |
JP2010182350A (ja) * | 2009-02-03 | 2010-08-19 | Renesas Electronics Corp | 半導体記憶装置 |
US8386867B2 (en) * | 2009-07-02 | 2013-02-26 | Silicon Image, Inc. | Computer memory test structure |
US8543873B2 (en) | 2010-01-06 | 2013-09-24 | Silicon Image, Inc. | Multi-site testing of computer memory devices and serial IO ports |
KR102245131B1 (ko) * | 2014-10-23 | 2021-04-28 | 삼성전자 주식회사 | 프로그램 가능한 신뢰성 에이징 타이머를 이용하는 장치 및 방법 |
KR20160117857A (ko) * | 2015-03-31 | 2016-10-11 | 에스케이하이닉스 주식회사 | 반도체장치 및 반도체시스템 |
US9865360B2 (en) * | 2015-10-22 | 2018-01-09 | Sandisk Technologies Llc | Burn-in memory testing |
US9904758B2 (en) * | 2016-05-18 | 2018-02-27 | Samsung Electronics Co., Ltd. | Using deep sub-micron stress effects and proximity effects to create a high performance standard cell |
US10566034B1 (en) * | 2018-07-26 | 2020-02-18 | Winbond Electronics Corp. | Memory device with control and test circuit, and method for test reading and writing using bit line precharge voltage levels |
WO2020063413A1 (en) * | 2018-09-28 | 2020-04-02 | Changxin Memory Technologies, Inc. | Chip and chip test system |
CN115686978B (zh) * | 2023-01-04 | 2023-03-21 | 深圳市大晶光电科技有限公司 | 一种老化测试方法、系统以及pcb板 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3863968B2 (ja) | 1997-06-10 | 2006-12-27 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
JPH11260054A (ja) * | 1998-01-08 | 1999-09-24 | Mitsubishi Electric Corp | ダイナミック型半導体記憶装置 |
JP4587500B2 (ja) | 1998-11-11 | 2010-11-24 | ルネサスエレクトロニクス株式会社 | 半導体集積回路、メモリモジュール、記憶媒体、及び半導体集積回路の救済方法 |
JP4623355B2 (ja) * | 2003-04-01 | 2011-02-02 | ソニー株式会社 | 半導体記憶装置及び半導体記憶装置の記憶再生方法 |
JP2004355720A (ja) | 2003-05-29 | 2004-12-16 | Sony Corp | 半導体メモリ装置 |
-
2005
- 2005-06-27 JP JP2005187389A patent/JP4261515B2/ja not_active Expired - Fee Related
- 2005-10-26 TW TW094137478A patent/TWI287231B/zh not_active IP Right Cessation
- 2005-10-28 US US11/260,486 patent/US7200059B2/en not_active Expired - Fee Related
- 2005-11-02 KR KR1020050104222A patent/KR100750576B1/ko not_active IP Right Cessation
- 2005-11-18 CN CNB2005101237091A patent/CN100570750C/zh not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114076889A (zh) * | 2021-11-18 | 2022-02-22 | 长江存储科技有限责任公司 | 测试系统和测试方法 |
WO2024060405A1 (zh) * | 2022-09-23 | 2024-03-28 | 长鑫存储技术有限公司 | 动态随机存储器测试方法及装置 |
Also Published As
Publication number | Publication date |
---|---|
KR20070000326A (ko) | 2007-01-02 |
KR100750576B1 (ko) | 2007-08-21 |
TWI287231B (en) | 2007-09-21 |
TW200701244A (en) | 2007-01-01 |
JP4261515B2 (ja) | 2009-04-30 |
US7200059B2 (en) | 2007-04-03 |
US20060291307A1 (en) | 2006-12-28 |
CN100570750C (zh) | 2009-12-16 |
JP2007004953A (ja) | 2007-01-11 |
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Legal Events
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: FUJITSU MICROELECTRONICS CO., LTD. Free format text: FORMER OWNER: FUJITSU LIMITED Effective date: 20081024 |
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C41 | Transfer of patent application or patent right or utility model | ||
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Effective date of registration: 20081024 Address after: Tokyo, Japan, Japan Applicant after: Fujitsu Microelectronics Ltd. Address before: Kanagawa Applicant before: Fujitsu Ltd. |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C56 | Change in the name or address of the patentee |
Owner name: FUJITSU SEMICONDUCTORS CO., LTD Free format text: FORMER NAME: FUJITSU MICROELECTRON CO., LTD. |
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CP03 | Change of name, title or address |
Address after: Kanagawa Patentee after: Fujitsu Semiconductor Co., Ltd. Address before: Tokyo, Japan, Japan Patentee before: Fujitsu Microelectronics Ltd. |
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ASS | Succession or assignment of patent right |
Owner name: SUOSI FUTURE CO., LTD. Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR CO., LTD. Effective date: 20150520 |
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C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20150520 Address after: Kanagawa Patentee after: Co., Ltd. Suo Si future Address before: Kanagawa Patentee before: Fujitsu Semiconductor Co., Ltd. |
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CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20091216 Termination date: 20181118 |