WO2024060405A1 - 动态随机存储器测试方法及装置 - Google Patents

动态随机存储器测试方法及装置 Download PDF

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Publication number
WO2024060405A1
WO2024060405A1 PCT/CN2022/136296 CN2022136296W WO2024060405A1 WO 2024060405 A1 WO2024060405 A1 WO 2024060405A1 CN 2022136296 W CN2022136296 W CN 2022136296W WO 2024060405 A1 WO2024060405 A1 WO 2024060405A1
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Prior art keywords
voltage
inverter
storage capacitor
transistor
substrate
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PCT/CN2022/136296
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English (en)
French (fr)
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章恒嘉
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长鑫存储技术有限公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/32—Serial access; Scan testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage

Definitions

  • the present disclosure relates to the field of memory technology, and specifically to a dynamic random access memory testing method and device.
  • the aging test of Dynamic Random Access Memory (DRAM) chips eliminates early failures by controlling the working status of the chip and applying temperature stress.
  • the main purpose of the burn-in test vector is to increase the test stress inside the part, improve the burn-in efficiency, and promote the occurrence of device abnormalities, so as to eliminate unqualified products at an early stage.
  • the purpose of this disclosure is to provide a dynamic random access memory testing method and device.
  • a dynamic random access memory testing method including: the dynamic random access memory includes a substrate and a plurality of storage units, each storage unit includes a storage capacitor and a first transistor, and the first transistor is an NMOS transistor, the first plate of the storage capacitor of each memory unit is electrically connected to the drain of the corresponding first transistor, and the P-type silicon substrate of the first transistor of each memory unit is electrically connected to the substrate.
  • the method includes: A first voltage is applied to the substrate, and a second voltage is applied to the second plate of the storage capacitor of each storage unit to charge the storage capacitor of each storage unit. The first voltage is higher than the third voltage. Two voltages; after the storage capacitor of each storage unit is charged for a predetermined period of time, a read operation is performed on each storage unit to perform an aging test on the dynamic random access memory.
  • charging the storage capacitor of each storage unit includes: applying the voltage to The input terminal of the switching circuit sends a first input signal to switch the voltage applied on the substrate from the third voltage to the first voltage, and to switch the voltage applied on the second plate of each storage capacitor from The fourth voltage is switched to the second voltage to charge the storage capacitor of each storage unit; wherein the third voltage is lower than the first voltage, and the fourth voltage is higher than the second voltage, so The fourth voltage is higher than the third voltage.
  • the voltage switching circuit includes a first inverter and a second inverter, and the input terminal of the first inverter is connected to the input terminal of the second inverter;
  • a first input signal is sent to the input terminal of the voltage switching circuit to switch the voltage applied on the substrate from a third voltage to the first voltage, and to switch the voltage applied on the second plate of each storage capacitor.
  • Switching the voltage from the fourth voltage to the second voltage includes: sending the first input signal to a common input terminal of the first inverter and the second inverter to pass the first inverter.
  • the inverter switches the voltage applied on the substrate from the third voltage to the first voltage, and the voltage applied on the second plate of each storage capacitor is switched from the second inverter to the first voltage.
  • the fourth voltage is switched to the second voltage.
  • performing a read operation on each storage unit after the storage capacitor of each storage unit is charged for a predetermined period of time includes: switching to the voltage after the storage capacitor of each storage unit is charged for a predetermined period of time.
  • the input terminal of the circuit sends a second input signal to switch the voltage applied on the substrate from the first voltage to the third voltage and to switch the voltage applied on the second plate of each storage capacitor. Switching from the second voltage to the fourth voltage.
  • the voltage switching circuit includes a first inverter and a second inverter, and the first inverter and the second inverter share an input terminal; switching to the voltage The input terminal of the circuit sends a second input signal to switch the voltage applied on the substrate from the first voltage to the third voltage and to switch the voltage applied on the second plate of each storage capacitor.
  • Switching from the second voltage to the fourth voltage includes: sending the second input signal to a common input terminal of the first inverter and the second inverter to pass the first An inverter switches the voltage applied on the substrate from the first voltage to the third voltage, and switches the voltage applied on the second plate of each storage capacitor from the second voltage to the fourth voltage.
  • the method further includes: obtaining area sizes of the plurality of memory cells; determining a voltage difference between the first voltage and the second voltage according to the area sizes of the plurality of memory cells, to The first voltage and the second voltage are obtained.
  • a dynamic random access memory testing device including: the dynamic random access memory includes a substrate and a plurality of storage units, each storage unit includes a storage capacitor and a first transistor, and the first transistor is NMOS transistor, the first plate of the storage capacitor of each memory unit is electrically connected to the drain of the corresponding first transistor, and the P-type silicon substrate of the first transistor of each memory unit is electrically connected to the substrate.
  • the device includes: A control module configured to charge the storage capacitor of each storage unit by applying a first voltage on the substrate and applying a second voltage on the second plate of the storage capacitor of each storage unit, the first The voltage is higher than the second voltage; a test module is used to perform a read operation on each storage unit after the storage capacitor of each storage unit is charged for a predetermined period of time to perform an aging test on the dynamic random access memory.
  • control module is further configured to: send a first input signal to an input end of a voltage switching circuit to switch the voltage applied on the substrate from the third voltage to the third voltage. a voltage, and switches the voltage applied on the second plate of each storage capacitor from a fourth voltage to the second voltage; wherein the third voltage is lower than the first voltage, and the fourth voltage is higher than the second voltage, and the fourth voltage is higher than the third voltage.
  • the voltage switching circuit includes a first inverter and a second inverter, and the input terminal of the first inverter is connected to the input terminal of the second inverter;
  • the control module is further configured to: send the first input signal to a common input end of the first inverter and the second inverter, so that the first inverter will The voltage applied on the substrate is switched from the third voltage to the first voltage, and the voltage applied on the second plate of each storage capacitor is switched from the fourth voltage to the first voltage through the second inverter. the second voltage.
  • control module is further configured to: after the storage capacitor of each storage unit is charged for a predetermined period of time, send a second input signal to the input end of the voltage switching circuit to change the voltage on the liner.
  • the voltage applied on the bottom is switched from the first voltage to the third voltage, and the voltage applied on the second plate of each storage capacitor is switched from the second voltage to the fourth voltage.
  • the voltage switching circuit includes a first inverter and a second inverter, and the first inverter and the second inverter share an input terminal; the control module, Also configured to: send the second input signal to a common input end of the first inverter and the second inverter, so as to transfer the signal applied on the substrate through the first inverter.
  • the voltage is switched from the first voltage to the third voltage, and the voltage applied on the second plate of each storage capacitor is switched from the second voltage to the fourth voltage.
  • the device further includes: a determining module, further configured to obtain area sizes of the plurality of memory cells; and determine the relationship between the first voltage and the second voltage according to the area sizes of the plurality of memory cells. The voltage difference between them is to obtain the first voltage and the second voltage.
  • a dynamic random access memory testing device including a dynamic random access memory to be tested and a voltage switching circuit, wherein: the dynamic random access memory to be tested includes a substrate and a plurality of storage units, and each storage unit includes Storage capacitor and first transistor, the first transistor is an NMOS transistor, the first plate of the storage capacitor of each storage unit is electrically connected to the drain of the corresponding first transistor, and the P-type silicon substrate of the first transistor of each storage unit electrically connected to the substrate; the voltage switching circuit includes a first output terminal and a second output terminal, the first output terminal of the voltage switching circuit is electrically connected to the substrate, and is used to apply The first voltage, the second output end of the voltage switching circuit is electrically connected to the second plate of each storage capacitor, for applying a second voltage on the second plate of each storage capacitor, the first voltage is higher than The second voltage is used to charge the storage capacitor of each storage unit.
  • the voltage switching circuit includes a first inverter and a second inverter, and the input terminal of the first inverter is connected to the input terminal of the second inverter, The output terminal of the first inverter is the first output terminal, and the output terminal of the second inverter is the second output terminal.
  • both the first inverter and the second inverter are CMOS transistors.
  • the drain of the NMOS transistor and the drain of the PMOS transistor of the first inverter are connected to the first output terminal, and the input voltage of the source of the PMOS transistor of the first inverter is The first voltage, the input voltage of the source of the NMOS transistor of the first inverter is the third voltage; the drain of the NMOS transistor and the drain of the PMOS transistor of the second inverter are in phase with the second output terminal.
  • the input voltage of the source of the PMOS transistor of the second inverter is the second voltage
  • the input voltage of the source of the NMOS transistor of the second inverter is a fourth voltage
  • the fourth voltage is higher than the The third voltage
  • the input terminal of the first inverter and the input terminal of the second inverter are used to receive the first input signal, so that the PMOS transistor of the first inverter and the The PMOS transistor of the second inverter is turned on, and the NMOS transistor of the first inverter and the NMOS transistor of the second inverter are turned off.
  • the input terminal of the first inverter and the input terminal of the second inverter are also used to receive a second input signal, so that the PMOS transistor of the first inverter and the PMOS transistor of the second inverter is turned off, and the NMOS transistor of the first inverter and the NMOS transistor of the second inverter are turned on.
  • the drain of the NMOS transistor and the drain of the PMOS transistor of the first inverter are connected to the first output terminal, and the input voltage of the source of the NMOS transistor of the first inverter is The first voltage, the input voltage of the source of the PMOS transistor of the first inverter is a third voltage; the drain of the NMOS transistor and the drain of the PMOS transistor of the second inverter are in phase with the second output terminal.
  • the input voltage of the source of the NMOS transistor of the second inverter is the second voltage
  • the input voltage of the source of the PMOS transistor of the second inverter is a fourth voltage
  • the fourth voltage is higher than the The third voltage
  • the input terminal of the first inverter and the input terminal of the second inverter are used to receive the first input signal, so that the NMOS transistor of the first inverter and the The NMOS transistors of the second inverter are turned on, and the PMOS transistors of the first inverter and the PMOS transistors of the second inverter are turned off.
  • the input terminal of the first inverter and the input terminal of the second inverter are also used to receive a second input signal, so that the NMOS transistor of the first inverter The NMOS transistor of the second inverter is turned off, and the PMOS transistor of the first inverter and the PMOS transistor of the second inverter are turned on.
  • the first output terminal of the voltage switching circuit is electrically connected to the substrate through a connection plug.
  • an electronic device including: a memory, a processor, and executable instructions stored in the memory and executable in the processor.
  • the processor executes the executable instructions. Implement any of the above methods when commanding.
  • a computer-readable storage medium on which computer-executable instructions are stored.
  • the executable instructions are executed by a processor, any one of the above methods is implemented.
  • Figure 1 exemplarily shows a flow chart of a write background operation.
  • Figure 2 shows a graph of the relationship between the failure period and the failure rate of a device.
  • FIG. 3 shows a schematic diagram of a DRAM architecture in an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of the wafer in the DRAM array shown in FIG. 3 in a side view direction.
  • FIG. 5 shows a flow chart of a method for testing dynamic random access memory in an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a voltage switching circuit according to an exemplary embodiment.
  • FIG. 7 is a schematic diagram of another voltage switching circuit according to an exemplary embodiment.
  • FIG. 8 is a flow chart of another dynamic random access memory testing method shown in FIGS. 5 to 7 .
  • FIG. 9 is a schematic flowchart of writing a background according to FIG. 8 .
  • FIG. 10 is a schematic flowchart of a reading operation shown in FIG. 8 .
  • Figure 11 shows a block diagram of a dynamic random access memory testing device in an embodiment of the present disclosure.
  • FIG. 12 shows a block diagram of another dynamic random access memory testing device in an embodiment of the present disclosure.
  • Figure 13 shows a schematic structural diagram of an electronic device in an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • the same reference numerals in the drawings represent the same or similar parts, and thus their repeated description will be omitted.
  • first”, “second”, etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • “plurality” means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.
  • the symbol “/” generally indicates that the related objects are an "or” relationship.
  • connection should be understood in a broad sense, for example, it can be an electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium.
  • connection should be understood in a broad sense, for example, it can be an electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium.
  • the burn-in test is to eliminate early failures by controlling the working status of the chip and applying temperature stress.
  • the aging test can be divided into static aging, dynamic aging and aging test.
  • Static burn-in means that only voltage is provided to the power supply end of the circuit, and the signal input pin does not provide a burn-in vector. At this time, the internal transistor basically does not flip.
  • Testing during aging refers to sampling the electrical parameters of the circuit during the dynamic aging process to complete all or part of the functional testing during the aging process.
  • Dynamic burn-in refers to providing the circuit power supply voltage and burn-in vector so that the circuit can achieve a certain function during burn-in and enable the internal transistors of the circuit to flip.
  • the main purpose of the burn-in test vector is to increase the test stress inside the part, improve the burn-in efficiency, and promote the occurrence of device abnormalities, so as to eliminate unqualified products at an early stage.
  • DFT Design For Test
  • FIG1 exemplarily shows a flowchart of a write background operation.
  • the current word line is activated (S102), and "1" is written to each bit line one by one after each word line is activated (S104), and when writing "1", it waits for n (n is a positive integer) chip unselected (Device Deselected, DES) instructions (S106) time, where the DES instruction is an instruction defined in the DRAM command truth table.
  • n is a positive integer
  • DES Chip unselected instructions
  • S106 chip unselected instructions
  • the current word line is precharged (S108), and then the activation action of the next word line is entered to traverse X word lines (S109).
  • Figure 2 shows a graph of the relationship between the failure period and failure rate of a device.
  • the method of writing the background in the burn-in test used in the related technology may cause the DRAM capacitor to still fail in the early stage. period, and some devices, such as WL circuits, BL circuits, sense amplifier (Sense Amplifier, SA) circuits or other circuits, have entered the loss and failure period.
  • SA sense amplifier
  • the present disclosure provides a dynamic random access memory testing method by applying a first voltage on a substrate electrically connected to the P-type silicon substrate of the first transistor of each memory unit, and connecting the first plate and the corresponding first A second voltage lower than the first voltage is applied to the second plate of each storage capacitor electrically connected to the drain of the transistor to charge the storage capacitor of each storage unit, and then after the storage capacitor of each storage unit is charged for a predetermined period of time,
  • the read operation is performed on each memory unit to perform a burn-in test on the dynamic random access memory, which can replace the command actions of word line activation, bit line writing, and precharging used in the write test background in the capacitor burn-in test in related technologies. This avoids the loss caused by writing background in the circuits involved in these command actions, and can reduce the loss of WL, BL, SA and other circuits caused by writing background at least to a certain extent during the capacitor aging test.
  • FIG. 3 shows an exemplary DRAM architecture 30 to which the dynamic random access memory testing method or dynamic random access memory testing device of the present disclosure can be applied.
  • the DRAM architecture 30 is used as the dynamic random access memory to be tested in the embodiment of the present disclosure.
  • the architecture 30 of the dynamic random access memory to be tested may include multiple storage units.
  • Two storage units 3062 and 3064 are shown in Figure 3. Referring to Figure 4, the storage capacitor 4062 and the storage capacitor 4064 in Figure 4 are passed through NC ( Node Contact (plate contact) is connected to the drain 4082 and drain 4084 of the two NMOS transistors (i.e. the first transistor). The two transistors share the source 3066.
  • the storage capacitor 4062 and its connected transistor together form the storage unit 3062
  • the storage capacitor 4064 and its connected transistor together form the storage unit 3064.
  • the common source 3066 of the two NMOS transistors is connected to BL 304, and the gate 4086 and gate 4088 of the two transistors are connected to WL 306.
  • the memory cell array in FIG. 3 may be disposed on the substrate 402 of FIG. 4 .
  • FIG. 4 is a schematic structural diagram of a memory cell in the DRAM array shown in FIG. 3 , viewed from the side.
  • FIG. 4 shows a side cross-sectional view of two memory cell groups 306 sharing a common source 3066 .
  • the common top cell plate (TCP) ie, the second plate
  • the voltage applied to the TCP 404 is the second voltage V2; the lower voltage of the storage capacitor 4062 and the storage capacitor 4064
  • the plate ie, the first plate
  • the P-type silicon substrate (also called P-well) of the two transistors is set on the substrate.
  • 402 is electrically connected to the substrate, so that the storage capacitor 4062 and the storage capacitor 4064 are electrically connected to the substrate through the PN junction of the two transistors.
  • a connection plug 410 electrically connected to the substrate 402 may be provided, and the first voltage V1 is applied to the substrate 402 through the connection plug 410 , that is, to the lower plates of the storage capacitor 4062 and the storage capacitor 4064 .
  • Shallow Trench Isolation (STI) is between the connection plug 410 and the PN junction.
  • a voltage switching circuit may be provided for changing the voltage applied on the substrate 402 and the voltage applied on the TCP 404, for example, the first output end of the voltage switching circuit is connected to the substrate 402 through the connecting plug 410. electrically connecting to switch the voltage applied to the substrate 402 from a third voltage to a first voltage higher than the third voltage, and switching the voltage applied to the TCP 404 from a fourth voltage higher than the third voltage to a lower voltage than The second voltage of the first voltage charges the storage capacitor 4062 and the storage capacitor 4064 .
  • FIG. 5 is a flow chart of a dynamic random access memory testing method according to an exemplary embodiment. The method shown in FIG. 5 can be applied to a plurality of memory cells shown in FIGS. 3 and 4 , for example.
  • the method 50 provided by the embodiment of the present disclosure may include the following steps.
  • step S502 the storage capacitor of each storage unit is charged by applying a first voltage on the substrate and applying a second voltage on the second plate of the storage capacitor of each storage unit.
  • the first voltage is higher than the second voltage. Two voltages.
  • a voltage switching circuit electrically connected to the substrate may be provided, and a first input signal may be sent to an input terminal of the voltage switching circuit to switch the voltage applied on the substrate from the third voltage to the first voltage, and to switch the voltage applied on the second plate of each storage capacitor from the fourth voltage to the second voltage, wherein the third voltage is lower than the first voltage, the fourth voltage is higher than the second voltage, and the fourth voltage is higher than the third voltage.
  • a first input signal may be sent to an input terminal of the voltage switching circuit to switch the voltage applied on the substrate from the third voltage to the first voltage, and to switch the voltage applied on the second plate of each storage capacitor from the fourth voltage to the second voltage, wherein the third voltage is lower than the first voltage, the fourth voltage is higher than the second voltage, and the fourth voltage is higher than the third voltage.
  • the voltage difference between the first voltage and the second voltage used in the burn-in test can be determined according to the manufacturing process.
  • the voltage difference between the first voltage and the second voltage can also be determined based on the number of memory cells, that is, the size of the area where the memory cells to be subjected to the aging test are located.
  • the number of memory cells that is, the size of the area where the memory cells to be subjected to the aging test are located.
  • step S504 after the storage capacitor of each memory unit is charged for a predetermined period of time, a read operation is performed on each memory unit to perform a burn-in test on the dynamic random access memory.
  • the voltage applied on the substrate may be switched from the third voltage to the first voltage, and the voltage applied on the second plate of each storage capacitor may be switched from the fourth voltage to the second voltage.
  • the preset number of command clocks can be, for example, n DES The duration of the instruction.
  • the specific implementation may refer to Figure 8 and Figure 9 .
  • a first voltage is applied on a substrate electrically connected to a P-type silicon substrate of a first transistor of each memory unit, and a first voltage is applied between the first plate and the corresponding first transistor.
  • a second voltage lower than the first voltage is applied to the second plate of each storage capacitor whose drain is electrically connected to charge the storage capacitor of each storage unit, and then after the storage capacitor of each storage unit is charged for a predetermined period of time, the Each memory unit performs a read operation to perform a burn-in test on the dynamic random access memory, which can replace the command actions of word line activation, bit line writing, and precharging used in the write test background in the capacitor burn-in test in related technologies.
  • FIG. 6 is a schematic diagram of a voltage switching circuit according to an exemplary embodiment.
  • the voltage switching circuit shown in Figure 6 can be used to apply a voltage to the substrate 402 in Figure 4 and apply a voltage to the TCP 404 to implement the method shown in Figure 5.
  • the voltage switching circuit may include a first output terminal 6042 and a second input terminal 6044.
  • the first output terminal 6042 of the voltage switching circuit is electrically connected to the substrate 402, and the second input terminal 6044 is electrically connected to the TCP 404.
  • the voltage switching circuit may include a first inverter and a second inverter.
  • the input terminal of the first inverter is connected to the input terminal of the second inverter for receiving the input signal 602.
  • the output terminal is the first output terminal 6042, and the output terminal of the second inverter is the second output terminal 6044.
  • the first inverter and the second inverter can both be CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor) transistors.
  • CMOS Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor
  • the drain of the NMOS transistor M2 of the first inverter and the drain of the PMOS transistor M1 have different voltages.
  • the first output terminal 6042 of the switching circuit is connected, the input voltage of the source of the NMOS transistor M2 of the first inverter is the third voltage V3, and the input voltage of the source of the PMOS transistor M1 of the first inverter is the first voltage. Voltage V1.
  • the third voltage V3 may be a normal operating voltage of the substrate, for example, it may be ground (0V); the first voltage V1 may be a high voltage, for example, it may be VDD (the operating voltage inside the device).
  • the drain of the NMOS transistor M3 and the drain of the PMOS transistor M4 of the second inverter are connected to the second output terminal 6044, the input voltage of the source of the PMOS transistor M4 of the second inverter is the second voltage V2, the input voltage of the source of the NMOS transistor M3 of the second inverter is the fourth voltage V4, and the fourth voltage V4 is higher than the third voltage V3.
  • the fourth voltage V4 may be the normal operating voltage of the TCP, for example, it may be Vcc (the supply voltage of the circuit)/2; the second voltage V2 may be a low voltage, for example, it may be Vss (the common ground terminal voltage of the circuit).
  • the input signal 602 sent to the input terminal of the first inverter may be a low-level first input signal to turn off the NMOS transistor M2 of the first inverter and the NMOS transistor M3 of the second inverter.
  • the PMOS transistor M1 of the first inverter and the PMOS transistor M4 of the second inverter are turned on, thereby applying the first voltage V1 to the substrate and applying the second voltage V2 to the TCP, that is, the upper voltage of each storage capacitor.
  • applying a high voltage difference to the lower plate can charge the storage capacitor of each storage unit.
  • the input signal 602 sent to the first inverter input terminal may also be a high-level second input signal, so that the PMOS transistor M1 of the first inverter and the PMOS transistor M1 of the second inverter The transistor M4 is turned off, and the NMOS transistor M2 of the first inverter and the NMOS transistor M3 of the second inverter are turned on, thereby applying the third voltage V3 to the substrate, and applying the fourth voltage V4 to the TCP, stopping each storage The unit's storage capacitor is charged.
  • FIG. 7 is a schematic diagram of another voltage switching circuit according to an exemplary embodiment.
  • the voltage switching circuit shown in FIG. 7 can be used to apply a voltage to the substrate 402 in FIG. 4 and apply a voltage to the TCP 404 to implement the method shown in FIG. 5 .
  • the voltage switching circuit may include a first output terminal 7042 and a second input terminal 7044.
  • the first output terminal 7042 of the voltage switching circuit is electrically connected to the substrate 402, and the second input terminal 7044 is electrically connected to the TCP 404.
  • the voltage switching circuit may include a first inverter and a second inverter.
  • the input terminal of the first inverter is connected to the input terminal of the second inverter for receiving the input signal 702.
  • the output terminal is the first output terminal 7042, and the output terminal of the second inverter is the second output terminal 7044.
  • the first inverter and the second inverter may both be CMOS transistors.
  • the drain of the NMOS transistor M2 and the drain of the PMOS transistor M1 of the first inverter are connected to the first output terminal 7042 of the voltage switching circuit.
  • the input voltage of the source of the NMOS transistor M2 of an inverter is the first voltage V1
  • the input voltage of the source of the PMOS transistor M1 of the first inverter is the third voltage V3.
  • the third voltage V3 may be a normal operating voltage of the substrate, for example, it may be ground (0V); the first voltage V1 may be a high voltage, for example, it may be VDD (the operating voltage inside the device).
  • the drains of the NMOS transistor M3 and the PMOS transistor M4 of the second inverter are connected to the second output terminal 7044.
  • the input voltage of the source of the PMOS transistor M4 of the second inverter is the fourth voltage V4.
  • the input voltage of the source of the NMOS transistor M3 of the two inverters is the second voltage V2, and the fourth voltage V4 is higher than the third voltage V3.
  • the fourth voltage V4 may be the normal operating voltage of the TCP, for example, it may be Vcc (the supply voltage of the circuit)/2; the second voltage V2 may be a low voltage, for example, it may be Vss (the common ground terminal voltage of the circuit).
  • the input signal 702 sent to the input terminal of the first inverter may be a high-level first input signal, so that the NMOS transistor M2 of the first inverter and the NMOS transistor M3 of the second inverter are turned on. is turned on, and the PMOS transistor M1 of the first inverter and the PMOS transistor M4 of the second inverter are turned off, thereby applying the first voltage V1 to the substrate and applying the second voltage V2 to the TCP, that is, the upper voltage of each storage capacitor. , applying a high voltage difference to the lower plate can charge the storage capacitor of each storage unit.
  • the input signal 702 sent to the first inverter input terminal may also be a low-level second input signal, so that the PMOS transistor M1 of the first inverter and the PMOS transistor M1 of the second inverter
  • the transistor M4 is turned on, and the NMOS transistor M2 of the first inverter and the NMOS transistor M3 of the second inverter are turned off, thereby applying the third voltage V3 to the substrate, and applying the fourth voltage V4 to the TCP, stopping each storage
  • the unit's storage capacitor is charged.
  • FIG. 8 is a flow chart of another dynamic random access memory testing method shown in FIGS. 5 to 7 .
  • the method 80 provided by the embodiment of the present disclosure may include the following steps.
  • step S802 area sizes of multiple storage units are obtained.
  • the region size of the plurality of memory cells may be, for example, the product of the number of rows and the number of columns of the memory cell array formed by the plurality of memory cells.
  • step S804 the voltage difference between the first voltage and the second voltage is determined according to the area sizes of the plurality of memory cells to obtain the first voltage and the second voltage.
  • the area where the memory cells to be subjected to the burn-in test is located is positively related to the voltage difference between the first voltage and the second voltage. The larger the area of the multiple memory cells, the greater the difference between the first voltage and the second voltage. The greater the voltage difference between them.
  • step S806 a first input signal is sent to the input end of the voltage switching circuit to switch the voltage applied on the substrate from the third voltage to the first voltage, and apply the voltage on the second plate of each storage capacitor. The voltage is switched from the fourth voltage to the second voltage.
  • the voltage switching circuit shown in FIG. 6 or 7 can be used to switch the voltage applied to the substrate and the voltage applied to the TCP.
  • the voltage switching circuit shown in FIG. 6 or 7 can be used to switch the voltage applied to the substrate and the voltage applied to the TCP.
  • FIG. 6 and FIG. 7 refer to FIG. 6 and FIG. 7 .
  • step S808 after the storage capacitors of each storage unit are charged for a predetermined period of time, a second input signal is sent to the input end of the voltage switching circuit to switch the voltage applied to the substrate from the first voltage to the third voltage, and to switch the voltage applied to the second plate of each storage capacitor from the second voltage to the fourth voltage.
  • the voltage applied on the substrate may be applied by sending a second input signal to the input terminal of the voltage switching circuit.
  • the voltage is switched from the first voltage to the third voltage, and the voltage applied on the second plate of each storage capacitor is switched from the second voltage to the fourth voltage, that is, charging to the storage capacitor of each storage unit is stopped.
  • step S810 a read operation is performed on each storage unit to perform a burn-in test on the dynamic random access memory.
  • the read operation can be performed on each memory cell one by one, bit line or word line, to perform pre-processing of the dynamic random access memory. Assume an aging test under temperature stress. For specific implementation, please refer to Figure 10.
  • FIG. 9 is a schematic flowchart of writing a background according to FIG. 8 .
  • step S806 the voltage applied on the substrate is switched from the third voltage to the first voltage, and the voltage applied on the second plate of each storage capacitor is switched from the fourth voltage to the second voltage.
  • the operation can be called entering testability design (Entry Design For Test, Entry DFT), and in step S808, the voltage applied on the substrate is switched from the first voltage to the third voltage, and each storage capacitor is The operation of switching the voltage applied on the second plate from the second voltage to the fourth voltage can be called Exit DFT.
  • the required writing time is n*Y*X DES instructions.
  • the writing time using the method of the embodiment of the present disclosure is Entry DFT + n DES instructions + Exit DFT, and the total time of DFT Entry and Exit usually does not exceed 10tCK, and the writing time has nothing to do with the number of rows and columns of the memory cell array. Therefore, the time to write the background "1" is shortened by (n*Y*X)–(Entry DFT+n+Exit DFT), which can greatly shorten the test time.
  • FIG. 10 is a schematic flowchart of a reading operation shown in FIG. 8 .
  • the current word line is activated (S1002), and after the word line is activated, "1" is read from the bit lines one by one. (S1004), wait for n DES instructions (S1006) when reading "1", and then after traversing and reading Y bit lines, precharge the current word line (S1008), and then enter the next word Line activation action to traverse X word lines (S1009).
  • the method shown in FIG5 or FIG8 is used to write “1" and read by the method shown in FIG10 to verify whether the failed bit is caused by a defect in the wafer itself or an abnormal Write operation. Therefore, the methods provided in the embodiments of FIG5 and FIG8 can also help verify whether the Write operation is abnormal.
  • FIG. 11 is a block diagram of a dynamic random access memory testing device according to an exemplary embodiment.
  • the device shown in FIG. 11 may be applied to a plurality of memory units shown in FIGS. 3 and 4 , for example.
  • the apparatus 110 may include a control module 1102 and a test module 1104 .
  • the control module 1102 may be configured to charge the storage capacitor of each storage unit by applying a first voltage on the substrate and applying a second voltage on the second plate of the storage capacitor of each storage unit, the first voltage being higher than the second voltage. Two voltages.
  • the test module 1104 can be used to perform a read operation on each storage unit after the storage capacitor of each storage unit is charged for a predetermined period of time to perform a burn-in test on the dynamic random access memory.
  • FIG. 12 is a block diagram of another dynamic random access memory testing device according to an exemplary embodiment.
  • the device shown in FIG. 12 may be applied to a plurality of memory units shown in FIGS. 3 and 4 , for example.
  • the device 120 may include a control module 1202 , a test module 1204 and a determination module 1206 .
  • the control module 1202 may be used to charge the storage capacitor of each storage unit by applying a first voltage on the substrate and applying a second voltage on the second plate of the storage capacitor of each storage unit, the first voltage being higher than the second voltage. Two voltages.
  • the control module 1202 may also be configured to: send a first input signal to the input end of the voltage switching circuit to switch the voltage applied on the substrate from the third voltage to the first voltage, and to switch the voltage on the second plate of each storage capacitor.
  • the applied voltage is switched from the fourth voltage to the second voltage; wherein the third voltage is lower than the first voltage, the fourth voltage is higher than the second voltage, and the fourth voltage is higher than the third voltage.
  • the control module 1202 may also be configured to: send a first input signal to a common input terminal of the first inverter and the second inverter, so as to switch the voltage applied on the substrate from the third voltage to the first voltage, and the voltage applied on the second plate of each storage capacitor is switched from the fourth voltage to the second voltage through the second inverter.
  • the control module 1202 may also be configured to: after the storage capacitor of each storage unit is charged for a predetermined period of time, send a second input signal to the input end of the voltage switching circuit to switch the voltage applied on the substrate from the first voltage to the third voltage. , and switches the voltage applied on the second plate of each storage capacitor from the second voltage to the fourth voltage.
  • the control module 1202 can also be used to: send a second input signal to the common input terminal of the first inverter and the second inverter to switch the voltage applied to the substrate from the first voltage to the third voltage through the first inverter, and switch the voltage applied to the second plate of each storage capacitor from the second voltage to the fourth voltage.
  • the test module 1204 can be used to perform a read operation on each storage unit after the storage capacitor of each storage unit is charged for a predetermined period of time to perform a burn-in test on the dynamic random access memory.
  • the determining module 1206 may be used to obtain the area sizes of multiple memory cells; determine the voltage difference between the first voltage and the second voltage according to the area sizes of the multiple memory cells to obtain the first voltage and the second voltage.
  • Figure 13 shows a schematic structural diagram of an electronic device in an embodiment of the present disclosure. It should be noted that the device shown in Figure 13 is only a computer system as an example, and should not impose any restrictions on the functions and scope of use of the embodiments of the present disclosure.
  • the device 1300 includes a central processing unit (CPU) 1301 that can operate according to a program stored in a read-only memory (ROM) 1302 or loaded from a storage portion 1308 into a random access memory (RAM) 1303 Perform various appropriate actions and processing.
  • CPU central processing unit
  • RAM random access memory
  • various programs and data required for the operation of the device 1300 are also stored.
  • CPU 1301, ROM 1302 and RAM 1303 are connected to each other through bus 1304.
  • An input/output (I/O) interface 1305 is also connected to bus 1304.
  • the following components are connected to the I/O interface 1305: an input section 1306 including a keyboard, a mouse, etc.; an output section 1307 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., speakers, etc.; and a storage section 1308 including a hard disk, etc. ; and a communication section 1309 including a network interface card such as a LAN card, a modem, etc.
  • the communication section 1309 performs communication processing via a network such as the Internet.
  • Driver 1310 is also connected to I/O interface 1305 as needed.
  • Removable media 1311 such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 1310 as needed, so that a computer program read therefrom is installed into the storage portion 1308 as needed.
  • embodiments of the present disclosure include a computer program product including a computer program carried on a computer-readable medium, the computer program containing program code for performing the method illustrated in the flowchart.
  • the computer program may be downloaded and installed from the network via communications portion 1309, and/or installed from removable media 1311.
  • CPU central processing unit
  • the computer-readable medium shown in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium, or any combination of the above two.
  • the computer-readable storage medium may be, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus or device, or any combination thereof. More specific examples of computer readable storage media may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard drive, random access memory (RAM), read only memory (ROM), removable Programmd read-only memory (EPROM or flash memory), fiber optics, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above.
  • a computer-readable storage medium may be any tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device.
  • a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code therein. Such propagated data signals may take many forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above.
  • a computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device .
  • Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the foregoing.
  • each block in the flowchart or block diagrams may represent a module, segment, or portion of code that contains one or more logic functions that implement the specified executable instructions.
  • the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown one after another may actually execute substantially in parallel, or they may sometimes execute in the reverse order, depending on the functionality involved.
  • each block in the block diagram or flowchart illustration, and combinations of blocks in the block diagram or flowchart illustration can be implemented by special purpose hardware-based systems that perform the specified functions or operations, or may be implemented by special purpose hardware-based systems that perform the specified functions or operations. Achieved by a combination of specialized hardware and computer instructions.
  • the modules involved in the embodiments of the present disclosure can be implemented in software or hardware.
  • the described module can also be provided in a processor.
  • a processor includes a data control module and a test module.
  • the names of these modules do not constitute a limitation on the module itself under certain circumstances.
  • the control module can also be described as "a module that sends control signals to the connected circuit.”
  • the present disclosure also provides a computer-readable medium.
  • the computer-readable medium may be included in the device described in the above embodiments; it may also exist separately without being assembled into the device.
  • the above-mentioned computer-readable medium carries one or more programs.
  • the device includes: by applying a first voltage on the substrate, and storing capacitors in each storage unit. A second voltage is applied to the second plate to charge the storage capacitor of each storage unit, and the first voltage is higher than the second voltage; after the storage capacitor of each storage unit is charged for a predetermined period of time, each storage unit is read. , to perform burn-in testing of dynamic random access memory.

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Abstract

一种动态随机存储器测试方法及装置，涉及存储器技术领域。动态随机存储器包括衬底（402）和多个存储单元（3062，3064），各个存储单元（3062，3064）包括存储电容（4062，4064）和第一晶体管 NMOS 晶体管，各个存储单元（3062，3064）的存储电容（4062，4064）的第一极板与对应第一晶体管的漏极（4082，4084）电连接，各个存储单元（3062，3064）的第一晶体管的 P 型硅基板与衬底（402）电连接，该方法包括:通过在衬底（402）上施加第一电压（V1），并在各个存储单元（3062，3064）的存储电容（4062，4064）的第二极板（404）上施加第二电压（V2），对各个存储单元（3062，3064）的存储电容（4062，4064）进行充电，第一电压（V1）高于第二电压（V2）（S502）；在各个存储单元（3062，3064）的存储电容（4062，4064）充电预定时长后，对各个存储单元（3062，3064）进行读取操作，以对动态随机存储器进行老炼测试（S504）。该方法可避免老炼测试中写入背景采用激活、写入、预充电的指令动作而导致的相关电路的损耗。

Description

动态随机存储器测试方法及装置
本公开基于申请号为202211166635.X、申请日为2022年9月23日、发明名称为《动态随机存储器测试方法及装置》的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及存储器技术领域，具体而言，涉及一种动态随机存储器测试方法及装置。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)芯片的老炼测试是通过对芯片工作状态的控制和温度应力的施加，剔除早期失效。老炼测试向量主要目的是增加件内部的测试应力，提高老炼效率，促使器件反常现象出现，以在早期淘汰不合格产品。
在所述背景技术部分公开的上述信息仅用于加强对本公开的背景的理解，因此它可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种动态随机存储器测试方法及装置。
本公开的其他特性和优点将通过下面的详细描述变得显然，或部分地通过本公开的实践而习得。
根据本公开的一方面，提供一种动态随机存储器测试方法，包括：所述动态随机存储器包括衬底和多个存储单元，各个存储单元包括存储电容和第一晶体管，所述第一晶体管为NMOS晶体管，各个存储单元的存储电容的第一极板与对应第一晶体管的漏极电连接，各个存储单元的第一晶体管的P型硅基板与所述衬底电连接，所述方法包括：通过在所述衬底上施加第一电压，并在各个存储单元的存储电容的第二极板上施加第二电压，对各个存储单元的存储电容进行充电，所述第一电压高于所述第二电压；在各个存储单元的存储电容充电预定时长后，对所述各个存储单元进行读取操作，以对所述动态随机存储器进行老炼测试。
根据本公开的一实施例，通过在所述衬底上施加第一电压，并在各 个存储电容的第二极板上施加第二电压，对各个存储单元的存储电容进行充电，包括：向电压切换电路的输入端发送第一输入信号，以将在所述衬底上施加的电压从第三电压切换为所述第一电压，并将在各个存储电容的第二极板上施加的电压从第四电压切换为所述第二电压，对各个存储单元的存储电容进行充电；其中，所述第三电压低于所述第一电压，所述第四电压高于所述第二电压，所述第四电压高于所述第三电压。
根据本公开的一实施例，所述电压切换电路包括第一反相器和第二反相器，所述第一反相器的输入端与所述第二反相器的输入端相连接；向电压切换电路的输入端发送第一输入信号，以将在所述衬底上施加的电压从第三电压切换为所述第一电压，并将在各个存储电容的第二极板上施加的电压从第四电压切换为所述第二电压，包括：向所述第一反相器与所述第二反相器的共用输入端发送所述第一输入信号，以通过所述第一反相器将在所述衬底上施加的电压从所述第三电压切换为所述第一电压，并通过所述第二反相器将在各个存储电容的第二极板上施加的电压从第四电压切换为所述第二电压。
根据本公开的一实施例，在各个存储单元的存储电容充电预定时长后，对所述各个存储单元进行读取操作，包括：在各个存储单元的存储电容充电预定时长后，向所述电压切换电路的输入端发送第二输入信号，以将在所述衬底上施加的电压从所述第一电压切换为所述第三电压，并将在各个存储电容的第二极板上施加的电压从所述第二电压切换为所述第四电压。
根据本公开的一实施例，所述电压切换电路包括第一反相器和第二反相器，所述第一反相器与所述第二反相器共用输入端；向所述电压切换电路的输入端发送第二输入信号，以将在所述衬底上施加的电压从所述第一电压切换为所述第三电压，并将在各个存储电容的第二极板上施加的电压从所述第二电压切换为所述第四电压，包括：向所述第一反相器与所述第二反相器的共用输入端发送所述第二输入信号，以通过所述第一反相器将在所述衬底上施加的电压从所述第一电压切换为所述第三电压，并将在各个存储电容的第二极板上施加的电压从所述第二电压切换为所述第四电压。
根据本公开的一实施例，所述方法还包括：获得所述多个存储单元的区域大小；根据所述多个存储单元的区域大小确定第一电压与第二电压之间的电压差，以获得所述第一电压和所述第二电压。
根据本公开的再一方面，提供一种动态随机存储器测试装置，包括：所述动态随机存储器包括衬底和多个存储单元，各个存储单元包括 存储电容和第一晶体管，所述第一晶体管为NMOS晶体管，各个存储单元的存储电容的第一极板与对应第一晶体管的漏极电连接，各个存储单元的第一晶体管的P型硅基板与所述衬底电连接，所述装置包括：控制模块，用于通过在所述衬底上施加第一电压，并在各个存储单元的存储电容的第二极板上施加第二电压，对各个存储单元的存储电容进行充电，所述第一电压高于所述第二电压；测试模块，用于在各个存储单元的存储电容充电预定时长后，对所述各个存储单元进行读取操作，以对所述动态随机存储器进行老炼测试。
根据本公开的一实施例，所述控制模块，还用于：向电压切换电路的输入端发送第一输入信号，以将在所述衬底上施加的电压从第三电压切换为所述第一电压，并将在各个存储电容的第二极板上施加的电压从第四电压切换为所述第二电压；其中，所述第三电压低于所述第一电压，所述第四电压高于所述第二电压，所述第四电压高于所述第三电压。
根据本公开的一实施例，所述电压切换电路包括第一反相器和第二反相器，所述第一反相器的输入端与所述第二反相器的输入端相连接；所述控制模块，还用于：向所述第一反相器与所述第二反相器的共用输入端发送所述第一输入信号，以通过所述第一反相器将在所述衬底上施加的电压从所述第三电压切换为所述第一电压，并通过所述第二反相器将在各个存储电容的第二极板上施加的电压从第四电压切换为所述第二电压。
根据本公开的一实施例，所述控制模块，还用于：在各个存储单元的存储电容充电预定时长后，向所述电压切换电路的输入端发送第二输入信号，以将在所述衬底上施加的电压从所述第一电压切换为所述第三电压，并将在各个存储电容的第二极板上施加的电压从所述第二电压切换为所述第四电压。
根据本公开的一实施例，所述电压切换电路包括第一反相器和第二反相器，所述第一反相器与所述第二反相器共用输入端；所述控制模块，还用于：向所述第一反相器与所述第二反相器的共用输入端发送所述第二输入信号，以通过所述第一反相器将在所述衬底上施加的电压从所述第一电压切换为所述第三电压，并将在各个存储电容的第二极板上施加的电压从所述第二电压切换为所述第四电压。
根据本公开的一实施例，所述装置还包括：确定模块，还用于获得所述多个存储单元的区域大小；根据所述多个存储单元的区域大小确定第一电压与第二电压之间的电压差，以获得所述第一电压和所述第二电压。
根据本公开的再一方面，提供一种动态随机存储器测试装置，包括待测试动态随机存储器和电压切换电路，其中：所述待测试动态随机存储器包括衬底和多个存储单元，各个存储单元包括存储电容和第一晶体管，所述第一晶体管为NMOS晶体管，各个存储单元的存储电容的第一极板与对应第一晶体管的漏极电连接，各个存储单元的第一晶体管的P型硅基板与所述衬底电连接；所述电压切换电路包括第一输出端和第二输出端，所述电压切换电路的第一输出端与所述衬底电连接，用于向所述衬底施加第一电压，所述电压切换电路的第二输出端与各个存储电容的第二极板电连接，用于在各个存储电容的第二极板上施加第二电压，所述第一电压高于所述第二电压，以对各个存储单元的存储电容进行充电。
根据本公开的一实施例，所述电压切换电路包括第一反相器和第二反相器，所述第一反相器的输入端与所述第二反相器的输入端相连接，所述第一反相器的输出端为所述第一输出端，所述第二反相器的输出端为所述第二输出端。
根据本公开的一实施例，所述第一反相器与所述第二反相器均为CMOS晶体管。
根据本公开的一实施例，第一反相器的NMOS晶体管的漏极、PMOS晶体管的漏极与所述第一输出端相连接，第一反相器的PMOS晶体管的源极的输入电压为所述第一电压，第一反相器的NMOS晶体管的源极的输入电压为第三电压；第二反相器的NMOS晶体管的漏极、PMOS晶体管的漏极与所述第二输出端相连接，第二反相器的PMOS晶体管的源极的输入电压为所述第二电压，第二反相器的NMOS晶体管的源极的输入电压为第四电压，所述第四电压高于所述第三电压；所述第一反相器的输入端与所述第二反相器的输入端用于接收第一输入信号，以使所述第一反相器的PMOS晶体管和所述第二反相器的PMOS晶体管导通，以及第一反相器的NMOS晶体管和第二反相器的NMOS晶体管截止。
根据本公开的一实施例，所述第一反相器的输入端与所述第二反相器的输入端还用于接收第二输入信号，以使所述第一反相器的PMOS晶体管和所述第二反相器的PMOS晶体管截止，以及第一反相器的NMOS晶体管和第二反相器的NMOS晶体管导通。
根据本公开的一实施例，第一反相器的NMOS晶体管的漏极、PMOS晶体管的漏极与所述第一输出端相连接，第一反相器的NMOS晶体管的源极的输入电压为所述第一电压，第一反相器的PMOS晶体管的源极的输入电压为第三电压；第二反相器的NMOS晶体管的漏极、 PMOS晶体管的漏极与所述第二输出端相连接，第二反相器的NMOS晶体管的源极的输入电压为所述第二电压，第二反相器的PMOS晶体管的源极的输入电压为第四电压，所述第四电压高于所述第三电压；所述第一反相器的输入端与所述第二反相器的输入端用于接收第一输入信号，以使所述第一反相器的NMOS晶体管和所述第二反相器的NMOS晶体管导通，以及第一反相器的PMOS晶体管和第二反相器的PMOS晶体管截止。
根据本公开的一实施例，所述第一反相器的输入端与所述第二反相器的输入端还用于接收第二输入信号，以使所述第一反相器的NMOS晶体管和所述第二反相器的NMOS晶体管截止，以及第一反相器的PMOS晶体管和第二反相器的PMOS晶体管导通。
根据本公开的一实施例，所述电压切换电路的第一输出端通过连接插塞与所述衬底电连接。
根据本公开的再一方面，提供一种电子设备，包括：存储器、处理器及存储在所述存储器中并可在所述处理器中运行的可执行指令，所述处理器执行所述可执行指令时实现如上述任一种方法。
根据本公开的再一方面，提供一种计算机可读存储介质，其上存储有计算机可执行指令，所述可执行指令被处理器执行时实现如上述任一种方法。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性的，并不能限制本公开。
附图说明
通过参照附图详细描述其示例实施例，本公开的上述和其它目标、特征及优点将变得更加显而易见。
图1示例性示出了一种写入背景操作的流程图。
图2示出了一种器件的失效期与故障率之间关系的曲线图。
图3示出本公开实施例中一种DRAM架构的示意图。
图4是根据图3示出的DRAM阵列中晶圆的侧视方向的结构示意图。
图5示出本公开实施例中动态随机存储器测试一种方法的流程图。
图6是根据一示例性实施例示出的一种电压切换电路的示意图。
图7是根据一示例性实施例示出的另一种电压切换电路的示意图。
图8是根据图5至图7示出的另一种动态随机存储器测试方法的流程图。
图9是根据图8示出的一种写入背景的流程示意图。
图10是根据图8示出的一种读取操作的流程示意图。
图11示出本公开实施例中一种动态随机存储器测试装置的框图。
图12示出本公开实施例中另一种动态随机存储器测试装置的框图。
图13示出本公开实施例中一种电子设备的结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。
此外，所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、装置、步骤等。在其它情况下，不详细示出或描述公知结构、方法、装置、实现或者操作以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。符号“/”一般表示前后关联对象是一种“或”的关系。
在本公开中，除非另有明确的规定和限定，“连接”等术语应做广义理解，例如，可以是电连接或可以互相通讯；可以是直接相连，也可以通过中间媒介间接相连。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
老炼测试是通过对芯片工作状态的控制和温度应力的施加，剔除早期失效。老炼试验可以分为静态老炼、动态老炼和老炼中测试。静态老炼是指只给电路电源端提供电压，信号输入引脚不提供老炼向量，这时内部晶体管基本没有翻转。老炼中测试是指在动态老炼过程中对电路电参数进行采样，实现老炼过程中完成全部或部分功能测试。动态老炼是指提供电路电源电压和老炼向量，使电路在老炼中实现某种功能，并使 电路内部晶体管实现翻转。老炼测试向量主要目的是增加件内部的测试应力，提高老炼效率，促使器件反常现象出现，以在早期淘汰不合格产品。
DRAM芯片的电容老炼测试部分向量需要写入背景，相关技术中写入背景时采用Active、Write、Precharge指令动作将WL逐次激活或者通过可测试性设计(Design For Test，DFT)同时激活大量WL，例如，在写入背景时逐条字线(Word Line，WL)进行激活(Active)，并在每条字线激活后逐条位线(Bit Line，BL)写入(Write)，然后在位线都写入后预充电(Precharge)，进入下一条字线的激活动作。
图1示例性示出了一种写入背景操作的流程图。如图1所示，以存储器阵列连接X条字线、Y条位线为例，对当前字线进行激活(S102)，并在每条字线激活后逐条位线写入“1”(S104)，在写入“1”时等待n(n为正整数)个芯片未选中(Device Deselected，DES)指令(S106)的时间，其中，DES指令为DRAM命令真值表中定义的指令。然后在遍历写入Y条位线(S107)后，为当前字线预充电(S108)，再进入下一条字线的激活动作，以遍历X条字线(S109)。这会导致这些指令动作涉及的电路损耗大于电容，进而造成DRAM电容老炼效率不足、但部份器件例如WL电路、BL电路、感应放大器(Sense Amplifier，SA)电路或其他电路等，却提早进入损耗失效期。
图2示出了一种器件的失效期与故障率之间关系的曲线图，如图2所示，相关技术采用的老炼测试中写入背景的方法有可能会导致DRAM电容仍在早期失效期，而部分器件例如WL电路、BL电路、感应放大器(Sense Amplifier，SA)电路或其他电路等，已进入损耗失效期。
如上所述，如何在电容老炼测试中减小写入背景导致的WL、BL、SA等电路的损耗成为亟待解决的问题。
因此，本公开提供了一种动态随机存储器测试方法，通过在与各个存储单元的第一晶体管的P型硅基板电连接的衬底上施加第一电压，并在第一极板与对应第一晶体管的漏极电连接的各个存储电容的第二极板上施加低于第一电压的第二电压，对各个存储单元的存储电容进行充电，然后在各个存储单元的存储电容充电预定时长后，对各个存储单元进行读取操作，以对动态随机存储器进行老炼测试，可替代相关技术中电容老炼测试中写入测试背景采用的字线激活、位线写入、预充电的指令动作，从而避免了这些指令动作涉及的电路因写入背景而导致的损耗，可在电容老炼测试中至少在一定程度上减小写入背景导致的WL、BL、SA等电路的损耗。
图3示出了可以应用本公开的动态随机存储器测试方法或动态随机 存储器测试装置的示例性DRAM架构30，以DRAM架构30为本公开实施例中的待测试动态随机存储器进行说明。
待测试动态随机存储器的架构30可以包括多个存储单元，图3中示出了两个存储单元3062和3064，参照图4，图4中的存储电容4062、存储电容4064和其分别通过NC(Node Contact，极板触点)连接到两个NMOS晶体管(即第一晶体管)的漏极4082和漏极4084，两个晶体管共用源极3066，存储电容4062与其连接的晶体管共同组成了存储单元3062，存储电容4064与其连接的晶体管共同组成了存储单元3064。两个NMOS晶体管共用源极3066接到BL 304，两个晶体管的栅极4086和栅极4088接到WL 306。图3中的存储单元阵列可以设置在图4的衬底402上。
图4是根据图3示出的DRAM阵列中存储单元的侧视方向的结构示意图。参照图3，图4示出了两个共用源极3066的存储单元组306的侧面剖视图。存储电容4062和存储电容4064的共用上极板(Top Cell Plate，TCP)(即第二极板)404，施加在TCP 404上的电压为第二电压V2；存储电容4062和存储电容4064的下极板(即第一极板)分别通过NC连接到两个晶体管的漏极4082和漏极4084，两个晶体管的P型硅基板(也称为P阱(P-well))设置在衬底402上与衬底电连接，以使存储电容4062和存储电容4064通过两个晶体管的PN结与衬底电连接。
在一些实施例中，可以设置与衬底402电连接的连接插塞410，通过连接插塞410向衬底402即向存储电容4062和存储电容4064的下极板施加第一电压V1。连接插塞410与PN结之间为浅槽隔离(Shallow Trench Isolation，STI)。
在一些实施例中，可以设置电压切换电路用于改变施加在衬底402上的电压和施加在TCP 404上的电压，例如将电压切换电路的第一输出端通过连接插塞410与衬底402电连接，将向衬底402施加的电压从第三电压切换为高于第三电压的第一电压，并将在TCP 404上施加的电压从高于第三电压的第四电压切换为低于第一电压的第二电压，对存储电容4062和存储电容4064进行充电。
应该理解，图3中的存储单元数目仅仅是示意性的。根据实现需要，可以具有任意数目的存储单元。
图5是根据一示例性实施例示出的一种动态随机存储器测试方法的流程图。如图5所示的方法例如可以应用于图3和图4所示的多个存储单元。
参考图5，本公开实施例提供的方法50可以包括以下步骤。
在步骤S502中，通过在衬底上施加第一电压，并在各个存储单元的存储电容的第二极板上施加第二电压，对各个存储单元的存储电容进行充电，第一电压高于第二电压。
在一些实施例中，可以设置与衬底电连接的电压切换电路，可通过向电压切换电路的输入端发送第一输入信号，以将在衬底上施加的电压从第三电压切换为第一电压，并将在各个存储电容的第二极板上施加的电压从第四电压切换为第二电压，其中，第三电压低于第一电压，第四电压高于第二电压，第四电压高于第三电压。具体实施方式可参照图6和图7。
在一些实施例中，老炼测试时使用的第一电压与第二电压之间的电压差可依制作工艺决定。
在一些实施例中，还可综合存储单元的多少即待进行老炼测试的存储单元所在区域的大小因素，确定第一电压与第二电压之间的电压差，具体实施方式可参照图8和图9。
在步骤S504中，在各个存储单元的存储电容充电预定时长后，对各个存储单元进行读取操作，以对动态随机存储器进行老炼测试。
在一些实施例中，可在将衬底上施加的电压从第三电压切换为第一电压，并将在各个存储电容的第二极板上施加的电压从第四电压切换为第二电压后，等待预设数量个命令时钟(tCK)后逐条位线、字线地对各个存储单元进行读取操作，以对动态随机存储器进行老炼测试，预设数量个命令时钟例如可以是n个DES指令的时长。具体实施方式可参照图8和图9。
根据本公开实施例提供的动态随机存储器测试方法，通过在与各个存储单元的第一晶体管的P型硅基板电连接的衬底上施加第一电压，并在第一极板与对应第一晶体管的漏极电连接的各个存储电容的第二极板上施加低于第一电压的第二电压，对各个存储单元的存储电容进行充电，然后在各个存储单元的存储电容充电预定时长后，对各个存储单元进行读取操作，以对动态随机存储器进行老炼测试，可替代相关技术中电容老炼测试中写入测试背景采用的字线激活、在位线写入、预充电的指令动作，从而避免了这些指令动作涉及的电路因写入背景而导致的损耗。而且可以在达到相关技术对电容的测试覆盖率的同时，节省了激活、写入和预充电的指令动作的时间，缩减了电容老炼测试项目中写入背景的时间，提高了测试效率。
图6是根据一示例性实施例示出的一种电压切换电路的示意图。图6所示的电压切换电路可以用于向图4中的衬底402施加电压并向TCP 404施加电压，实施图5所示的方法。
如图6所示，电压切换电路可包括第一输出端6042和第二输入端6044，电压切换电路的第一输出端6042与衬底402电连接，第二输入端6044与TCP 404电连接。电压切换电路可以包括第一反相器和第二反相器，第一反相器的输入端与第二反相器的输入端相连接，用于接收输入信号602，第一反相器的输出端为第一输出端6042，第二反相器的输出端为第二输出端6044。
第一反相器与第二反相器可以均为CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)晶体管，第一反相器的NMOS晶体管M2的漏极、PMOS晶体管M1的漏极与电压切换电路的第一输出端6042相连接，第一反相器的NMOS晶体管M2的源极的输入电压为第三电压V3，第一反相器的PMOS晶体管M1的源极的输入电压为第一电压V1。
在一些实施例中，第三电压V3可以为衬底正常工作电压，例如可以为接地(0V)；第一电压V1可以为高压，例如可以为VDD(器件内部的工作电压)。
第二反相器的NMOS晶体管M3的漏极、PMOS晶体管M4的漏极与第二输出端6044相连接，第二反相器的PMOS晶体管M4的源极的输入电压为第二电压V2，第二反相器的NMOS晶体管M3的源极的输入电压为第四电压V4，第四电压V4高于第三电压V3。
在一些实施例中，第四电压V4可以为TCP正常工作电压，例如可以为Vcc(电路的供电电压)/2；第二电压V2可以为低压，例如可以为Vss(电路公共接地端电压)。
参照图6，向第一反相器输入端发送的输入信号602可以为低电平的第一输入信号，以使第一反相器的NMOS晶体管M2和第二反相器的NMOS晶体管M3截止，以及第一反相器的PMOS晶体管M1和第二反相器的PMOS晶体管M4导通，从而实现向衬底施加第一电压V1，并向TCP施加第二电压V2，即将各存储电容的上、下极板施加高电压差，可实现对各个存储单元的存储电容进行充电。
在一些实施例中，向第一反相器输入端发送的输入信号602还可以为高电平的第二输入信号，以使第一反相器的PMOS晶体管M1和第二反相器的PMOS晶体管M4截止，以及第一反相器的NMOS晶体管M2和第二反相器的NMOS晶体管M3导通，从而向衬底施加第三电压V3，并向TCP施加第四电压V4，停止对各个存储单元的存储电容进行充电。
通过向第一反相器输入端发送第一输入信号与第二输入信号之间的切换，可实现向衬底施加第一电压V1与第三电压V3之间的切换以及向TCP施加第二电压V2与第四电压V4之间的切换。
图7是根据一示例性实施例示出的另一种电压切换电路的示意图。图7所示的电压切换电路可以用于向图4中的衬底402施加电压并向TCP404施加电压，实施图5所示的方法。
如图7所示，电压切换电路可包括第一输出端7042和第二输入端7044，电压切换电路的第一输出端7042与衬底402电连接，第二输入端7044与TCP 404电连接。电压切换电路可以包括第一反相器和第二反相器，第一反相器的输入端与第二反相器的输入端相连接，用于接收输入信号702，第一反相器的输出端为第一输出端7042，第二反相器的输出端为第二输出端7044。
第一反相器与第二反相器可以均为CMOS晶体管，第一反相器的NMOS晶体管M2的漏极、PMOS晶体管M1的漏极与电压切换电路的第一输出端7042相连接，第一反相器的NMOS晶体管M2的源极的输入电压为第一电压V1，第一反相器的PMOS晶体管M1的源极的输入电压为第三电压V3。
在一些实施例中，第三电压V3可以为衬底正常工作电压，例如可以为接地(0V)；第一电压V1可以为高压，例如可以为VDD(器件内部的工作电压)。
第二反相器的NMOS晶体管M3的漏极、PMOS晶体管M4的漏极与第二输出端7044相连接，第二反相器的PMOS晶体管M4的源极的输入电压为第四电压V4，第二反相器的NMOS晶体管M3的源极的输入电压为第二电压V2，第四电压V4高于第三电压V3。
在一些实施例中，第四电压V4可以为TCP正常工作电压，例如可以为Vcc(电路的供电电压)/2；第二电压V2可以为低压，例如可以为Vss(电路公共接地端电压)。
参照图7，向第一反相器输入端发送的输入信号702可以为高电平的第一输入信号，以使第一反相器的NMOS晶体管M2和第二反相器的NMOS晶体管M3导通，以及第一反相器的PMOS晶体管M1和第二反相器的PMOS晶体管M4截止，从而实现向衬底施加第一电压V1，并向TCP施加第二电压V2，即将各存储电容的上、下极板施加高电压差，可实现对各个存储单元的存储电容进行充电。
在一些实施例中，向第一反相器输入端发送的输入信号702还可以为低电平的第二输入信号，以使第一反相器的PMOS晶体管M1和第二反相器的PMOS晶体管M4导通，以及第一反相器的NMOS晶体管M2和第二反相器的NMOS晶体管M3截止，从而向衬底施加第三电压V3，并向TCP施加第四电压V4，停止对各个存储单元的存储电容进行充电。
通过向第一反相器输入端发送第一输入信号与第二输入信号之间的切换，可实现向衬底施加第一电压V1与第三电压V3之间的切换、以及向TCP施加第二电压V2与第四电压V4之间的切换。
图8是根据图5至图7示出的另一种动态随机存储器测试方法的流程图。
参考图8，本公开实施例提供的方法80可以包括以下步骤。
在步骤S802中，获得多个存储单元的区域大小。
在一些实施例中，多个存储单元的区域大小例如可以是多个存储单元组成的存储单元的阵列的行数与列数的乘积。
在步骤S804中，根据多个存储单元的区域大小确定第一电压与第二电压之间的电压差，以获得第一电压和第二电压。
在一些实施例中，待进行老炼测试的存储单元所在区域可以与第一电压与第二电压之间的电压差正相关，多个存储单元的区域越大，第一电压与第二电压之间的电压差越大。
在步骤S806中，向电压切换电路的输入端发送第一输入信号，以将在衬底上施加的电压从第三电压切换为第一电压，并将在各个存储电容的第二极板上施加的电压从第四电压切换为第二电压。
在一些实施例中，可利用图6或图7所示的电压切换电路实现向衬底施加的电压与向TCP施加的电压的切换，具体实施方式可参照图6和图7。
在步骤S808中，在各个存储单元的存储电容充电预定时长后，向电压切换电路的输入端发送第二输入信号，以将在衬底上施加的电压从第一电压切换为第三电压，并将在各个存储电容的第二极板上施加的电压从第二电压切换为第四电压。
在一些实施例中，在各个存储单元的存储电容充电预定时长后，例如在等待预设数量个命令时钟后，可通过向电压切换电路的输入端发送第二输入信号将在衬底上施加的电压从第一电压切换为第三电压，并将在各个存储电容的第二极板上施加的电压从第二电压切换为第四电压，即停止向各个存储单元的存储电容进行充电。
在步骤S810中，对各个存储单元进行读取操作，以对动态随机存储器进行老炼测试。
在一些实施例中，可在对整个区域的存储单元的电容充电即写入“1”之后，对逐条位线、字线地对各个存储单元进行读取操作，以对动态随机存储器进行在预设温度应力下的老炼测试，具体实施方式可参照 图10。
图9是根据图8示出的一种写入背景的流程示意图。参照图8，步骤S806中的将在衬底上施加的电压从第三电压切换为第一电压，并将在各个存储电容的第二极板上施加的电压从第四电压切换为第二电压的操作，可以称之为进入可测试性设计(Entry Design For Test，Entry DFT)，而步骤S808中将在衬底上施加的电压从第一电压切换为第三电压，并将在各个存储电容的第二极板上施加的电压从第二电压切换为第四电压的操作，可以称之为离开可测试性设计(Exit DFT)。如图9所示，采用图8所示的方法写入背景时，可先采用S802和S804的方法确定第一电压和第二电压，进入可测试性设计(S902)，然后在等待n个DES指令的时长(S904)后，离开可测试性设计(S906)，然后变更存储电容充电区域(S908)，采用S802和S804的方法确定第一电压和第二电压之后，返回S902。待所有待进行老炼测试的存储电容都充电完成(没有可变更的存储电容充电区域)，结束写入背景流程(S910)。
参照图1，采用图1的方法为X条字线、Y条位线的存储单元阵列写入背景“1”时，所需要的写入时间为n*Y*X个DES指令。采用本公开实施例的方法的写入时间为Entry DFT+n个DES指令+Exit DFT，而DFT Entry及Exit总时间通常不超过10tCK，而且写入时间与存储单元阵列的行列数无关。因此写入背景“1”的时间缩短了(n*Y*X)–(Entry DFT+n+Exit DFT)，即可大大缩短测试时间。
图10是根据图8示出的一种读取操作的流程示意图。如图10所示，以读取连接X条字线、Y条位线的存储单元为例，对当前字线进行激活(S1002)，并在字线激活后在逐条位线读取“1”(S1004)，在读取“1”时等待n个DES指令(S1006)的时间，然后在遍历读取Y条位线后，为当前字线预充电预充电(S1008)，再进入下一条字线的激活动作，以遍历X条字线(S1009)。
可在采用图1所示的方法写入“1”并采用图10所示的方法读取后测试得到失效位元的情况下，再采用图5或图8所示的方法写入“1”并采用图10所示的方法读取，可验证失效位元的是由晶圆本身缺陷导致，还是由Write操作异常导致。因此图5和图8实施例提供的方法还可协助验证Write操作是否异常。
图11是根据一示例性实施例示出的一种动态随机存储器测试装置的框图。如图11所示的装置例如可以应用于图3和图4所示的多个存储单元。
参考图11，本公开实施例提供的装置110可以包括控制模块1102和测试模块1104。
控制模块1102可用于通过在衬底上施加第一电压，并在各个存储单元的存储电容的第二极板上施加第二电压，对各个存储单元的存储电容进行充电，第一电压高于第二电压。
测试模块1104可用于在各个存储单元的存储电容充电预定时长后，对各个存储单元进行读取操作，以对动态随机存储器进行老炼测试。
图12是根据一示例性实施例示出的另一种动态随机存储器测试装置的框图。如图12所示的装置例如可以应用于图3和图4所示的多个存储单元。
参考图12，本公开实施例提供的装置120可以包括控制模块1202、测试模块1204和确定模块1206。
控制模块1202可用于通过在衬底上施加第一电压，并在各个存储单元的存储电容的第二极板上施加第二电压，对各个存储单元的存储电容进行充电，第一电压高于第二电压。
控制模块1202还可用于：向电压切换电路的输入端发送第一输入信号，以将在衬底上施加的电压从第三电压切换为第一电压，并将在各个存储电容的第二极板上施加的电压从第四电压切换为第二电压；其中，第三电压低于第一电压，第四电压高于第二电压，第四电压高于第三电压。
控制模块1202还可用于：向第一反相器与第二反相器的共用输入端发送第一输入信号，以通过第一反相器将在衬底上施加的电压从第三电压切换为第一电压，并通过第二反相器将在各个存储电容的第二极板上施加的电压从第四电压切换为第二电压。
控制模块1202还可用于：在各个存储单元的存储电容充电预定时长后，向电压切换电路的输入端发送第二输入信号，以将在衬底上施加的电压从第一电压切换为第三电压，并将在各个存储电容的第二极板上施加的电压从第二电压切换为第四电压。
控制模块1202还可用于：向第一反相器与第二反相器的共用输入端发送第二输入信号，以通过第一反相器将在衬底上施加的电压从第一电压切换为第三电压，并将在各个存储电容的第二极板上施加的电压从第二电压切换为第四电压。
测试模块1204可用于在各个存储单元的存储电容充电预定时长后，对各个存储单元进行读取操作，以对动态随机存储器进行老炼测试。
确定模块1206可用于获得多个存储单元的区域大小；根据多个存储单元的区域大小确定第一电压与第二电压之间的电压差，以获得第一电压第二电压。
本公开实施例提供的装置中的各个模块的具体实现可以参照上述方法中的内容，此处不再赘述。
图13示出本公开实施例中一种电子设备的结构示意图。需要说明的是，图13示出的设备仅以计算机系统为示例，不应对本公开实施例的功能和使用范围带来任何限制。
如图13所示，设备1300包括中央处理单元(CPU)1301，其可以根据存储在只读存储器(ROM)1302中的程序或者从存储部分1308加载到随机访问存储器(RAM)1303中的程序而执行各种适当的动作和处理。在RAM 1303中，还存储有设备1300操作所需的各种程序和数据。CPU1301、ROM 1302以及RAM 1303通过总线1304彼此相连。输入/输出(I/O)接口1305也连接至总线1304。
以下部件连接至I/O接口1305：包括键盘、鼠标等的输入部分1306；包括诸如阴极射线管(CRT)、液晶显示器(LCD)等以及扬声器等的输出部分1307；包括硬盘等的存储部分1308；以及包括诸如LAN卡、调制解调器等的网络接口卡的通信部分1309。通信部分1309经由诸如因特网的网络执行通信处理。驱动器1310也根据需要连接至I/O接口1305。可拆卸介质1311，诸如磁盘、光盘、磁光盘、半导体存储器等等，根据需要安装在驱动器1310上，以便于从其上读出的计算机程序根据需要被安装入存储部分1308。
特别地，根据本公开的实施例，上文参考流程图描述的过程可以被实现为计算机软件程序。例如，本公开的实施例包括一种计算机程序产品，其包括承载在计算机可读介质上的计算机程序，该计算机程序包含用于执行流程图所示的方法的程序代码。在这样的实施例中，该计算机程序可以通过通信部分1309从网络上被下载和安装，和/或从可拆卸介质1311被安装。在该计算机程序被中央处理单元(CPU)1301执行时，执行本公开的系统中限定的上述功能。
需要说明的是，本公开所示的计算机可读介质可以是计算机可读信号介质或者计算机可读存储介质或者是上述两者的任意组合。计算机可读存储介质例如可以是——但不限于——电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。计算机可读存储介质的更具体的例子可以包括但不限于：具有一个或多个导线的电连接、便携式计算机磁盘、硬盘、随机访问存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑磁盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。在本公开中，计算机可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使 用或者与其结合使用。而在本公开中，计算机可读的信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了计算机可读的程序代码。这种传播的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。计算机可读的信号介质还可以是计算机可读存储介质以外的任何计算机可读介质，该计算机可读介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。计算机可读介质上包含的程序代码可以用任何适当的介质传输，包括但不限于：无线、电线、光缆、RF等等，或者上述的任意合适的组合。
附图中的流程图和框图，图示了按照本公开各种实施例的系统、方法和计算机程序产品的可能实现的体系架构、功能和操作。在这点上，流程图或框图中的每个方框可以代表一个模块、程序段、或代码的一部分，上述模块、程序段、或代码的一部分包含一个或多个用于实现规定的逻辑功能的可执行指令。也应当注意，在有些作为替换的实现中，方框中所标注的功能也可以以不同于附图中所标注的顺序发生。例如，两个接连地表示的方框实际上可以基本并行地执行，它们有时也可以按相反的顺序执行，这依所涉及的功能而定。也要注意的是，框图或流程图中的每个方框、以及框图或流程图中的方框的组合，可以用执行规定的功能或操作的专用的基于硬件的系统来实现，或者可以用专用硬件与计算机指令的组合来实现。
描述于本公开实施例中所涉及到的模块可以通过软件的方式实现，也可以通过硬件的方式来实现。所描述的模块也可以设置在处理器中，例如，可以描述为：一种处理器包括数据控制模块和测试模块。其中，这些模块的名称在某种情况下并不构成对该模块本身的限定，例如，控制模块还可以被描述为“向所连接的电路发送控制信号的模块”。
作为另一方面，本公开还提供了一种计算机可读介质，该计算机可读介质可以是上述实施例中描述的设备中所包含的；也可以是单独存在，而未装配入该设备中。上述计算机可读介质承载有一个或者多个程序，当上述一个或者多个程序被一个该设备执行时，使得该设备包括：通过在衬底上施加第一电压，并在各个存储单元的存储电容的第二极板上施加第二电压，对各个存储单元的存储电容进行充电，第一电压高于第二电压；在各个存储单元的存储电容充电预定时长后，对各个存储单元进行读取操作，以对动态随机存储器进行老炼测试。
以上具体地示出和描述了本公开的示例性实施例。应可理解的是，本公开不限于这里描述的详细结构、设置方式或实现方法；相反，本公开意图涵盖包含在所附权利要求的精神和范围内的各种修改和等效设置。

Claims (15)

  1. 一种动态随机存储器测试方法，其中，所述动态随机存储器包括衬底和多个存储单元，各个存储单元包括存储电容和第一晶体管，所述第一晶体管为NMOS晶体管，各个存储单元的存储电容的第一极板与对应第一晶体管的漏极电连接，各个存储单元的第一晶体管的P型硅基板与所述衬底电连接，所述方法包括：
    通过在所述衬底上施加第一电压，并在各个存储单元的存储电容的第二极板上施加第二电压，对各个存储单元的存储电容进行充电，所述第一电压高于所述第二电压；
    在各个存储单元的存储电容充电预定时长后，对所述各个存储单元进行读取操作，以对所述动态随机存储器进行老炼测试。
  2. 根据权利要求1所述的方法，其中，通过在所述衬底上施加第一电压，并在各个存储电容的第二极板上施加第二电压，对各个存储单元的存储电容进行充电，包括：
    向电压切换电路的输入端发送第一输入信号，以将在所述衬底上施加的电压从第三电压切换为所述第一电压，并将在各个存储电容的第二极板上施加的电压从第四电压切换为所述第二电压，以对各个存储单元的存储电容进行充电；
    其中，所述第三电压低于所述第一电压，所述第四电压高于所述第二电压，所述第四电压高于所述第三电压。
  3. 根据权利要求2所述的方法，其中，所述电压切换电路包括第一反相器和第二反相器，所述第一反相器的输入端与所述第二反相器的输入端相连接；
    向电压切换电路的输入端发送第一输入信号，以将在所述衬底上施加的电压从第三电压切换为所述第一电压，并将在各个存储电容的第二极板上施加的电压从第四电压切换为所述第二电压，包括：
    向所述第一反相器与所述第二反相器的共用输入端发送所述第一输入信号，以通过所述第一反相器将在所述衬底上施加的电压从所述第三电压切换为所述第一电压，并通过所述第二反相器将在各个存储电容的第二极板上施加的电压从第四电压切换为所述第二电压。
  4. 根据权利要求2所述的方法，其中，在各个存储单元的存储电容充电预定时长后，对所述各个存储单元进行读取操作，包括：
    在各个存储单元的存储电容充电预定时长后，向所述电压切换电路的输入端发送第二输入信号，以将在所述衬底上施加的电压从所述第一电压切换为所述第三电压，并将在各个存储电容的第二极板上施加的电压从所述第二电压切换为所述第四电压。
  5. 根据权利要求4所述的方法，其中，所述电压切换电路包括第一反相器和第二反相器，所述第一反相器与所述第二反相器共用输入端；
    向所述电压切换电路的输入端发送第二输入信号，以将在所述衬底上施加的电压从所述第一电压切换为所述第三电压，并将在各个存储电容的第二极板上施加的电压从所述第二电压切换为所述第四电压，包括：
    向所述第一反相器与所述第二反相器的共用输入端发送所述第二输入信号，以通过所述第一反相器将在所述衬底上施加的电压从所述第一电压切换为所述第三电压，并将在各个存储电容的第二极板上施加的电压从所述第二电压切换为所述第四电压。
  6. 根据权利要求1所述的方法，其中，还包括：
    获得所述多个存储单元的区域大小；
    根据所述多个存储单元的区域大小确定第一电压与第二电压之间的电压差，以获得所述第一电压和所述第二电压。
  7. 一种动态随机存储器测试装置，其中，所述动态随机存储器包括衬底和多个存储单元，各个存储单元包括存储电容和第一晶体管，所述第一晶体管为NMOS晶体管，各个存储单元的存储电容的第一极板与对应第一晶体管的漏极电连接，各个存储单元的第一晶体管的P型硅基板与所述衬底电连接，所述装置包括：
    控制模块，用于通过在所述衬底上施加第一电压，并在各个存储单元的存储电容的第二极板上施加第二电压，对各个存储单元的存储电容进行充电，所述第一电压高于所述第二电压；
    测试模块，用于在各个存储单元的存储电容充电预定时长后，对所述各个存储单元进行读取操作，以对所述动态随机存储器进行老炼测试。
  8. 一种动态随机存储器测试装置，其中，包括待测试动态随机存储器和电压切换电路，其中：
    所述待测试动态随机存储器包括衬底和多个存储单元，各个存储单元包括存储电容和第一晶体管，所述第一晶体管为NMOS晶体管，各个存储单元的存储电容的第一极板与对应第一晶体管的漏极电连接，各个存储单元的第一晶体管的P型硅基板与所述衬底电连接；
    所述电压切换电路包括第一输出端和第二输出端，所述电压切换电路的第一输出端与所述衬底电连接，用于向所述衬底施加第一电压，所述电压切换电路的第二输出端与各个存储电容的第二极板电连接，用于在各个存储电容的第二极板上施加第二电压，所述第一电压高于所述第二电压，以对各个存储单元的存储电容进行充电。
  9. 根据权利要求8所述的装置，其中，所述电压切换电路包括第一反相器和第二反相器，所述第一反相器的输入端与所述第二反相器的输入端相连接，所述第一反相器的输出端为所述第一输出端，所述第二反相器的输出端为所述第二输出端。
  10. 根据权利要求9所述的装置，其中，所述第一反相器与所述第二反相器均为CMOS晶体管。
  11. 根据权利要求10所述的装置，其中，第一反相器的NMOS晶体管的漏极、PMOS晶体管的漏极与所述第一输出端相连接，第一反相器的PMOS晶体管的源极的输入电压为所述第一电压，第一反相器的NMOS晶体管的源极的输入电压为第三电压；
    第二反相器的NMOS晶体管的漏极、PMOS晶体管的漏极与所述第二输出端相连接，第二反相器的PMOS晶体管的源极的输入电压为所述第二电压，第二反相器的NMOS晶体管的源极的输入电压为第四电压，所述第四电压高于所述第三电压；
    所述第一反相器的输入端与所述第二反相器的输入端用于接收第一输入信号，以使所述第一反相器的PMOS晶体管和所述第二反相器的PMOS晶体管导通，以及第一反相器的NMOS晶体管和第二反相器的NMOS晶体管截止。
  12. 根据权利要求11所述的装置，其中，所述第一反相器的输入端与所述第二反相器的输入端还用于接收第二输入信号，以使所述第一反相器的PMOS晶体管和所述第二反相器的PMOS晶体管截止，以及第一反相器的NMOS晶体管和第二反相器的NMOS晶体管导通。
  13. 根据权利要求10所述的装置，其中，第一反相器的NMOS晶体管的漏极、PMOS晶体管的漏极与所述第一输出端相连接，第一反相器的NMOS晶体管的源极的输入电压为所述第一电压，第一反相器的PMOS晶体管的源极的输入电压为第三电压；
    第二反相器的NMOS晶体管的漏极、PMOS晶体管的漏极与所述第二输出端相连接，第二反相器的NMOS晶体管的源极的输入电压为所述第二电压，第二反相器的PMOS晶体管的源极的输入电压为第四电压，所述第四电压高于所述第三电压；
    所述第一反相器的输入端与所述第二反相器的输入端用于接收第一输入信号，以使所述第一反相器的NMOS晶体管和所述第二反相器的NMOS晶体管导通，以及第一反相器的PMOS晶体管和第二反相器的PMOS晶体管截止。
  14. 根据权利要求13所述的装置，其中，所述第一反相器的输入端与所述第二反相器的输入端还用于接收第二输入信号，以使所述第一反相器的NMOS晶体管和所述第二反相器的NMOS晶体管截止，以及第一反相器的PMOS晶体管和第二反相器的PMOS晶体管导通。
  15. 根据权利要求8所述的装置，其中，所述电压切换电路的第一输出端通过连接插塞与所述衬底电连接。
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