CN1885557B - 半导体元件及形成半导体元件的方法 - Google Patents
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Abstract
本发明提供一种半导体元件及形成半导体元件的方法,具体涉及一种具有降低源极或漏极区域中掺杂物扩散的PMOS晶体管及其形成方法。PMOS晶体管包括掺杂P型杂质及扩散延迟材料的源极或漏极区域。PMOS晶体管更包括一栅极介电层,位于半导体基板的沟道上、一栅极电极,位于栅极介电层之上以及一轻掺杂源极或漏极区域对齐栅极电极的边缘。其中扩散延迟材料较佳包括碳、氟、氮或上述材料的组合。本发明由于扩散延迟材料减少了源极或漏极区域的扩散,因此源极或漏极区域的片电阻降低,可形成较陡峭的接面以及改善短沟道效应。
Description
技术领域
本发明有关于一种晶体管的制程,特别有关于降低PMOS半导体元件中源极或漏极区域杂质的扩散。
背景技术
随着晶体管尺寸的缩小,需要较浅的源极或漏极接面来维持短沟道。源极或漏极接面的尺寸缩小,使源极或漏极的片电阻提高及多晶硅栅极空乏增加,进而降低驱动电流。
为了降低多晶硅栅极空乏效应及源极或栅极电阻,最好能够提高源极或漏极区域的掺杂浓度。然而随着掺杂浓度的增加,源极或漏极区域的扩散行为也随之增加,产生明显的短沟道效应。
传统上控制掺杂物扩散的方法是降低退火制程,例如快速退火制程(rapid thermal anneal,RTA)的退火温度,但是降低温度会使源极或漏极区域内杂质的活性受影响,而造成不良的驱动电流。
也有其他用来降低扩散以及维持掺杂轮廓的方法,美国专利5885861揭露一种用来限制P型或N型杂质扩散的方法。如图1所示,栅极电极6形成在基板2上。将P型杂质及N型杂质分别掺杂于PMOS元件及NMOS元件的栅极电极6与轻掺杂源极或漏极区域8。箭头10代表掺杂制程。就N型元件而言,共掺杂氮及氟于栅极电极6与轻掺杂区域8,就P型元件而言,共掺杂氮及碳于栅极电极6与轻掺杂区域8。其中氮、碳及氟具有延迟掺杂物扩散的功能。因此在后续的退火制程中能有效控制掺杂物的扩散,使得轻掺杂区域8具有较高的浓度及限制掺杂区范围。
为了达到更好的效果,N型杂质的扩散也必须受限制。美国专 利案号2004/0102013揭露一种限制NMOS元件中深源极或漏极区域16内磷掺杂轮廓的方法,如图2所示。在基板20上形成栅极电极12后,以N型掺杂物,例如砷,进行掺杂以形成轻掺杂区域14,接着形成间隙壁11。箭头22代表掺杂制程,以磷进行掺杂形成深源极或漏极区域16。此外,也将氟及碳掺杂至相同区域。氟及碳的掺杂可降低磷的扩散,并改善驱动电流而降低短沟道效应。
然而这些方法并非针对PMOS元件中源极或漏极区域内杂质的扩散。虽然美国专利5885861中揭露碳可用来延迟PMOS元件中轻掺杂区域内P型掺杂物的扩散,但其中并未提在PMOS元件中形成源极或漏极区时,掺杂物种类以及掺杂条件(例如剂量、掺杂能量或剂量比例)的影响。值得注意的是,扩散延迟材料的种类及掺杂条件需最佳化,以产生扩散延迟的功效,若不改变而直接将NMOS元件的掺杂条件用于PMOS元件将无法得到扩散延迟的效果。
对于非常微小的元件,例如以65nm或更高阶制程制造的元件,源极或漏极的扩散会影响沟道区域,在如此微小的尺寸下,源极或漏极区域的杂质可能会扩散至轻掺杂区域,甚至会扩散至沟道区域。由于扩散使源极或漏极区域的掺杂浓度下降,会增加其片电阻。因此需要一种降低PMOS元件中掺杂区的扩散并改善短沟道效应的方法。
发明内容
有鉴于此,本发明提供一种PMOS晶体管及其形成方法,可降低自源极或漏极区域的扩散。
为达成上述目的,本发明提供一种PMOS晶体管,包括一源极或漏极区域,掺杂P型杂质以及至少一扩散延迟材料。该PMOS晶体管更包括一栅极介电层,位于一半导体基底内的一沟道上;一栅极电极,位于该栅极介电层之上;一轻掺杂源极或漏极区域,大抵对齐该栅极电极的边缘,其中该轻掺杂区域包括P型杂质。该扩散延迟材料较佳包括碳、氟、氮或上述材料的组合。栅极电极的掺杂物较佳与源极或漏极区域中的掺杂物相同。
为达上述目的,本发明提供一种降低扩散的方法,包括形成一掺杂P型杂质及一扩散延迟材料的源极或漏极区域。上述方法更包括在一半导体基板内的沟道上形成一栅极介电层;在该栅极介电层上形成一栅极电极;以该栅极电极作为掩膜,掺杂一额外的P型杂质以形成一轻掺杂区域;以及沿着栅极电极的侧壁形成一间隙壁。其中该P型杂质及该扩散延迟材料可同时或依序掺杂。
本发明是这样实现的:
本发明提供一种半导体元件,所述半导体元件包括:一半导体基底;一栅极介电层,位于该半导体基底内的一沟道上;一栅极电极,位于该栅极介电层之上;一轻掺杂源极或漏极区域,大抵对齐该栅极电极的边缘,其中该轻掺杂区域包括P型杂质;一栅极间隙壁,位于该栅极电极的侧边;一源极或漏极区域,位于在该半导体基底中,且大抵对齐该栅极间隙壁的边缘,其中该源极或漏极区域包括P型杂质;以及一扩散延迟区域,包括一扩散延迟材料,大抵对齐该栅极间隙壁的边缘,其中该扩散延迟区域比该源极或漏极区域深,其中该半导体基底的一曝露部分为注入有锗或氙的非晶态。
本发明所述的半导体元件,该扩散延迟材料包括碳、氟、氮或上述材料的组合。
本发明所述的半导体元件,该扩散延迟区域大抵与该源极或漏极区域重叠。
本发明所述的半导体元件,沿着该源极或漏极区域的边界的该扩散延迟区域比位于其余位置的该扩散延迟区域具有更高浓度的扩散延迟材料。
本发明所述的半导体元件,该P型杂质包括B、BF2或上述材料的组合。
本发明所述的半导体元件,该源极或漏极区域中P型杂质的浓度大于约1015/cm3。
本发明所述的半导体元件,该栅极电极包括扩散延迟材料及P型杂质。
本发明所述的半导体元件,该扩散延迟材料具有一第一浓度,而该P型杂质具有一第二浓度,且该第一与该第二浓度的比率约介于0.1至10。
本发明提供一种形成半导体元件的方法,所述形成半导体元件的方法包括:提供一半导体基底;在该半导体基底内的一沟道上形成一栅极介电层;在该栅极介电层之上形成一栅极电极;在该半导体基底的一曝露部分经由注入锗或氙转变形成非晶态;在该半导体基底中形成一轻掺杂源极或漏极区域,大抵对齐该栅极电极的边缘,其中该轻掺杂源极或漏极区域包括P型杂质;在该栅极电极的侧边形成一栅极间隙壁;在该半导体基底中形成一源极或漏极区域,大抵对齐该栅极间隙壁的边缘,其中该源极或漏极区域包括P型杂质;以及在该半导体基底中形成一扩散延迟区域,包括一扩散延迟材料,大抵对齐该栅极间隙壁的边缘,其中该扩散延迟区域比该源极或漏极区域深。
本发明所述的形成半导体元件的方法,该扩散延迟材料包括碳、氟、氮或上述材料的组合。
本发明所述的形成半导体元件的方法,该扩散延迟区域大抵与该源极或漏极区域重叠。
本发明所述的形成半导体元件的方法,沿着该源极或漏极区域的边界的该扩散延迟区域比位于其余位置的该扩散延迟区域具有更高浓度的扩散延迟材料。
本发明所述的形成半导体元件的方法,该P型杂质包括B、BF2或上述材料的组合。
本发明所述的形成半导体元件的方法,该源极或漏极区域中P型杂质的浓度大于约1015/cm3。
本发明所述的形成半导体元件的方法,该扩散延迟材料具有一第一浓度,而该P型杂质具有一第二浓度,且该第一与该第二浓度的比率约介于0.1至10。
由于扩散延迟材料减少了源极或漏极区域的扩散,因此源极或漏极区域的片电阻降低,可形成较陡峭的接面以及改善短沟道效应。
附图说明
图1为现有形成晶体管的方法,其中氮及氟用来降低P型杂质的扩散,而氮及碳则用来降低N型杂质的扩散;
图2为现有利用共掺杂碳或氟与磷来制造NMOS晶体管的方法;
图3至图7为本发明PMOS晶体管制程剖面图;
图8为本发明掺杂浓度随深度的变化。
具体实施方式
为了让本发明的上述和其他目的、特征和优点能更明显易懂,下文特举一较佳实施例,并配合所附图示,作详细说明如下:
图3显示在基板40上形成栅极介电层44及栅极电极46,基板40较佳为硅、锗化硅、锗化硅上的应变硅、硅覆绝缘层(SOI)、锗化硅覆绝缘层(SGOI)或锗覆绝缘层(GOI)。栅极介电层44较佳为高介电常数材料。栅极电极层46较佳为多晶硅、金属或金属硅化物,形成在栅极介电层44之上。
视情况而定,可针对栅极电极46及露出的基板40进行预非晶化注入制程(pre-amorphization implantation,PAI),以降低掺杂物沟道效应(dopant channeling effect),并提升掺杂物的活性,在一较佳实施例中,可注入锗或/及氙。预非晶化注入制程(PAI)可预防后续掺杂的杂质在晶格结构间产生沟道,以及预防掺杂超 过预期的深度。经过PAI后,至少部分栅极电极46的顶部及基板40露出的部分转变形成非晶态。
图4显示源极或漏极的轻掺杂区(LDD)52的形成。轻掺杂区52是利用P型杂质,例如B、BF2,注入所形成。箭头50代表注入制程,较佳为垂直注入。也可视需要进行轻掺杂区中掺杂物的活化制程。
图5显示间隙壁54形成在栅极介电层44及栅极电极46的侧壁。根据现有技术,间隙壁54较佳的形成方法为,在所有区域上形成一坦覆性的介电层,接着进行非等向性蚀刻制程,移除介电层水平部分,即形成间隙壁54。
图6显示源极或漏极区域60及扩散延迟区域62的形成。为了明确标示两区域,而以不同的图案显示,实际上,两者可为单一区域或为可分辨的两区域。箭头56表示注入扩散延迟材料与P型杂质,以形成源极或漏极区域,并利用间隙壁54作为注入时的掩膜。其中P型杂质,例如B或/与BF2,的掺杂浓度较佳约大于1015/cm3,最佳约介于1015/cm3至1017/cm3。
图6也显示了注入扩散延迟材料形成的扩散延迟区域62,其中扩散延迟杂质较佳为碳、氟、氮或上述材料的组合。值得注意的是,扩散延迟区域62较佳自基板40的表面延伸至基板40内。因此扩散延迟区域包括源极或漏极区域60以及延伸至源极或漏极区域60下的部分。扩散延迟区域62的掺杂剂量约介于1014/cm3至1016/cm3。其掺杂深度D1部分取决于注入时的能量,其注入能量约介于1KeV至50KeV,可形成深度约5nm至100nm。此外,P型杂质与扩散延迟材料的比率较佳约0.1至10。
源极或漏极区域60较佳与扩散延迟区域62重叠。为了获得最佳的效果,扩散延迟区域62较佳大抵围住源极或漏极区域60,虽然源极或漏极区域60也可围住扩散延迟区域62。较佳在沿着源极 或漏极区域60的边界具有高浓度的扩散延迟材料,特别是在底部边界。扩散延迟材料的深度D1可利用注入时的能量进行调整。在一较佳实施例中,可依序形成源极或漏极区域60以及扩散延迟区域62,且制程顺序颠倒并不影响最后元件的特性。在其他实施例中,源极或漏极区域60与扩散延迟区域62也可同时形成。
当形成源极或漏极区域60以及扩散延迟区域62时,较佳在栅极电极46中掺杂相同的杂质。然而栅极电极也可在注入步骤中以掩膜遮蔽。通过掺杂P型杂质及扩散延迟材料不只增加掺物浓度以及降低空乏效应,也可减少杂质扩散进入栅极电极46与栅极介电层44,因此改善元件的可靠度。
接着活化上述注入的掺杂物。可利用传统的加热制程,例如加热炉退火、快速退火制程(RTA)、激光退火或快闪退火(flashanneal)。在活化过程中,源极或漏极区域60及栅极电极46中的掺杂物会产生些微扩散,但随着共掺杂的扩散延迟材料注入于扩散路径上,则扩散现象趋缓,使得源极或漏极区域60具有较高的杂质浓度,因此具有较高电流驱动力。特别是可借此减少掺杂物扩散入沟道,以改善短沟道效应。
图7显示形成硅化物70、接触蚀刻停止层(CESL)72、层间介电层(ILD)74、接触插塞76以及金属线78后的结构。为了形成硅化物70,先在元件上形成钴、镍、铒、钼或铂的薄金属层,接着将元件退火,以在上述沉积的金属层与下方露出的硅区域间形成硅化物,之后移除剩余的金属层。其中较佳以毯覆性地沉积接触蚀刻停止层(CESL)72,用来提供下层元件应力以加强载流子移动能力,并保护下层结构避免后续蚀刻层间介电层74时受到伤害。接着在接触蚀刻停止层(CESL)上沉积层间介电层74,并图案化形成接触开口。之后形成接触插塞76及金属线78。由于上述制程为现有技术,因此不重复描述。
图8显示本发明较佳实施例扩散延迟的效果,其中硼的浓度为掺杂深度的函数。曲线82代表经过预非晶化注入及共掺杂硼及碳的第一元件。曲线84代表的经过硼注入的第二元件。其中曲线82的坡度较曲线84陡峭。由曲线84可得知,第二元件的接面深度约404埃。由于扩散延迟的效果,第一元件的接面深度低于第二元件约256埃。由于接面深度的关系,第一元件的片电阻也低于第二元件。因此,图8中硼浓度的分布图证明了扩散延迟材料的效果。
更进一步的实验结果显示注入硼或/与BF2以及共掺杂氟或碳明显的降低了元件的片电阻。
本发明的较佳实施例是利用共掺杂碳、氟或氮明显改善了PMOS元件的特性。本发明较佳实施力具有许多优点,第一,较少的扩散以提高掺杂区的浓度,因此片电阻降低。第二,较陡峭的浓度分布曲线代表较少的杂质扩散入栅极介电层,因此元件具有较佳的栅极氧化层完整性,以及较佳的临界电压控制。第三,扩散延迟效果能维持栅极电极与源极或漏极区域中掺杂物的高浓度,因此饱和电流增加。
虽然本发明已通过较佳实施例说明如上,但该较佳实施例并非用以限定本发明。本领域的技术人员,在不脱离本发明的精神和范围内,应有能力对该较佳实施例做出各种更改和补充,因此本发明的保护范围以权利要求书的范围为准。
附图中符号的简单说明如下:
基板:1
栅极电极:6
箭头:10
轻掺杂区域:8
基板:20
栅极电极:12
箭头:22
深源极或漏极区域:16
基板:40
栅极介电层:44
栅极电极:46
注入制程:50
轻掺杂区域:52
间隙壁:54
注入制程:56
扩散延迟区域:62
源极或漏极区域:60
硅化物:70
接触蚀刻停止层:72
层间介电层:74
接触插塞:76
金属线:78
曲线:82、84
Claims (15)
1.一种半导体元件,其特征在于,所述半导体元件包括:
一半导体基底;
一栅极介电层,位于该半导体基底内的一沟道上;
一栅极电极,位于该栅极介电层之上;
一轻掺杂源极或漏极区域,对齐该栅极电极的边缘,其中该轻掺杂区域包括P型杂质;
一栅极间隙壁,位于该栅极电极的侧边;
一源极或漏极区域,位于在该半导体基底中,且对齐该栅极间隙壁的边缘,其中该源极或漏极区域包括P型杂质;以及
一扩散延迟区域,包括一扩散延迟材料,对齐该栅极间隙壁的边缘,其中该扩散延迟区域比该源极或漏极区域深,
其中该半导体基底的一曝露部分为注入有锗或氙的非晶态。
2.根据权利要求1所述的半导体元件,其特征在于,该扩散延迟材料包括碳、氟、氮或上述材料的组合。
3.根据权利要求1所述的半导体元件,其特征在于,该扩散延迟区域与该源极或漏极区域重叠。
4.根据权利要求1所述的半导体元件,其特征在于,沿着该源极或漏极区域的边界的该扩散延迟区域比位于其余位置的该扩散延迟区域具有更高浓度的扩散延迟材料。
5.根据权利要求1所述的半导体元件,其特征在于,该P型杂质包括B、BF2或上述材料的组合。
6.根据权利要求5所述的半导体元件,其特征在于,该源极或漏极区域中P型杂质的浓度大于1015/cm3。
7.根据权利要求1所述的半导体元件,其特征在于,该栅极电极包括扩散延迟材料及P型杂质。
8.根据权利要求1所述的半导体元件,其特征在于,该扩散延迟材料具有一第一浓度,而该P型杂质具有一第二浓度,且该第一与该第二浓度的比率介于0.1至10。
9.一种形成半导体元件的方法,其特征在于,所述形成半导体元件的方法包括:
提供一半导体基底;
在该半导体基底内的一沟道上形成一栅极介电层;
在该栅极介电层之上形成一栅极电极;
在该半导体基底的一曝露部分经由注入锗或氙转变形成非晶态;
在该半导体基底中形成一轻掺杂源极或漏极区域,对齐该栅极电极的边缘,其中该轻掺杂源极或漏极区域包括P型杂质;
在该栅极电极的侧边形成一栅极间隙壁;
在该半导体基底中形成一源极或漏极区域,对齐该栅极间隙壁的边缘,其中该源极或漏极区域包括P型杂质;以及
在该半导体基底中形成一扩散延迟区域,包括一扩散延迟材料,对齐该栅极间隙壁的边缘,其中该扩散延迟区域比该源极或漏极区域深。
10.根据权利要求9所述的形成半导体元件的方法,其特征在于,该扩散延迟材料包括碳、氟、氮或上述材料的组合。
11.根据权利要求9所述的形成半导体元件的方法,其特征在于,该扩散延迟区域与该源极或漏极区域重叠。
12.根据权利要求9所述的形成半导体元件的方法,其特征在于,沿着该源极或漏极区域的边界的该扩散延迟区域比位于其余位置的该扩散延迟区域具有更高浓度的扩散延迟材料。
13.根据权利要求9所述的形成半导体元件的方法,其特征在于,该P型杂质包括B、BF2或上述材料的组合。
14.根据权利要求13所述的形成半导体元件的方法,其特征在于,该源极或漏极区域中P型杂质的浓度大于1015/cm3。
15.根据权利要求9所述的形成半导体元件的方法,其特征在于,该扩散延迟材料具有一第一浓度,而该P型杂质具有一第二浓度,且该第一与该第二浓度的比率介于0.1至10。
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KR101263648B1 (ko) * | 2007-08-31 | 2013-05-21 | 삼성전자주식회사 | 핀 전계 효과 트랜지스터 및 그 제조 방법. |
US8232605B2 (en) * | 2008-12-17 | 2012-07-31 | United Microelectronics Corp. | Method for gate leakage reduction and Vt shift control and complementary metal-oxide-semiconductor device |
CN101770950B (zh) * | 2008-12-31 | 2012-08-22 | 中芯国际集成电路制造(上海)有限公司 | 轻掺杂漏极的形成方法 |
US8173503B2 (en) * | 2009-02-23 | 2012-05-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fabrication of source/drain extensions with ultra-shallow junctions |
JP5285519B2 (ja) * | 2009-07-01 | 2013-09-11 | パナソニック株式会社 | 半導体装置及びその製造方法 |
US8659112B2 (en) | 2009-12-18 | 2014-02-25 | Texas Instruments Incorporated | Carbon and nitrogen doping for selected PMOS transistor on an integrated circuit |
CN102122618B (zh) * | 2010-01-08 | 2013-03-13 | 上海华虹Nec电子有限公司 | 获得交替的p型和n型半导体的方法 |
CN102214561A (zh) * | 2010-04-06 | 2011-10-12 | 上海华虹Nec电子有限公司 | 超级结半导体器件及其制造方法 |
CN102543736B (zh) * | 2010-12-15 | 2014-10-01 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件结构及其制作方法 |
CN103227105A (zh) * | 2013-03-29 | 2013-07-31 | 昆山东日半导体有限公司 | 一种附磷涂硼工艺 |
CN103346167A (zh) * | 2013-06-24 | 2013-10-09 | 成都瑞芯电子有限公司 | 可有效降低栅极电阻和栅极电容的柱栅金氧半场效晶体管及其制造方法 |
CN104637879A (zh) * | 2013-11-06 | 2015-05-20 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制备方法 |
KR102278608B1 (ko) * | 2017-03-10 | 2021-07-19 | 삼성디스플레이 주식회사 | 유기 발광 표시 장치 및 유기 발광 표시 장치의 제조 방법 |
CN110660669B (zh) * | 2018-06-29 | 2024-01-26 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6294415B1 (en) * | 2000-04-26 | 2001-09-25 | United Microelectronics Corp. | Method of fabricating a MOS transistor |
US6355543B1 (en) * | 1998-09-29 | 2002-03-12 | Advanced Micro Devices, Inc. | Laser annealing for forming shallow source/drain extension for MOS transistor |
US6503817B1 (en) * | 1999-09-23 | 2003-01-07 | Advanced Micro Devices, Inc. | Method for establishing dopant profile to suppress silicidation retardation effect in CMOS process |
CN1449002A (zh) * | 2002-03-28 | 2003-10-15 | 华邦电子股份有限公司 | 金氧半晶体管的自对准硅化物的制备方法 |
Family Cites Families (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4755865A (en) * | 1986-01-21 | 1988-07-05 | Motorola Inc. | Means for stabilizing polycrystalline semiconductor layers |
US5108935A (en) * | 1990-11-16 | 1992-04-28 | Texas Instruments Incorporated | Reduction of hot carrier effects in semiconductor devices by controlled scattering via the intentional introduction of impurities |
KR0136935B1 (ko) * | 1994-04-21 | 1998-04-24 | 문정환 | 메모리 소자의 제조방법 |
US5585286A (en) * | 1995-08-31 | 1996-12-17 | Lsi Logic Corporation | Implantation of a semiconductor substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant subsequently implanted into the substrate to form P- LDD region of a PMOS device |
US5719425A (en) * | 1996-01-31 | 1998-02-17 | Micron Technology, Inc. | Multiple implant lightly doped drain (MILDD) field effect transistor |
US6410409B1 (en) * | 1996-10-31 | 2002-06-25 | Advanced Micro Devices, Inc. | Implanted barrier layer for retarding upward diffusion of substrate dopant |
KR100232206B1 (ko) * | 1996-12-26 | 1999-12-01 | 김영환 | 반도체 소자의 제조방법 |
US5933721A (en) * | 1997-04-21 | 1999-08-03 | Advanced Micro Devices, Inc. | Method for fabricating differential threshold voltage transistor pair |
US5885861A (en) * | 1997-05-30 | 1999-03-23 | Advanced Micro Devices, Inc. | Reduction of dopant diffusion by the co-implantation of impurities into the transistor gate conductor |
US6225151B1 (en) * | 1997-06-09 | 2001-05-01 | Advanced Micro Devices, Inc. | Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion |
US6018180A (en) * | 1997-12-23 | 2000-01-25 | Advanced Micro Devices, Inc. | Transistor formation with LI overetch immunity |
JP2000012856A (ja) * | 1998-06-26 | 2000-01-14 | Sony Corp | Mosトランジスタの製造方法 |
US6030863A (en) * | 1998-09-11 | 2000-02-29 | Taiwan Semiconductor Manufacturing Company | Germanium and arsenic double implanted pre-amorphization process for salicide technology |
US6271095B1 (en) * | 1999-02-22 | 2001-08-07 | Advanced Micro Devices, Inc. | Locally confined deep pocket process for ULSI mosfets |
US6268640B1 (en) * | 1999-08-12 | 2001-07-31 | International Business Machines Corporation | Forming steep lateral doping distribution at source/drain junctions |
US6440805B1 (en) * | 2000-02-29 | 2002-08-27 | Mototrola, Inc. | Method of forming a semiconductor device with isolation and well regions |
US6399452B1 (en) * | 2000-07-08 | 2002-06-04 | Advanced Micro Devices, Inc. | Method of fabricating transistors with low thermal budget |
US6475885B1 (en) * | 2001-06-29 | 2002-11-05 | Advanced Micro Devices, Inc. | Source/drain formation with sub-amorphizing implantation |
US6555439B1 (en) * | 2001-12-18 | 2003-04-29 | Advanced Micro Devices, Inc. | Partial recrystallization of source/drain region before laser thermal annealing |
US6680250B1 (en) * | 2002-05-16 | 2004-01-20 | Advanced Micro Devices, Inc. | Formation of deep amorphous region to separate junction from end-of-range defects |
US20040031970A1 (en) * | 2002-08-13 | 2004-02-19 | Srinivasan Chakravarthi | Process for retarding lateral diffusion of phosphorous |
US6657223B1 (en) * | 2002-10-29 | 2003-12-02 | Advanced Micro Devices, Inc. | Strained silicon MOSFET having silicon source/drain regions and method for its fabrication |
US20040102013A1 (en) * | 2002-11-27 | 2004-05-27 | Jack Hwang | Codoping of source drains using carbon or fluorine ion implants to improve polysilicon depletion |
JP2005033098A (ja) * | 2003-03-05 | 2005-02-03 | Nec Electronics Corp | 半導体装置及びその製造方法 |
US20040188774A1 (en) * | 2003-03-31 | 2004-09-30 | Sanyo Electric Co., Ltd. | Semiconductor device and method of fabricating semiconductor device |
JP2005136351A (ja) * | 2003-10-31 | 2005-05-26 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US7545001B2 (en) * | 2003-11-25 | 2009-06-09 | Taiwan Semiconductor Manufacturing Company | Semiconductor device having high drive current and method of manufacture therefor |
US7271443B2 (en) * | 2004-08-25 | 2007-09-18 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method for the same |
US7091097B1 (en) * | 2004-09-03 | 2006-08-15 | Advanced Micro Devices, Inc. | End-of-range defect minimization in semiconductor device |
US7135372B2 (en) * | 2004-09-09 | 2006-11-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained silicon device manufacturing method |
JP2006100599A (ja) * | 2004-09-29 | 2006-04-13 | Toshiba Corp | 半導体装置及びその製造方法 |
US7163878B2 (en) * | 2004-11-12 | 2007-01-16 | Texas Instruments Incorporated | Ultra-shallow arsenic junction formation in silicon germanium |
US7320921B2 (en) * | 2005-03-22 | 2008-01-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Smart grading implant with diffusion retarding implant for making integrated circuit chips |
US20060234455A1 (en) * | 2005-04-19 | 2006-10-19 | Chien-Hao Chen | Structures and methods for forming a locally strained transistor |
US7172954B2 (en) * | 2005-05-05 | 2007-02-06 | Infineon Technologies Ag | Implantation process in semiconductor fabrication |
-
2005
- 2005-06-21 US US11/157,515 patent/US20060284249A1/en not_active Abandoned
- 2005-11-24 TW TW094141261A patent/TW200701455A/zh unknown
- 2005-12-26 CN CN2005101324901A patent/CN1885557B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6355543B1 (en) * | 1998-09-29 | 2002-03-12 | Advanced Micro Devices, Inc. | Laser annealing for forming shallow source/drain extension for MOS transistor |
US6503817B1 (en) * | 1999-09-23 | 2003-01-07 | Advanced Micro Devices, Inc. | Method for establishing dopant profile to suppress silicidation retardation effect in CMOS process |
US6294415B1 (en) * | 2000-04-26 | 2001-09-25 | United Microelectronics Corp. | Method of fabricating a MOS transistor |
CN1449002A (zh) * | 2002-03-28 | 2003-10-15 | 华邦电子股份有限公司 | 金氧半晶体管的自对准硅化物的制备方法 |
Non-Patent Citations (1)
Title |
---|
US 6503817 B1,说明书第2栏第44-56行、图1-3. |
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