CN1802071A - 模块衬底和盘设备 - Google Patents

模块衬底和盘设备 Download PDF

Info

Publication number
CN1802071A
CN1802071A CNA2005101253658A CN200510125365A CN1802071A CN 1802071 A CN1802071 A CN 1802071A CN A2005101253658 A CNA2005101253658 A CN A2005101253658A CN 200510125365 A CN200510125365 A CN 200510125365A CN 1802071 A CN1802071 A CN 1802071A
Authority
CN
China
Prior art keywords
circuit pattern
substrate
active element
module substrate
installation region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2005101253658A
Other languages
English (en)
Inventor
青木慎
细田邦康
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of CN1802071A publication Critical patent/CN1802071A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B25/00—Apparatus characterised by the shape of record carrier employed but not specific to the method of recording or reproducing, e.g. dictating apparatus; Combinations of such apparatus
    • G11B25/04—Apparatus characterised by the shape of record carrier employed but not specific to the method of recording or reproducing, e.g. dictating apparatus; Combinations of such apparatus using flat record carriers, e.g. disc, card
    • G11B25/043—Apparatus characterised by the shape of record carrier employed but not specific to the method of recording or reproducing, e.g. dictating apparatus; Combinations of such apparatus using flat record carriers, e.g. disc, card using rotating discs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/48—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed
    • G11B5/4806—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed specially adapted for disk drive assemblies, e.g. assembly prior to operation, hard or flexible disk drives
    • G11B5/4846—Constructional details of the electrical connection between arm and support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01009—Fluorine [F]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/015—Fluoropolymer, e.g. polytetrafluoroethylene [PTFE]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Moving Of Heads (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

本发明公开了一种模块衬底，包括绝缘衬底(1)；至少形成于绝缘衬底(1)的主表面上的电路图案(2)；形成于包括有电路图案(2)的绝缘衬底(1)的主表面上的保护膜(7)，以便显露出电路图案(2)中的安装区域；安装于所述电路图案中的安装区域上的有源元件(11)；至少在有源元件(11)的安装区域附近形成于保护膜(7)上的氟树脂膜(10)；以及填充在有源元件(11)与电路图案(2)中的安装区域之间的底层填料(14)。

Description

模块衬底和盘设备
技术领域
本发明的一个实施例涉及一种模块衬底和盘设备。
背景技术
作为一种已知的常规衬底，存在着这样一种模块衬底，其中包括裸露芯片在内的有源元件被安装在印刷线路板上的电路图案中。当在常规的模块衬底中将有源元件安装在印刷线路板上的电路图案中时，首先，将有源元件上的电极焊接在印刷线路板上的电路图案中。接着，在印刷线路板与有源元件之间注射一种用于形成底层填料的树脂溶液，并且进行固化来形成底层填料。以这种方式，确保了将有源元件与印刷线路板的机械式固定和类似固定。
但是，在注射用于形成底层填料的树脂溶液时，在某些情况下，树脂溶液会从印刷线路板上安装有有源元件的区域流出，散布到外围部件，并且由此有可能出现下述问题。也就是说，例如，在这样一种模块衬底中，即使用了其中包括一个由环氧树脂作为其主要材料制成的刚性绝缘衬底的印刷线路板，底层填料散布到外围部件会在更换有源元件的过程中产生麻烦。另一方面，在这样一种模块衬底中，即使用了其中包括一个由聚酰亚胺膜制成的柔性绝缘衬底的印刷线路板，由于底层填料由一种高性能固化树脂作为其主要成分制成，所以衬底上散布有底层填料的部分会失去其柔性。还有，如果所述膜在底层填料散布的部分处发生了弯曲，那么这部分底层填料会发生剥落而形成碎屑，并且由此对于盘设备来说，有可能对装载在设备中的介质产生不利影响。
作为一种解决前述问题的方案，USP 6707162公开了这样一种技术，即针对印刷线路板上的各个电路图案部分设置一个对齐区域，其中待安装的有源元件与底层填料固定在一起，以便扩大它们之间的间距。在USP 6291264中公开了另外一种解决方案，其中设置了一个沟槽来在将有源元件与底层填料固定起来的过程中阻止底层填料流出。但是，由于安装部件的密度已经提高，所以这种考虑了一个用于供底层填料溶液流出的间隙或者形成沟槽的部件排布方式在实际中非常困难。
另一方面，日本专利申请特开(KOKAI)公告No.2001-102700公开了一种柔性印刷线路板，其甚至可以在如同移动电话那样多次打开/闭合操作(例如大约为1000次)之后防止断开。这种柔性线路板例如用于可折叠式移动电话的铰链部分，其会被反复地弯曲和拉伸，并且具有这样一种结构，即电路图案上的金属层或者类似部分被置于一对薄膜之间，并且至少这些薄膜中之一由一种耐磨构件或者一种抗磨构件制成。
还有，日本专利申请特开(KOKAI)公告No.6-326445公开了一种电路板，其中在各个阻焊剂膜的表面上附着一种耐热绝缘介质，这种耐热绝缘介质具有排斥熔融焊料的特性(也就是说例如一种由非晶体氟树脂作为其主要成分制成的耐热绝缘介质)，其中所述阻焊剂膜被制成远离布线图案中的各个岛。
附图说明
图1是一个示意图，示出了一个按照本发明第一实施例的模块衬底的横剖面；
图2A、2B、2C、2D、2E和2F均是示意图，示出了按照本发明第一实施例的模块衬底在制造这种衬底的工艺的各个相应步骤中的横剖面；
图3是一个示意图，示出了一个按照本发明第二实施例的模块衬底的横剖面；
图4A、4B、4C、4D、4E、4F、4G、4H、4I、4J、4K、4L和4M均是示意图，示出了按照本发明第二实施例的模块衬底在制造这种衬底的工艺的各个相应步骤中的横剖面；
图5是一个示意性透视图，示出了一个按照本发明第三实施例用作盘设备的硬盘驱动器(在下文中被称作HDD)；而
图6是一个示意性透视图，示出了在图5中示出的柔性模块衬底。
具体实施方式
下面将参照附图详细地对按照本发明的实施例的模块衬底和盘设备进行描述。
(第一实施例)
图1是一个示意图，示出了一个按照本发明第一实施例的模块衬底的横剖面，该模块衬底装配有一个包括有刚性绝缘衬底的印刷线路板。
一个例如由玻璃环氧树脂制成的刚性绝缘衬底1，具有分别形成于上表面和下表面上的线路图案2和3。一个通孔4被制成贯穿刚性绝缘衬底1。岛5和6分别在通孔4的两个端部处形成于开口的附近。用作保护膜的阻焊剂膜7和8被形成在刚性绝缘衬底1的上表面和下表面上，来分别覆盖住电路图案2和3。形成于上表面侧的阻焊剂膜7在线路图案2中安装有有源元件和无源元件的部分处具有开口，并且在岛5所在的区域处具有开口。形成于后表面侧的阻焊剂膜8在岛6所在的区域处具有开口。利用前述结构，刚性绝缘衬底1、电路图案2和3、包括岛5和6的通孔4、以及阻焊剂7和8形成一个刚性印刷线路板9(在下文中被称作RPC)。
一个氟树脂膜10被至少贴敷在阻焊剂膜7上这些区域上，即这些区域位于安装有有源元件的区域的附近。
诸如裸露芯片1这样的有源元件上的电极12通过一种焊接材料13连接在电路图案2上的相应部分上，所述相应部分从位于RPC 9上表面侧的阻焊剂膜7上的开口(安装区域)中显露出来。一种底层填料14在安装区域中被设置在绝缘衬底1与裸露芯片11之间，来将裸露芯片11机械式固定在绝缘衬底1上。诸如芯片电阻器器这样的无源元件被连接在电路图案2中的相应部分上，这些相应部分从位于RPC 9上表面侧的阻焊剂膜7上的相应开口(安装区域)中显露出来。
除了裸露芯片之外，所述有源构件的可使用例子是芯片尺寸封装(CSP)、球栅阵列(BGA)、塑料球栅阵列(PBGA)、塑料细距球栅阵列(PFBGA)、多层塑料细距球栅阵列(Stacked PFBGA)以及倒装芯片球栅阵列(FCBGA)。
除了芯片电阻器之外，例如芯片电容器也可以用作所述无源元件。
所述氟树脂的可使用例子是聚四氟乙烯(PTFE)、四氟乙烯-全氟烷基乙烯醚共聚物(FEP)、四氟乙烯-乙烯共聚物(ETFE)、聚偏氟乙烯(PVDF)以及聚三氟氯乙烯(PCTFE)。
所希望的是，所述氟树脂膜必须具有5至50微米的厚度，并且更为优选的是5至20微米的厚度。
所述底层填料例如由一种填充有填料的环氧树脂制成。填料的一种例子是精细硅粉。精细硅粉以占据环氧树脂与精细硅粉总量的30至70％重量比进行混合。这种包含有环氧树脂和精细硅粉的底层填料例如能够从Henkel Japan有限公司以FP 4511或者FP 4546的商品名称购买到。
接下来，将参照图2A至2F对一种制造图1中所示模块衬底的方法进行描述。
首先，如图2A中所示，分别将铜箔21和22附着在例如由玻璃环氧树脂制成的刚性绝缘衬底1的上表面和下表面上，并且由此制备出一种所谓的双侧铜箔板。接下来，如图2B中所示，利用钻具或者类似器具贯穿所述双侧铜箔板制取一个孔23。接着，对所制得的衬底进行电镀(例如电镀铜)，来在铜箔21和22上形成铜电镀膜24和25，分别在图2C中所示。与此同时，在孔23所在的区域处形成一个通孔4。
接着，如图2D中所示，利用一种光致抗蚀图案(图中未示出)作为掩模对形成于刚性绝缘衬底1的上表面和下表面上的铜箔21和22以及铜电镀膜24和25进行选择性蚀刻。由此，在刚性绝缘衬底1的上表面和下表面上形成电路图案2和3以及与通孔4连通的岛5和6。接下来，如图2E中所示，在刚性绝缘衬底1的上表面和下表面上分别形成阻焊剂膜7和8，其中所述上表面和下表面上包括电路图案2和3以及岛5和6，以便使得电路图案2中安装有有源元件和无源元件的部分以及岛5所在的区域外露出来。由此，刚性印刷线路板(RPC)9得以制成。接下来，如图2F中所示，至少在阻焊剂膜7的某些部分上形成氟树脂膜10，其中所述部分位于安装有有源元件的区域的附近。氟树脂膜10可以通过采用一种利用粘结剂将具有预期图案的膜状氟树脂粘附在阻焊剂膜7上的方法或者一种利用印刷技术在阻焊剂膜7上涂敷氟树脂溶液并且随后进行印刷的方法得以制成。
此后，如在前述的图1中所示，诸如裸露芯片11这样的有源元件上的电极12通过焊接材料13连接在电路图案2中的相应部分上，所述相应部分从位于RPC 9上表面侧的阻焊剂膜7上的开口(安装区域)中显露出来。在这个安装区域中，例如从一个分配喷嘴将一种底层成形树脂溶液(例如一种包含有填料的环氧树脂溶液)滴入绝缘衬底1与裸露芯片11之间的间隙内，随后进行干燥和固化。以这种方式，形成一种底层填料14，来将裸露芯片11机械式固定在绝缘衬底1上。还有，诸如芯片电阻器15和16这样的无源元件被安装在电路图案2中的相应部分上，所述相应部分从位于RPC 9上表面侧的阻焊剂膜7上的相应开口(安装区域)显露出来。利用前述步骤，裸露芯片11、芯片电阻器15和16以及类似元件被安装在RPC 9上，由此制成一个模块衬底。
如前所述，按照第一实施例，印刷线路板9上的阻焊剂膜7的某些部分由氟树脂膜10包覆起来，其中所述部分至少位于有源元件安装区域的附近，而氟树脂膜10难以被浸湿并且具有高的斥水性。利用这种结构，能够在经由焊接材料13将诸如裸露芯片11这样的有源元件上的电极12连接到电路图案2中的相应部分上以便在相应的安装区域利用底层填料13将裸露芯片11机械式固定在绝缘衬底1上的过程中，防止底层填料13从印刷线路板9上的裸露芯片11的安装区域散布到外围部件。由此，无需类似于常规技术那样设置一个隆起或者沟槽来防止溶液流出，并且能够使得部件之间的间距变窄。因此，能够获得一种其中裸露芯片11和类似元件被以高密度安装起来的模块衬底。
与此同时，当在模块衬底中有源元件11损坏并且需要利用一个新的部件进行更换时，能够防止底层填料13从印刷线路板上的有源元件11的安装区域散布到外围部件，其中在所述模块衬底中有源元件11被安装在包括有刚性绝缘衬底1的印刷线路板9中。以这种方式，可以在不破坏所述外围部件的条件下轻易地对有源元件进行更换。
需要指出的是，在第一实施例中，在刚性印刷线路板中电路图案被分别形成在其两个表面上，但是本发明并不局限于这种结构。例如，替代性地，能够使用一种带有仅形成于其一个表面上的电路图案的刚性印刷线路板，或者一种带有形成于其内部的内层电路图案的刚性多层印刷线路板。
(第二实施例)
图3是一个示意图，示出了一个按照本发明第二实施例的模块衬底，该模块衬底装配有一个包括有柔性绝缘衬底的柔性印刷线路板。
柔性绝缘衬底31例如由聚酰亚胺制成，具有一个区域性形成的开口部分32。在柔性绝缘衬底31的上表面上形成有一个电路图案，该电路图案具有一个例如由Cr/Cu和Cu形成的分层结构，并且在下表面上(至少在对应于有源元件的区域，所述有源元件将在后面予以描述)形成有一个例如由SUS制成的衬板34。电路图案33的外露表面均例如包覆有一个Ni薄膜35。在包括有电路图案33的柔性绝缘衬底31上形成有一个例如由聚酰亚胺制成的包覆层(coverlay)36，该包覆层36用作一个保护膜。包覆层36在对应于电路图案33中的相应部分的区域处均具有开口，其中在所述相应部分中安装有有源元件。例如，在从相应开口中显露出来的电路图案33中的相应部分的相应Ni薄膜35上形成有一个Ni/Au薄膜37。如前所述，柔性绝缘衬底31、电路图案33、Ni薄膜35、Ni/Au薄膜27、衬板34以及包覆层36形成了一个柔性印刷线路板(在下文中被称作FPC)38。
氟树脂39被至少涂敷在包覆层36的某些区域上，所述区域位于安装有有源元件的区域附近。
有源元件(例如裸露芯片)40的电极(未示出)经由一种焊接材料41连接在从FPC 38的包覆层36的相应开口(安装区域)显露出来的电路图案33中的相应部分的Ni/Au薄膜37上。底层填料42在安装区域中被设置在包覆层36与裸露芯片40之间，由此将裸露芯片11机械式固定在包覆层36上。
正如结合第一实施例提及的那样，除了裸露芯片之外，所述有源元件的可使用例子是芯片尺寸封装(CSP)、球栅阵列(BGA)、塑料球栅阵列(PBGA)、塑料细距球栅阵列(PFBGA)、多层塑料细距球栅阵列(Stacked PFBGA)以及倒装芯片球栅阵列(FCBGA)。
作为所述氟树脂，可以采用类似于在第一实施例中提及的那些材料。优选的是，所述氟树脂膜必须具有5至50微米的厚度。
所述底层填料例如由一种填充有填料的环氧树脂制成。填料的一种例子是精细硅粉。精细硅粉以占据环氧树脂与精细硅粉总量的30至70％重量比进行混合。这种包含有环氧树脂和精细硅粉的底层填料例如能够从Henkel Jpan有限公司以FP 4511或者FP 4546的商品名称购买到。
接下来，将参照图4A至4M对一种制造图3中所示模块衬底的方法进行描述。
首先，如图4A中所示，例如在一个SUS制薄板51上形成一个感光性聚酰亚胺膜52。接着，如图4B中所示，对感光性聚酰亚胺膜52进行光刻来进行图案化处理，并且由此将柔性绝缘衬底31制成为在一个区域处具有开口部分32。
接下来，如图4C中所示，在包括有开口部分32的柔性绝缘衬底31的上表面上例如通过一种溅射方法形成一个由Cr/Cu制成的镀覆底层53。接着，如图4D中所示，在底层53的表面上包覆一个抗蚀膜，该抗蚀膜随后经受光刻处理，由此形成一个使电路图案形成部分露出的镀覆抗蚀图案54。此后，例如，执行电镀铜处理，其中SUS制薄板51和底层53被用作共用电极，由此形成一个Cu图案55。接着，如图4E中所示，将抗蚀图案54去除。
接下来，如图4F中所示，通过利用Cu图案55作为掩模进行蚀刻处理将底层53选择性地去除，由此形成一个电路图案33，该电路图案33具有一个由Cr/Cu和Cu形成的分层结构。接着，执行无电镀Ni镀敷，来如图4G中所示在电路图案33中的外露表面部分上形成一个Ni薄膜35。此后，除了开口部分32之外，在柔性绝缘衬底31上形成一个例如由聚酰亚胺制成的包覆层36。
接下来，如图4H中所示，选择性地去除覆盖住呈预定形式的电路图案33表面的包覆层部分36，来显露出位于电路图案33上的Ni薄膜35。此后，对所制得的衬底进行无电镀Ni镀敷和无电镀Au镀敷。由此，如图4I中所示，在Ni薄膜35的外露部分上形成一个Ni/Au薄膜37。接着，如图4J中所示，在包覆层36的整个表面上贴敷一个抗蚀膜56。还有，在SUS制薄板51的下表面上贴敷一个抗蚀膜，该抗蚀膜随后经受光刻处理，由此形成一个抗蚀图案57。利用抗蚀图案57作为掩模，通过蚀刻处理选择性地去除SUS制薄板51，来形成衬板34。此后，抗蚀膜56和抗蚀图案57被去除，并且由此制得一个如图4K中所示的柔性印刷线路板(FPC)38。接着，如图4L中所示，在包覆层36的某些部分上形成氟树脂膜39，其中所述部分位于安装有有源元件的区域附近。氟树脂膜39可以通过采用一种利用粘结剂将具有预期图案的膜状氟树脂粘附在包覆层36上的方法或者一种利用印刷技术在包覆层36上涂敷氟树脂溶液并且随后进行印刷的方法得以制成。
此后，如图4M中所示，诸如裸露芯片40这样的有源元件上的电极(未示出)通过焊接材料41连接在位于电路图案33上的Ni/Au薄膜37上，其中所述Ni/Au薄膜37从FPC 38的包覆层36上的开口(安装区域)中显露出来。在这个安装区域中，例如从一个分配喷嘴59将一种底层成形树脂溶液(例如一种包含有填料的环氧树脂溶液)滴入包覆层36与裸露芯片40之间的间隙内，随后进行干燥和固化。以这种方式，形成一种底层填料42，来将裸露芯片40机械式固定在绝缘衬底36上，如在前述图3中所示。由此，制得一个其中裸露芯片40和类似元件被安装在FPC 38上的柔性模块衬底。
如前所述，按照第二实施例，柔性印刷线路板(FPC)38的包覆层36上的某些部分包覆有氟树脂膜39，其中氟树脂膜39难以被浸湿并且具有高的斥水性，而所述部分至少位于有源元件安装区域的附近。利用这种结构，能够在经由焊接材料41将诸如有源元件(比如裸露芯片)40上的电极12连接到电路图案33上的Ni/Au薄膜37上以便在相应的安装区域利用底层填料42将裸露芯片40机械式固定在包覆层36上的过程中，防止底层填料42从FPC 38中的裸露芯片40的安装区域散布到外围部件。由此，无需类似于常规技术那样设置一个隆起或者沟槽来防止溶液流出，并且能够使得部件之间的间距变窄。因此，能够获得一种其中裸露芯片40和类似元件被以高密度安装起来的模块衬底。
还有，在其中有源元件(比如裸露芯片)40被安装在FPC 38中的模块衬底内，能够防止由固化树脂作为其主要成分制成并且具有坚硬特性的底层填料42从裸露芯片40的安装区域散布到位于其周围的包覆层36。因此，可以防止碎屑的产生，如果有的话，所述碎屑是当线路板在接近裸露芯片40的安装区域的部分发生弯曲时由于底层填料的散布部分发生剥落而造成的。由此，对于盘设备来说，能够避免装载在设备中的介质遭受不利影响。
还有，在一个至少与裸露芯片40相对的位置处，在柔性绝缘衬底31的下表面上设置有衬板34。利用这种结构，可以抑止绝缘衬底31上安装有裸露芯片40的部分的柔性，并且由此能够将裸露芯片40正确地固定在FPC 38上。
需要指出的是，在第二实施例中的FPC制造过程内，替代性地，能够使用一种铜箔聚酰亚胺作为初始材料。
(第三实施例)
图5是一个示意性透视图，示出了一个按照本发明第三实施例用作盘设备的硬盘驱动器(在下文中被称作HDD)，而图6是一个示意性透视图，示出了一个在图5中示出的柔性模块衬底。
如图5中所示，HDD包括一个壳体61，该壳体61呈一个上表面敞口的长方形盒状，和一个顶盖，用以打开/关闭壳体61的敞口上端部，该顶盖利用大量的螺钉固定在壳体上。
壳体61包含有两个用作记录介质的磁盘62a和62b，一个用作驱动元件用于支撑和旋转这些磁盘的主轴马达63，大量在磁盘上记录数据或者从磁盘上读取数据的磁头，一个支撑这些磁头以便能够相对于磁盘62a和62b移动的磁头致动器(head actuator)64，一个旋转式移动和定位磁头致动器的音圈马达(在下文中被称作VCM)，一个当磁头移动至磁盘最外周时将相应磁头保持在一个远离相应磁盘的位置处的滑道装载机构66，以及一个其中安装有诸如前置放大器、裸露芯片以及类似元件这样的电子部件的柔性模块衬底67。
还有，利用螺钉将一个印刷线路板(未示出)固定在壳体61的外表面上，以便位于一个与壳体61的底壁相对的位置处，其中所述印刷线路板经由柔性模块衬底67对主轴马达63、VCM 65以及磁头的工作过程进行控制。
两个磁盘62a和62b均被装配在主轴马达63的轴芯(未示出)上，以便相互同轴，并且还利用一个夹持弹簧68将它们夹持起来，以便在它们之间利用预定的间距沿着轴芯的轴向叠置起来。磁盘62a和62b在主轴马达63的作用下以预定的速度进行旋转。
磁头致动器64包括一个固定在壳体61的底壁上的轴承组件69。还有，磁头致动器64包括大量的，例如四根安装于轴承组件68的轴芯(未示出)上的臂70，均支撑在一个从各根臂70延伸出来的悬架(未示出)的延展端部处的磁头71，以及三个隔离环(未示出)。
另一方面，磁头致动器64上的各个磁头71均经由相应的柔性印刷线路板(未示出)电连接在一个FM单元67中的主柔性印刷线路板上，所述主柔性印刷线路板将在后面予以描述。
如图5和6中所示，柔性模块衬底67包括一个具有柔性印刷线路板的底座72，其中所述柔性印刷线路板被弯曲成基本上长方形；和一个带状柔性印刷线路板73，其中该柔性印刷线路板73从底座中的柔性印刷线路板发生弯曲和延伸，以便被连接在磁头致动器64上。由此，被制成共用柔性印刷线路板中的一个整体式构件。
底座72的结构基本上类似于图3中所示前述第二实施例中的柔性模块衬底。更具体地说，柔性印刷线路板74包括一个例如由聚酰亚胺制成并且在一个区域处具有开口的柔性绝缘衬底，一个形成于柔性绝缘衬底上并且具有一种例如由Cr/Cu和Cu形成的分层结构的电路图案，一个例如由SUS制成形成于柔性绝缘衬底的下表面(至少一个对应于有源元件的区域，所述有源元件将在后面予以描述)上的衬板，一个例如由Ni制成并且覆盖住电路图案33的外露表面部分的薄膜，一个例如由聚酰亚胺制成用作保护膜并且形成于柔性绝缘衬底31上除所述开口之外的部分上的包覆层，以及一个形成于电路图案的包覆层上安装有有源元件的各个开口部分处的Ni/Au薄膜。在所述安装区域的附近，在包覆层的表面上形成有一个氟树脂层。一个有源元件(例如磁头放大器)75在相应的安装区域中被连接在从包覆层中显露出来的电路图案上，并且利用一种底层填料机械式固定在所述包覆层上。还有，一个接插件76、芯片电阻器77以及芯片电容器78被安装在柔性印刷线路板74上。需要注意的是，在柔性印刷线路板74上安装有磁头放大器75和类似元件的另一侧以这样一种方式设置一个例如由SUS制成的衬板，即该衬板与磁头放大器75和接插件77对置。底座72被固定在壳体61的底壁上。从底座延伸出来的带状柔性印刷线路板73的延展端部形成了一个连接端部79。该连接端部79被安装在磁头致动器64的近端侧。
具有前述结构的HDD具有下述优点。也就是说，在具有这种结构的柔性模块衬底67中的底座内，氟树脂在安装区域的附近被涂敷在包覆层部分的表面上，用以防止底层填料散布到周围部分，其中在所述结构中有源元件(例如磁头放大器)75被安装在从柔性印刷线路板74的包覆层(保护膜)中显露出来的电路图案上，并且磁头放大器75利用底层填料机械式固定在所述包覆层上。以这种方式，磁头放大器75和类似元件的安装密度可以提高。
还有，在底座中，防止了由固化树脂作为其主要成分制成并且具有坚硬特性的底层填料散布到周围部分(包括有带状柔性印刷线路板73上的弯曲部分，其中带状柔性印刷线路板73被从底座72连接在磁头致动器64上)。以这种方式，底层填料不会存在于所述弯曲部分处。因此，可以抑止底层填料发生剥落的可能性。因此，带状柔性印刷线路板73可以在不产生碎屑的条件下顺畅地从底座72发生弯曲，其中所述碎屑是由于底层填料发生剥落而造成的。
因此，能够获得一种包括柔性模块衬底67的HDD，其中柔性模块衬底67包括可以以高密度安装部件并且具有高可靠性的底座72。
对于本技术领域中那些熟练人员来说，将会轻易地发现其它优点和修改。因此，本发明在其较宽意义上来说并不局限于在这里图示和描述的具体细节和代表性实施例。因此，在不脱离由所附权利要求以及它们的等效描述所限定的总体发明构思的精神实质或者保护范围的条件下，可以进行各种修改。

Claims (16)

1.一种模块衬底，其特征在于包括：
绝缘衬底(1)；
电路图案(2)，至少形成于绝缘衬底(1)的主表面上；
保护膜(7)，形成于包括有电路图案(2)的绝缘衬底(1)的主表面上，以便显露出电路图案(2)中的安装区域；
有源元件(11)，安装于所述电路图案中的安装区域上；
氟树脂膜(10)，至少在有源元件(11)的安装区域附近形成于保护膜(7)上，以及
底层填料(14)，填充在有源元件(11)与电路图案(2)中的安装区域之间。
2.按照权利要求1的模块衬底，其特征在于，绝缘衬底(1)是一种由热固性树脂作为其主要成分制成的刚性绝缘衬底。
3.按照权利要求1的模块衬底，其特征在于，电路图案(2，3)被分别形成在绝缘衬底(1)的主表面上和与该主表面相对的表面上。
4.按照权利要求1的模块衬底，其特征在于，绝缘衬底(31)是一种柔性绝缘衬底。
5.按照权利要求4的模块衬底，其特征在于，在绝缘衬底(31)的与电路图案(33)相对的表面上还设置有一个衬板(34)，以便面对着有源元件(44)。
6.按照权利要求1的模块衬底，其特征在于，保护膜(7)是一个阻焊剂膜。
7.按照权利要求1的模块衬底，其特征在于，有源元件(11)是一个裸露芯片。
8.按照权利要求1的模块衬底，其特征在于，氟树脂膜(10)具有5至50微米的厚度。
9.按照权利要求1的模块衬底，其特征在于，底层填料(14)由一种包含有填料的环氧树脂制成。
10.按照权利要求1的模块衬底，其特征在于，在所述电路图案上还安装有无源元件(15)。
11.一种盘设备，其特征在于包括：
盘状记录介质(62a)；
驱动构件(63)，支撑和旋转记录介质(62a)；
磁头(71)，在记录介质(62a)上进行数据处理；
磁头致动器(64)，支撑着磁头(71)并且相对于记录介质(62a)移动磁头(71)；以及
柔性模块衬底(67)，包含有一个包括柔性印刷线路板(74)的底座(72)，和一个带状柔性印刷线路板，该带状柔性印刷线路板从底座(72)中的柔性印刷线路板发生弯曲和延伸，并且被连接在磁头致动器(64)上；
其中，柔性模块衬底(67)中的底座(72)包括：绝缘衬底；至少形成于绝缘衬底的主表面上的电路图案；形成于包括有电路图案的绝缘衬底主表面上的保护膜，以便显露出所述线路图案中的安装区域；安装于电路图案中的安装区域上的有源元件；至少在有源元件的安装区域附近形成于保护膜上的氟树脂膜；以及填充在有源元件与电路图案中的安装区域之间的底层填料。
12.按照权利要求11的盘设备，其特征在于，所述底座中的有源元件(75)是一个裸露芯片。
13.按照权利要求11的盘设备，其特征在于，底座(72)中的氟树脂膜具有5至50微米的厚度。
14.按照权利要求1的盘设备，其特征在于，底座(72)中的底层填料由一种包含有填料的环氧树脂制成。
15.按照权利要求11的盘设备，其特征在于，在底座(72)中的电路图案上还安装有无源元件(77)。
16.按照权利要求11的盘设备，其特征在于，在所述柔性绝缘衬底的与底座(72)中的电路图案相对的表面上还设置有一个衬板，以便面对着有源元件(75)。
CNA2005101253658A 2004-11-16 2005-11-16 模块衬底和盘设备 Pending CN1802071A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004331979 2004-11-16
JP2004331979A JP4843214B2 (ja) 2004-11-16 2004-11-16 モジュール基板およびディスク装置

Publications (1)

Publication Number Publication Date
CN1802071A true CN1802071A (zh) 2006-07-12

Family

ID=36385411

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2005101253658A Pending CN1802071A (zh) 2004-11-16 2005-11-16 模块衬底和盘设备

Country Status (3)

Country Link
US (1) US7327040B2 (zh)
JP (1) JP4843214B2 (zh)
CN (1) CN1802071A (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102150480A (zh) * 2008-08-18 2011-08-10 赛姆布兰特环球有限公司 卤代烃聚合物涂层
CN103140020A (zh) * 2011-12-05 2013-06-05 昆山雅森电子材料科技有限公司 挠性印刷电路板的覆盖膜、挠性印刷电路板结构及其制法
CN103140018A (zh) * 2011-12-05 2013-06-05 昆山雅森电子材料科技有限公司 软性印刷电路板的保护膜、软性印刷电路板结构及其制法
CN103140019A (zh) * 2011-12-05 2013-06-05 昆山雅森电子材料科技有限公司 软性电路板的黑色覆盖膜、软性印刷电路板结构及其制法

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2007180A4 (en) * 2006-03-14 2011-03-23 Sharp Kk PCB, ELECTRONIC CIRCUIT ARRANGEMENT AND DISPLAY
DE102006022748B4 (de) * 2006-05-12 2019-01-17 Infineon Technologies Ag Halbleiterbauteil mit oberflächenmontierbaren Bauelementen und Verfahren zu seiner Herstellung
GB0703172D0 (en) 2007-02-19 2007-03-28 Pa Knowledge Ltd Printed circuit boards
JP4986738B2 (ja) * 2007-06-27 2012-07-25 新光電気工業株式会社 半導体パッケージおよびこれを用いた半導体装置
JP5098498B2 (ja) * 2007-08-06 2012-12-12 株式会社デンソー 電子装置
US8492263B2 (en) 2007-11-16 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Protected solder ball joints in wafer level chip-scale packaging
US7872483B2 (en) 2007-12-12 2011-01-18 Samsung Electronics Co., Ltd. Circuit board having bypass pad
US8217514B2 (en) * 2008-04-07 2012-07-10 Stats Chippac Ltd. Integrated circuit packaging system with warpage control system and method of manufacture thereof
US8618420B2 (en) * 2008-08-18 2013-12-31 Semblant Global Limited Apparatus with a wire bond and method of forming the same
US8299616B2 (en) * 2010-01-29 2012-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. T-shaped post for semiconductor devices
US8803319B2 (en) 2010-02-11 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
US8318596B2 (en) * 2010-02-11 2012-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
US8995146B2 (en) 2010-02-23 2015-03-31 Semblant Limited Electrical assembly and method
US8241963B2 (en) 2010-07-13 2012-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Recessed pillar structure
GB2485419B (en) * 2010-11-15 2015-02-25 Semblant Ltd Method for reducing creep corrosion
US9230932B2 (en) 2012-02-09 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect crack arrestor structure and methods
US9515036B2 (en) 2012-04-20 2016-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for solder connections
JP2014072372A (ja) * 2012-09-28 2014-04-21 Ibiden Co Ltd プリント配線板の製造方法及びプリント配線板
KR20140084801A (ko) * 2012-12-27 2014-07-07 삼성전기주식회사 인쇄회로기판 및 인쇄회로기판 제조 방법
TWI556366B (zh) * 2014-05-26 2016-11-01 南茂科技股份有限公司 薄膜覆晶封裝結構及其可撓性線路載板
JP2016219574A (ja) * 2015-05-19 2016-12-22 株式会社リコー フレキシブルプリント配線板およびフレキシブルプリント配線板の製造方法
GB201621177D0 (en) 2016-12-13 2017-01-25 Semblant Ltd Protective coating
US11259406B2 (en) * 2018-11-21 2022-02-22 Synaptics Incorporated Flexible connector for a display device
US10886648B2 (en) * 2018-11-26 2021-01-05 Canon Kabushiki Kaisha Communication module, electronic device, and image pickup apparatus
JP2020107692A (ja) * 2018-12-27 2020-07-09 トヨタ自動車株式会社 プリント配線回路基板の製造方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2678958B2 (ja) * 1992-03-02 1997-11-19 カシオ計算機株式会社 フィルム配線基板およびその製造方法
JPH06326445A (ja) 1993-05-10 1994-11-25 Noriyuki Yoshida 回路基板のソルダーレジスト製造方法
JPH0722741A (ja) * 1993-07-01 1995-01-24 Japan Gore Tex Inc カバーレイフィルム及びカバーレイフィルム被覆回路基板
US6639155B1 (en) * 1997-06-11 2003-10-28 International Business Machines Corporation High performance packaging platform and method of making same
JP3367886B2 (ja) * 1998-01-20 2003-01-20 株式会社村田製作所 電子回路装置
US6297564B1 (en) * 1998-04-24 2001-10-02 Amerasia International Technology, Inc. Electronic devices employing adhesive interconnections including plated particles
JP2000058709A (ja) * 1998-08-17 2000-02-25 Nec Corp 突起電極構造および突起電極形成方法
JP2001102700A (ja) 1999-07-27 2001-04-13 Sanyo Electric Co Ltd フレキシブルプリント基板及びフレキシブルプリント基板を有する携帯電話端末
JP4044267B2 (ja) * 2000-06-02 2008-02-06 株式会社東芝 磁気ディスク装置
US6291264B1 (en) * 2000-07-31 2001-09-18 Siliconware Precision Industries Co., Ltd. Flip-chip package structure and method of fabricating the same
JP2003100957A (ja) * 2001-09-26 2003-04-04 Nec Corp 半導体パッケージ
TW543923U (en) * 2002-10-25 2003-07-21 Via Tech Inc Structure of chip package
JP2004179578A (ja) * 2002-11-29 2004-06-24 Ngk Spark Plug Co Ltd 配線基板及びその製造方法
US7070207B2 (en) * 2003-04-22 2006-07-04 Ibiden Co., Ltd. Substrate for mounting IC chip, multilayerd printed circuit board, and device for optical communication
US20050028361A1 (en) * 2003-08-07 2005-02-10 Indium Corporation Of America Integrated underfill process for bumped chip assembly
WO2005020215A1 (en) * 2003-08-21 2005-03-03 Sae Magnetics (H. K.) Ltd. Electrical connection and component assembly for constitution of a hard disk drive
US7061085B2 (en) * 2003-09-19 2006-06-13 Micron Technology, Inc. Semiconductor component and system having stiffener and circuit decal

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102150480A (zh) * 2008-08-18 2011-08-10 赛姆布兰特环球有限公司 卤代烃聚合物涂层
CN105744750A (zh) * 2008-08-18 2016-07-06 赛姆布兰特有限公司 卤代烃聚合物涂层
CN105744750B (zh) * 2008-08-18 2019-06-18 赛姆布兰特有限公司 卤代烃聚合物涂层
CN103140020A (zh) * 2011-12-05 2013-06-05 昆山雅森电子材料科技有限公司 挠性印刷电路板的覆盖膜、挠性印刷电路板结构及其制法
CN103140018A (zh) * 2011-12-05 2013-06-05 昆山雅森电子材料科技有限公司 软性印刷电路板的保护膜、软性印刷电路板结构及其制法
CN103140019A (zh) * 2011-12-05 2013-06-05 昆山雅森电子材料科技有限公司 软性电路板的黑色覆盖膜、软性印刷电路板结构及其制法
CN103140018B (zh) * 2011-12-05 2016-06-08 昆山雅森电子材料科技有限公司 软性印刷电路板的保护膜、软性印刷电路板结构及其制法
CN103140020B (zh) * 2011-12-05 2016-06-08 昆山雅森电子材料科技有限公司 挠性印刷电路板的覆盖膜、挠性印刷电路板结构及其制法

Also Published As

Publication number Publication date
US7327040B2 (en) 2008-02-05
US20060103030A1 (en) 2006-05-18
JP4843214B2 (ja) 2011-12-21
JP2006147652A (ja) 2006-06-08

Similar Documents

Publication Publication Date Title
CN1802071A (zh) 模块衬底和盘设备
TWI527848B (zh) 非隨機異方性導電膠膜及其製程
CN2712046Y (zh) 多层布线板以及用于该布线板的基板材料
CN100426492C (zh) 微电子封装件及其制造方法
EP1651021B1 (en) Suspension board with circuit
CN1728921A (zh) 配线板和磁盘装置
US20080006942A1 (en) Bottom substrate of package on package and manufacturing method thereof
CN1571626A (zh) 印刷电路板的焊盘及其形成方法
CN1511342A (zh) 用于微电子封装制造的分配工艺
US7554131B2 (en) Chip embedded package structure and fabrication method thereof
US20120111607A1 (en) Circuit board with high-density circuit patterns
CN1206936A (zh) 半导体器件及其制造方法
JP5363417B2 (ja) 密集したアレイとフレックス回路との相互接続
US5929522A (en) Semiconductor non-laminate package and method
KR100997576B1 (ko) 반도체 소자 테스트용 콘택터
JP2014501451A (ja) 印刷回路基板及びその製造方法
US20180218970A1 (en) Method for forming solder bumps using sacrificial layer
CN1993021A (zh) 用于制造配线基板的方法
US7135377B1 (en) Semiconductor package substrate with embedded resistors and method for fabricating same
KR100772454B1 (ko) 이방성 도전 필름 및 그 제조방법
US6188546B1 (en) Method of electrically connecting a magnetic head, a magnetic head body and a magnetic disc apparatus
US20070187842A1 (en) Printed circuit, method of manufacturing the printed circuit, printed circuit/electronic element assembly, and method of manufacturing the printed circuit/electronic element assembly
CN2681524Y (zh) 线路载板
KR101776305B1 (ko) 인쇄회로기판 및 그의 제조 방법
CN1462172A (zh) 具固定防焊层的印刷电路板

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
AD01 Patent right deemed abandoned

Effective date of abandoning: 20060712

C20 Patent right or utility model deemed to be abandoned or is abandoned