CN1511342A - 用于微电子封装制造的分配工艺 - Google Patents

用于微电子封装制造的分配工艺 Download PDF

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CN1511342A
CN1511342A CNA028072049A CN02807204A CN1511342A CN 1511342 A CN1511342 A CN 1511342A CN A028072049 A CNA028072049 A CN A028072049A CN 02807204 A CN02807204 A CN 02807204A CN 1511342 A CN1511342 A CN 1511342A
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CN1255867C (zh
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S·N·托勒
J·S·库恩德特
Լ��ѷ
K·T·约翰逊
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Abstract

一种微电子封装,包括设置在微电子封装核心的开口内的至少一个微电子管芯,其中通过处于开口内未被微电子管芯占据的部分中的分配针来注射液体密封材料。密封材料随后固化。那么在微电子管芯、密封材料和微电子封装核心上制造介质材料和导电迹线的互连层,以形成微电子封装。

Description

用于微电子封装制造的分配工艺
                     发明背景
发明领域
本发明涉及用于微电子封装制造的工艺。特别是,本发明涉及一种将至少一个微电子管芯密封在微电子封装核心内以形成一个微电子封装的分配工艺。
背景技术
集成电路元件的高性能、低成本和更高的微型化,以及集成电路的更大封装密度是计算机行业的当前目标。由于要实现这些目标,微电子管芯变得更小。当然,更大封装密度的目标要求整个微电子管芯封装等于或只稍大于(约10%到30%)微电子管芯自身的尺寸。这种微电子管芯封装称为“芯片级封装”或“CSP”。
如图22所示,精确CSP(true CSP)包括在微电子管芯202的有效面204上直接制造组合层。组合层可包括设在微电子管芯的有效面204上的介质层206。可在介质层206上形成导电迹线208,其中各导电迹线208的一部分与有效面204上的至少一个触点212接触。可制出外触点如用于与外部元件(未示出)接触的焊球或导电引脚,以与至少一条导电迹线208电接触。图22显示了焊球214形式的外触点,其被介质层206上的阻焊掩膜材料216所包围。然而在这种精确的CSP中,由微电子管芯的有效面204所提供的表面区域通常无法为需要与用于某些类型的微电子管芯(如逻辑部件)的外部元件(未示出)接触的所有外触点提供足够的表面。
可通过使用插入件如衬底(基本上为刚性的材料)或柔性元件(基本上为柔性的材料)来提供附加的表面区域。图23显示了具有微电子管芯224的衬底插入件222,管芯224通过小焊球228与衬底插入件222的第一表面226相连并与之电接触。小焊球228在微电子管芯224上的触点232和衬底插入件的第一表面226上的导电迹线234之间延伸。导电迹线234通过在衬底插入件222中延伸的通孔242而与衬底插入件222的第二表面238上的焊接区236形成不连续的电接触。外触点244(显示为焊球)形成于焊接区236之上。外触点244用于实现微电子管芯224和外部电系统(未示出)之间的电连接。
使用衬底插入件222需要许多加工工序。这些加工工序增加了封装的成本。另外,即使使用小焊球228,也存在会导致小焊球228之间发生短路的拥挤问题,并在微电子管芯224和衬底插入件222之间插入底层填料以防止污染和提供机械稳定性方面存在着困难。此外,当前的衬底因衬底插入件222的厚度原因而无法满足未来的微电子管芯224的功率传输要求,这会导致焊接区一侧的电容器具有过高的电感。
图24显示了一种柔性元件插入件252,其中微电子管芯256的有效面254通过粘结层262而与柔性元件插入件252的第一表面258相连。微电子管芯256被密封在密封材料264中。采用激光烧蚀在柔性元件插入件252中形成开口,其穿过柔性元件插入件252到达微电子管芯的有效面254上的触点266处和设在柔性元件插入件252内的选出的金属垫片268处。在柔性元件插入件252的第二表面272上和开口中形成了导电材料层。通过标准的光掩膜/蚀刻工艺使导电材料层形成图案,从而形成导电通孔274和导电迹线276。外触点形成于导电迹线276上(其显示为由邻近导电迹线276的阻焊掩膜材料282所包围的焊球278)。
使用柔性元件插入件252需要可形成柔性元件插入件252的胶合材料层,并要求将柔性元件插入件252胶粘到微电子管芯256上。这些胶粘工艺比较困难,而且会增加封装的成本。此外,已经发现这样得到的封装的可靠性较差。
因此,开发一种克服了上述问题的用于CSP应用的可提供另外的表面区域以形成迹线的新型装置和技术是有利的。
                      附图说明
尽管说明书总结了特别指明并清楚提出了本发明要求的权利要求,然而在结合附图来阅读时可从本发明的下述介绍中更容易地确定本发明的优点,在附图中:
图1是根据本发明的微电子封装核心的斜视图;
图2a和2b是根据本发明的具有备选的微电子封装核心开口的微电子封装核心的顶平面视图;
图3是微电子封装核心的侧剖视图,其具有与其第一表面相连并跨过微电子封装核心开口的第一保护膜以及与其第二表面相连的背面保护膜;
图4是设于微电子封装核心开口内的微电子管芯的侧剖视图,其中微电子管芯也与第一保护膜邻接;
图5是图4所示组件的侧剖视图,其具有处于微电子封装核心开口内的颗粒化的密封材料;
图6是处于压板之间的图5所示组件的侧剖视图;
图7是在由压板进行压缩之后的图6所示组件的侧剖视图;
图8是在密封材料被磨削后的图7所示组件的侧剖视图;
图9是图8所示的区域9的侧剖视图,显示了微电子管芯和微电子封装核心的角部附近的空隙;
图10是根据本发明的微电子封装核心的侧剖视图,其具有与其第一表面相连并跨过封装核心开口的第一保护膜;
图11是根据本发明的设于微电子封装核心开口内的微电子管芯的侧剖视图,其中微电子管芯也与第一保护膜邻接;
图12是根据本发明的插入到微电子封装核心开口中的分配针的侧剖视图;
图13是根据本发明的在用密封材料填充了微电子封装核心开口之后的分配针的侧剖视图;
图14是根据本发明的密封后的组件的侧剖视图;
图15和16是显示了根据本发明的分配密封材料的真空辅助工艺的侧剖视图;
图17是显示了根据本发明的用于提高密封材料的平面度的技术的侧剖视图;
图18是根据本发明的图14或图17所示组件的侧剖视图,其已被翻转过来并除去了第一保护膜和第二保护膜(如果存在的话);
图19是根据本发明的微电子管芯的侧剖视图,其具有形成于其有效面上的互连层;
图20是图16的侧剖视图,其中根据本发明的互连层具有与之相连的外部互连构件;
图21是根据本发明的单个微电子封装的侧剖视图;
图22是本领域中已知的微电子器件的精确CSP的剖视图;
图23是本领域中已知的采用衬底插入件的微电子器件的CSP的剖视图;和
图24是本领域中已知的采用柔性元件插入件技术的微电子器件的CSP的剖视图。
                  所示实施例的详细描述
在下面的详细介绍中将参考附图,附图通过图例显示了可实施本发明的具体实施例。这些实施例以足够详细的方式进行了介绍,以便本领域的技术人员可实施本发明。另外,应当理解,在不脱离本发明的精神和范围的前提下,所公开的各实施例中的各元件的位置或设置可进行修改。因此,下述详细介绍不具有限制意义,本发明的范围只由适当解释的所附权利要求及其等效物的整个范围来限定。在附图中,相似的标号在所有的视图中均表示相同或相似的功能性。
本发明包括微电子管芯制造技术,其可将至少一个微电子管芯放入微电子封装核心或其它微电子封装衬底的至少一个开口中,并用液体密封材料将微电子管芯固定在开口内,此液体密封材料由针来分配。液体密封材料随后固化。然后在微电子管芯、密封材料和微电子封装核心上制造介质材料和导电迹线的互连层,从而形成微电子管芯。
图1显示了用于制造微电子封装的微电子封装核心102。微电子封装核心102最好包括基本上平面的材料。用于制造微电子封装核心102的材料可包括但不限于双马来酰亚胺三嗪(BT)树脂基层压材料、FR4层压材料(一种阻燃玻璃/环氧树脂材料)、各种聚酰亚胺层压材料、其它聚合物和聚合物复合材料、陶瓷材料等,以及金属材料(如铜)等。
微电子封装核心102具有至少一个开口104,其从微电子封装核心102的第一表面106延伸出并通到微电子封装核心102的相对的第二表面108。如图2a所示,开口104可以为任何形状和尺寸,包括但不限于矩形/方形104a、带有圆角的矩形/方形104b和圆形104c。在如图2b所示的另一实施例中,开口104可具有从开口104中延伸出的通道105,以允许在真空辅助分配工艺中将针放置到较远处(如下所介绍)。在一个优选实施例中,通道105以与开口104相似的方式延伸穿过微电子封装核心102的厚度。这种设置对获得经开口104的液体分配材料的最佳流动来说是有利的,并且如果存在与针位置相关的任何缺陷,那么这种缺陷将位于对最终微电子封装的损害较小的位置处。对开口104的大小和形状的唯一限制是,它们必须具有适当的大小和形状以在其中容纳相应的微电子管芯,这将在下文中讨论。
图3-9显示了用于制造微电子器件的压缩模制方法。图3显示了贴在微电子封装核心的第一表面106的至少一部分上的至少一个第一保护膜110,使得第一保护膜110跨置在微电子封装核心开口104上。背面保护膜112紧贴在微电子封装核心的第二表面108的至少一部分上,并靠近微电子封装核心开口104(但不跨置于其上)。第一保护膜110和背面保护膜112最好是基本上柔性的材料,例如Kapton聚酰亚胺薄膜(美国特拉华州Wilmington的E.I.du Pont deNemours and Company),但其也可由任何合适的材料制成,包括金属膜。在一个优选实施例中,第一保护膜110和背面保护膜112可具有与微电子封装核心102基本上相同的热膨胀系数(CTE)。
图4显示了微电子管芯114,各管芯均具有处于微电子封装核心102的相应开口104内的有效面116和背面118。微电子管芯114可以是任何有源或无源的微电子器件,包括但不限于逻辑部件(CPU)、存储器(DRAM,SRAM,SDRAM等)、控制器(芯片组)、电容器、电阻器、电感器等。
微电子封装核心102的厚度117与微电子管芯114的厚度115最好基本上相等。微电子管芯114均放置成使得它们的有效面116贴在第一保护膜110上。第一保护膜110可具有粘合剂,例如硅树脂或丙烯酸树脂,其粘附在微电子封装核心的第一表面106和微电子管芯的有效面116上。背面保护膜112也可具有粘合剂,其粘附在微电子封装核心的第二表面108上。
如图5所示,在开口104内未被微电子管芯114占据的部分(见图4)中放置了颗粒化密封材料122,例如塑料、树脂、环氧树脂、弹性体(如橡胶)材料等。如图6所示,使第一压板124与第一保护膜110相接触,并使第二压板126与颗粒化密封材料122相接触。为了促进将材料从板124和/或126上释放出来,可在板124和/或126上设置由化学惰性材料如聚四氟乙烯(PTFE)制成的保护膜。在包括颗粒化密封材料122在内的微电子封装核心102上施加约400磅/平方英寸的负载(由箭头128表示),就可使颗粒化密封材料122熔化并形成固体形式的密封材料132(见图7)。密封材料132将微电子管芯114固定在微电子封装核心102内,为所得结构提供了机械刚度,并为后续构建迹线层提供了表面区域。
在压缩工艺中,一部分密封材料132流到背面保护膜112上(如圆圈134所示),并可覆盖微电子管芯的背面118,如图7所示(第一压板124和第二压板126已被移开)。采用背面保护膜112来帮助去除过度模制部分(overmolding)。然而,此过度模制部分需要进行磨削,以得到具有密封材料132的平表面的板136,此平表面与微电子管芯的背面118和微电子封装核心的第二表面108基本上平齐,如图8所示(第一保护膜110和背面保护膜112已被去除)。
此外,如图9所示(其为图8中的区域9的放大视图),压缩模制工艺会在微电子管芯114和/或微电子封装核心102的角部附近产生空隙138。这些空隙138会在后续加工工序中带来问题。与压缩模制有关的其它潜在问题包括:板136的扭曲;微电子管芯114可在第一保护膜110上移动,这使得在组合层中产生了与微电子管芯-管芯的图案对齐有关的问题(将在下文中讨论);压缩可能会使微电子管芯114产生裂纹;压缩模制工艺在形成较大组件方面较困难;以及需要细粒的密封材料122来实现均匀的模制,这可能会损害呼吸方面的健康,并且无法在净室中进行操作。
如图10-18所示,本发明涉及一种用于替代上述压缩模制技术的分配工艺。如图10所示,微电子封装核心102具有至少一个第一保护膜110,其贴在微电子封装核心的第一表面106的至少一部分上,使得第一保护膜110跨置在微电子封装核心开口104上。如图11所示,将均具有有效面116和背面118的微电子管芯114放入到微电子封装核心102的相应开口104中,使得微电子管芯的有效面116贴在第一保护膜110上。
如图12和13所示,采用分配工具如分配针142来将液体密封材料144注射到开口104内未被微电子管芯114占据的部分内(见图10)。分配针142可以是本领域中已知的用于在封装和BGA倒装片之间注射底层填料的那种类型。密封材料可包括但不限于塑料、树脂、环氧树脂、弹性体(即橡胶)材料等。然而应当理解,密封材料144应当具有与微电子管芯114和微电子封装核心102的良好粘结,如果可能的话应当具有与微电子管芯114和微电子封装核心102相似的热膨胀系数,应当具有足够的顺应性和其它机械性能以调节微电子封装核心102和微电子管芯114之间的固有性质的任何不匹配,并且应具有足够的流动性和其它分配性能,使得可适于用分配针142来分配。具有这种性能的液体密封材料144可包括但不限于Shin-Etsu 122X硅石填充的环氧树脂(可从日本Shin-Etsu Chemical Co.,Ltd.公司得到)和Dow Corning DC6812硅树脂(可从美国密执安州Midland的Dow Corning公司得到)。
组件然后在一定温度下固化,并持续一段足以使液体密封材料144进入固态或基本上固态的时间。如图14所示,密封材料144的第一表面148与微电子封装核心的第二表面108基本上成一平面。因此,不需要进行任何平面化(即磨削)加工,使得互连层可直接形成在组件150上。
在另一实施例中,可将分配针142插入到微电子封装核心102和微电子管芯114之间的微电子封装核心开口104中并靠近第一保护膜110。在注射液体密封材料144时,将分配针142从封装核心开口104中抽出。当封装核心开口被填满时,液体密封材料144的注射结束,如图13所示。当然应当理解,在注射密封材料144时,分配针142可在封装核心开口104内四处移动,以便使密封材料144均匀地分布。
在如图15所示的另一实施例中,微电子封装核心102和微电子管芯114之间的微电子封装核心开口104被第一保护膜110和第二保护膜111所密封,保护膜跨置在微电子封装核心开口104上,并邻近微电子管芯的背面118和微电子封装核心的第二表面108。将第一针113和第二针115插入到第二保护膜111中。由第一针113形成了至少部分真空,而密封材料144由第二针115来注射。第一针113和第二针115可插入到第二保护膜111的工艺孔中,或只是插入到第二保护膜111中。如图16所示,在填充了微电子封装核心开口之后将第一针113和第二针115抽出。已经发现,此真空辅助工艺可得到较少的空隙、较少的过度模制部分,允许密封材料具有较大范围的流变性质,并允许微电子管芯和微电子封装核心的可能的几何形状具有更大的范围。
回来看图2b,在另一实施例中,在真空辅助工艺中可利用通道105。可将第一针113(图14)插入到一个通道105中,而将第二针115插入到另一通道105中。在真空辅助工艺中优选使用如图2b所示的通道105从相对的角部延伸出来的通道设置,这是因为它可防止形成零净流量的区域。在一股射流分成沿基本上相反方向流动的两股、然后大致迎面再次汇合时可能会形成这些区域。这种零净流量的区域可能会形成空隙。另外,如果在针113和115的插入位置处存在任何缺陷(例如外形差异),封装的第一层中的迹线可能会围绕这些位置布置。如果通道105从开口104的角部而不是从其侧面延伸出,那么这种布置较简单,并对其它封装设计的限制较少。
组件然后在一定温度下固化,并持续一段足以使液体密封材料144进入固态或基本上固态的时间。如图14所示,密封材料144的第一表面148与微电子封装核心的第二表面108基本上成一平面。因此,不需要进行任何平面化(即磨削)加工,使得互连层可直接形成在组件150上。然而,如果需要的话,通过将组件放在两块板之间,并通过施加压力来使微电子封装核心的第一表面106和微电子管芯的有效面116压在硬面板151(即抛光钢板)上,并且使微电子封装核心的第二表面108和微电子管芯的背面116压在软面板153(例如具有硅橡胶表面155)上,如图17所示,就可进一步提高密封材料的正面148的平面度。这种包括施加压力的固化工艺具有可潜在地提高固化密封材料144的断裂韧度的优点。通过适当地优化分配工艺,就可以防止管芯的背面被密封材料污染。
在密封材料144固化后,如图18所示,将组件150倒转并除去第一保护膜110和第二保护膜111(如果有的话),以暴露出微电子管芯的有效面116和微电子管芯的背面118。同样如图18所示,密封材料144形成了至少一个第二表面152,其与微电子管芯的有效面116和微电子封装核心的第一表面106基本上形成一平面。在其它制造工序中可利用密封材料的第二表面152与微电子封装核心的第一表面106来作为用于形成互连层的额外表面区域,互连层例如为介质材料层和导电迹线。
虽然下述介绍涉及用于形成互连层的无突出块(bumpless)的组合层技术,然而这种制造方法并不限于此。互连层可由本领域中已知的多种技术来制造。
图19显示了位于微电子封装核心102内的一个微电子管芯114以及位于微电子管芯114和微电子封装核心102之间的密封材料144的视图。当然,微电子管芯114包括多个位于微电子管芯的有效面116上的电触点154。电触点154与微电子管芯114内的电路(未示出)电连接。为简单和清楚起见,图中只显示了四个电触点154。
如图19所示,在微电子管芯的有效面116(包括电触点154)、微电子封装核心的第一表面106和密封材料的第二表面152上分别层叠了介质层156,156’和导电迹线158,158’。介质层156,156’优选为环氧树脂、聚酰亚胺、双苯并环丁烯等,最好填充有环氧树脂,其可从美国新泽西州Paramus的Ajinomoto USA公司中得到。导电迹线158,158’可以是任何导电材料,包括但不限于铜、铝及其合金。
可通过任何已知的工艺来形成第一介质层156,156’,包括但不限于层压、旋涂、辊涂和喷射沉积。导电迹线158,158’可延伸穿过它们各自的介质层156,156’以相互间形成电接触,或者通过电触点154形成电接触。这可通过本领域中已知的任何方法来在介质层156,156’上形成通孔来实现,这些方法包括但不限于激光打孔和光刻术(之后通常还进行蚀刻),或者以与光刻工艺中的抗蚀膜暴露类似的方式来通过掩膜暴露光敏介质材料,这是本领域的技术人员所显而易见的。导电迹线158,158’可由任何已知的技术来形成,包括但不限于半添加电镀(semi-additive plating)和光刻技术。
如图20所示,可形成导电互连件162如焊接凸起、焊球、引脚等,使其与导电迹线158’接触并用于与外部部件(未示出)相连。图20显示了延伸穿过阻焊介质164的焊接凸起以形成组件160。在此之后,可从组件160(见图20)上切下(切割)单个的微电子封装170,如图21所示。
当然应当理解,可在微电子封装核心开口104中放置多个各种尺寸的微电子管芯,并与导电迹线158互连。
注射工艺的优点包括但不限于:消除了在压缩模制中会形成的空隙;不存在会使微电子管芯114形成裂纹的压力;分配可在较低的温度下进行,这使得可更简单地控制扭曲和管芯-管芯的不对准;以及由于分配是一个个管芯地来完成,因此可更容易地实施此工艺。
通过上述对本发明实施例的详细介绍,应当理解,由所附权利要求定义的本发明不限于上述的特定细节,在不脱离本发明的精神实质或范围的前提下,可对本发明进行多种明显的变动。

Claims (30)

1.一种制造微电子封装的方法,包括:
提供具有第一表面和相对的第二表面的微电子封装核心,所述微电子封装核心具有至少一个形成于其中的开口,其从所述微电子封装核心的第一表面延伸到所述微电子封装核心的第二表面;
将至少一个微电子管芯置于所述至少一个微电子封装核心开口内,所述至少一个微电子管芯具有有效面;
将分配工具定位在未被所述至少一个微电子管芯占据的所述微电子封装核心开口的附近;和
从所述分配工具中分配密封材料。
2.根据权利要求1所述的方法,其特征在于,定位所述分配工具包括将所述分配工具插入到未被所述至少一个微电子管芯占据的所述微电子封装核心开口中。
3.根据权利要求1所述的方法,其特征在于,从所述分配工具中分配所述密封材料还包括形成至少一个与所述微电子管芯的有效面和所述微电子封装核心的第一表面基本上成一平面的密封材料表面。
4.根据权利要求3所述的方法,其特征在于,所述方法还包括在所述密封材料的表面、所述微电子管芯的有效面和所述微电子封装核心的第一表面上形成互连层。
5.根据权利要求4所述的方法,其特征在于,形成至少一个互连层包括:
在所述微电子管芯的有效面、所述至少一个密封材料的表面和所述微电子封装核心的第一表面的至少一部分上形成至少一个介质材料层;
形成至少一个穿过所述至少一个介质材料层的通孔,以暴露出所述微电子管芯的一部分有效面;和
在所述至少一个介质材料层上形成至少一个导电迹线,所述导电迹线延伸到所述至少一个通孔中以与所述微电子管芯的有效面电接触。
6.根据权利要求5所述的方法,其特征在于,所述方法还包括在所述至少一个导电迹线和所述至少一个介质材料层上形成至少一个附加介质材料层。
7.根据权利要求6所述的方法,其特征在于,所述方法还包括形成至少一个附加导电迹线,其延伸穿过所述至少一个附加介质材料层并处于其上。
8.根据权利要求1所述的方法,其特征在于,所述提供所述微电子封装核心包提供选自双马来酰亚胺三嗪的树脂基层压材料、FR4层压材料、聚酰亚胺层压材料、陶瓷和金属的微电子封装核心。
9.根据权利要求1所述的方法,其特征在于,从所述分配工具中分配所述密封材料包括分配选自塑料、树脂、环氧树脂、弹性体材料的密封材料。
10.根据权利要求1所述的方法,其特征在于,所述方法还包括在从所述分配工具中分配所述密封材料之前在所述微电子封装核心的第一表面和所述微电子管芯的有效面上贴上保护膜。
11.根据权利要求10所述的方法,其特征在于,在所述微电子封装核心的第一表面和所述微电子管芯的有效面上贴保护膜包括在从所述分配工具中分配所述密封材料之前使所述微电子封装核心的第一表面和所述微电子管芯的有效面与所述保护膜的粘合层相贴合。
12.根据权利要求1所述的方法,其特征在于,所述方法还包括使所述密封材料固化。
13.根据权利要求1所述的方法,其特征在于,将分配工具定位在所述微电子封装核心开口内未被所述至少一个微电子管芯占据的至少一部分的附近包括将分配针定位在所述微电子封装核心开口内未被所述至少一个微电子管芯占据的至少一部分中。
14.一种用于制造微电子封装的方法,包括:
提供保护膜;
在微电子封装核心的第一表面上贴上所述保护膜,所述微电子封装核心具有至少一个形成于其中的开口,其从所述微电子封装核心的第一表面延伸到所述微电子封装核心的第二表面;
将至少一个微电子管芯放到所述微电子封装核心开口内,并使所述至少一个微电子管芯的有效面与所述保护膜贴合;
将分配工具定位在未被所述至少一个微电子管芯占据的所述微电子封装核心开口内;
从所述分配工具中分配密封材料;和
除去所述保护膜。
15.根据权利要求14所述的方法,其特征在于,定位所述分配工具包括将所述分配工具插入到未被所述至少一个微电子管芯占据的所述微电子封装核心开口中。
16.根据权利要求14所述的方法,其特征在于,分配所述密封材料包括形成至少一个与所述微电子管芯的有效面基本上成一平面的密封材料表面。
17.根据权利要求16所述的方法,其特征在于,所述方法还包括在所述多个微电子管芯的有效面和所述至少一个密封材料的表面的至少其中之一上形成互连层。
18.根据权利要求17所述的方法,其特征在于,形成互连层包括:
在所述微电子管芯的有效面和所述至少一个密封材料的表面的至少一部分上形成至少一个介质材料层;
形成至少一个穿过所述至少一个介质材料层的通孔,以暴露出所述微电子管芯的一部分有效面;和
在所述至少一个介质材料层上形成至少一个导电迹线,所述导电迹线延伸到所述至少一个通孔中以与所述微电子管芯的有效面电接触。
19.根据权利要求18所述的方法,其特征在于,所述方法还包括在所述至少一个导电迹线和所述至少一个介质材料层上形成至少一个附加介质材料层。
20.根据权利要求19所述的方法,其特征在于,所述方法还包括形成至少一个附加导电迹线,其延伸穿过所述至少一个附加介质材料层并处于其上。
21.根据权利要求14所述的方法,其特征在于,提供所述保护膜包括提供具有粘合剂的所述保护膜;在所述至少一个微电子管芯的有效面上贴上所述保护膜包括使所述至少一个微电子管芯的有效面与所述保护膜的粘合层贴合。
22.根据权利要求14所述的方法,其特征在于,所述提供所述微电子封装核心包括提供选自双马来酰亚胺三嗪的树脂基层压材料、FR4层压材料、聚酰亚胺层压材料、陶瓷和金属的微电子封装核心。
23.根据权利要求14所述的方法,其特征在于,从所述分配工具中分配所述密封材料包括分配选自塑料、树脂、环氧树脂、弹性体材料的密封材料。
24.根据权利要求14所述的方法,其特征在于,所述方法还包括使所述密封材料固化。
25.一种用于制造微电子封装的方法,包括:
提供第一保护膜;
在微电子封装核心的第一表面上贴上所述第一保护膜,所述微电子封装核心具有至少一个形成于其中的开口,其从所述微电子封装核心的第一表面延伸到所述微电子封装核心的第二表面;
将至少一个微电子管芯放到所述微电子封装核心开口内,并使所述至少一个微电子管芯的有效面与所述保护膜贴合;
将第二保护膜贴在所述微电子封装核心的第一表面的第二表面和所述微电子管芯的背面上,以跨置在所述至少一个开口上;
将第一分配针通过所述第二保护膜插入到所述开口内;
将第二分配针通过所述第二保护膜插入到所述开口内;
用所述第一分配针抽出至少一个部分真空;和
从所述第二分配针中分配密封材料。
26.根据权利要求25所述的方法,其特征在于,分配所述密封材料包括形成至少一个与所述微电子管芯的有效面基本上成一平面的密封材料表面。
27.根据权利要求25所述的微电子封装,其特征在于,所述方法还包括在所述多个微电子管芯的有效面和所述至少一个密封材料的表面的至少其中之一上形成互连层。
28.根据权利要求25所述的方法,其特征在于,所述提供所述微电子封装核心包括提供选自双马来酰亚胺三嗪的树脂基层压材料、FR4层压材料、聚酰亚胺层压材料、陶瓷和金属的微电子封装核心。
29.根据权利要求25所述的方法,其特征在于,分配所述密封材料包括分配选自塑料、树脂、环氧树脂、弹性体材料的密封材料。
30.根据权利要求25所述的方法,其特征在于,所述方法还包括使所述密封材料固化。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102097337A (zh) * 2009-10-22 2011-06-15 英飞凌科技股份有限公司 使用重组晶圆的半导体器件制造的方法和设备
CN103367169A (zh) * 2012-03-27 2013-10-23 通用电气公司 超薄包埋模模块及其制造方法
CN107295746A (zh) * 2016-03-31 2017-10-24 奥特斯(中国)有限公司 器件载体及其制造方法
CN107295747A (zh) * 2016-03-31 2017-10-24 奥特斯(中国)有限公司 器件载体及制造器件载体的方法

Families Citing this family (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020020898A1 (en) * 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6555906B2 (en) * 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer
US7498196B2 (en) 2001-03-30 2009-03-03 Megica Corporation Structure and manufacturing method of chip scale package
TW544882B (en) * 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
TW503496B (en) 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
US6673698B1 (en) 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
WO2004001848A1 (en) * 2002-06-19 2003-12-31 Sten Bjorsell Electronics circuit manufacture
US7485489B2 (en) * 2002-06-19 2009-02-03 Bjoersell Sten Electronics circuit manufacture
TWI251910B (en) * 2004-06-29 2006-03-21 Phoenix Prec Technology Corp Semiconductor device buried in a carrier and a method for fabricating the same
KR100645643B1 (ko) * 2004-07-14 2006-11-15 삼성전기주식회사 수동소자칩 내장형의 인쇄회로기판의 제조방법
FI20041525A (fi) * 2004-11-26 2006-03-17 Imbera Electronics Oy Elektroniikkamoduuli ja menetelmä sen valmistamiseksi
US7500531B2 (en) * 2005-10-03 2009-03-10 Latourneau Technologies Drilling Systems, Inc. Low speed AC motor for direct drive applications
US20070212813A1 (en) * 2006-03-10 2007-09-13 Fay Owen R Perforated embedded plane package and method
US8829661B2 (en) * 2006-03-10 2014-09-09 Freescale Semiconductor, Inc. Warp compensated package and method
JP4559993B2 (ja) * 2006-03-29 2010-10-13 株式会社東芝 半導体装置の製造方法
US7592202B2 (en) * 2006-03-31 2009-09-22 Intel Corporation Embedding device in substrate cavity
US7425758B2 (en) * 2006-08-28 2008-09-16 Micron Technology, Inc. Metal core foldover package structures
US7682872B2 (en) * 2007-03-02 2010-03-23 Stats Chippac Ltd. Integrated circuit package system with underfill
US7926173B2 (en) * 2007-07-05 2011-04-19 Occam Portfolio Llc Method of making a circuit assembly
JP2011501870A (ja) * 2007-05-08 2011-01-13 オッカム ポートフォリオ リミテッド ライアビリティ カンパニー はんだの無い電子組立体及びそれらの製造方法
US8300425B2 (en) * 2007-07-31 2012-10-30 Occam Portfolio Llc Electronic assemblies without solder having overlapping components
US20090072382A1 (en) * 2007-09-18 2009-03-19 Guzek John S Microelectronic package and method of forming same
US9941245B2 (en) * 2007-09-25 2018-04-10 Intel Corporation Integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate
US7851905B2 (en) 2007-09-26 2010-12-14 Intel Corporation Microelectronic package and method of cooling an interconnect feature in same
US8035216B2 (en) * 2008-02-22 2011-10-11 Intel Corporation Integrated circuit package and method of manufacturing same
US8093704B2 (en) 2008-06-03 2012-01-10 Intel Corporation Package on package using a bump-less build up layer (BBUL) package
FR2934082B1 (fr) * 2008-07-21 2011-05-27 Commissariat Energie Atomique Dispositif multi composants integres dans une matrice
TWI373113B (en) * 2008-07-31 2012-09-21 Unimicron Technology Corp Method of fabricating printed circuit board having semiconductor components embedded therein
US20100073894A1 (en) * 2008-09-22 2010-03-25 Russell Mortensen Coreless substrate, method of manufacturing same, and package for microelectronic device incorporating same
US20100167471A1 (en) * 2008-12-30 2010-07-01 Stmicroelectronics Asia Pacific Pte. Ltd. Reducing warpage for fan-out wafer level packaging
JP5330065B2 (ja) * 2009-04-13 2013-10-30 新光電気工業株式会社 電子装置及びその製造方法
US8263434B2 (en) * 2009-07-31 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP
US20110108999A1 (en) * 2009-11-06 2011-05-12 Nalla Ravi K Microelectronic package and method of manufacturing same
US20110156239A1 (en) * 2009-12-29 2011-06-30 Stmicroelectronics Asia Pacific Pte Ltd. Method for manufacturing a fan-out embedded panel level package
US8901724B2 (en) 2009-12-29 2014-12-02 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
US8742561B2 (en) 2009-12-29 2014-06-03 Intel Corporation Recessed and embedded die coreless package
US8535989B2 (en) 2010-04-02 2013-09-17 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
US8319318B2 (en) 2010-04-06 2012-11-27 Intel Corporation Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages
US8618652B2 (en) 2010-04-16 2013-12-31 Intel Corporation Forming functionalized carrier structures with coreless packages
US8939347B2 (en) 2010-04-28 2015-01-27 Intel Corporation Magnetic intermetallic compound interconnect
US9847308B2 (en) 2010-04-28 2017-12-19 Intel Corporation Magnetic intermetallic compound interconnect
US8313958B2 (en) 2010-05-12 2012-11-20 Intel Corporation Magnetic microelectronic device attachment
US8434668B2 (en) 2010-05-12 2013-05-07 Intel Corporation Magnetic attachment structure
US8609532B2 (en) 2010-05-26 2013-12-17 Intel Corporation Magnetically sintered conductive via
US20120001339A1 (en) 2010-06-30 2012-01-05 Pramod Malatkar Bumpless build-up layer package design with an interposer
US8372666B2 (en) 2010-07-06 2013-02-12 Intel Corporation Misalignment correction for embedded microelectronic die applications
US8754516B2 (en) 2010-08-26 2014-06-17 Intel Corporation Bumpless build-up layer package with pre-stacked microelectronic devices
US8304913B2 (en) 2010-09-24 2012-11-06 Intel Corporation Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby
US8502367B2 (en) 2010-09-29 2013-08-06 Stmicroelectronics Pte Ltd. Wafer-level packaging method using composite material as a base
US8937382B2 (en) 2011-06-27 2015-01-20 Intel Corporation Secondary device integration into coreless microelectronic device packages
US8848380B2 (en) 2011-06-30 2014-09-30 Intel Corporation Bumpless build-up layer package warpage reduction
US9679863B2 (en) 2011-09-23 2017-06-13 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interconnect substrate for FO-WLCSP
US9257368B2 (en) 2012-05-14 2016-02-09 Intel Corporation Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias
CN104321864B (zh) 2012-06-08 2017-06-20 英特尔公司 具有非共面的、包封的微电子器件和无焊内建层的微电子封装
WO2014045139A1 (en) * 2012-09-18 2014-03-27 Assa Abloy Ab Method of protecting an electrical component in a laminate
US9320149B2 (en) * 2012-12-21 2016-04-19 Intel Corporation Bumpless build-up layer package including a release layer
US9812350B2 (en) 2013-03-06 2017-11-07 Qorvo Us, Inc. Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer
US9583414B2 (en) 2013-10-31 2017-02-28 Qorvo Us, Inc. Silicon-on-plastic semiconductor device and method of making the same
US20150147845A1 (en) * 2013-11-26 2015-05-28 Texas Instruments Incorporated Dual sided embedded die and fabrication of same background
US10665475B2 (en) * 2014-06-11 2020-05-26 Texas Instruments Incorporated Quad flat no lead package and method of making
US10085352B2 (en) 2014-10-01 2018-09-25 Qorvo Us, Inc. Method for manufacturing an integrated circuit package
US10121718B2 (en) 2014-11-03 2018-11-06 Qorvo Us, Inc. Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer
US9613831B2 (en) 2015-03-25 2017-04-04 Qorvo Us, Inc. Encapsulated dies with enhanced thermal performance
US20160343604A1 (en) 2015-05-22 2016-11-24 Rf Micro Devices, Inc. Substrate structure with embedded layer for post-processing silicon handle elimination
US10276495B2 (en) 2015-09-11 2019-04-30 Qorvo Us, Inc. Backside semiconductor die trimming
US10020405B2 (en) 2016-01-19 2018-07-10 Qorvo Us, Inc. Microelectronics package with integrated sensors
US10090262B2 (en) 2016-05-09 2018-10-02 Qorvo Us, Inc. Microelectronics package with inductive element and magnetically enhanced mold compound component
US10773952B2 (en) 2016-05-20 2020-09-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10784149B2 (en) 2016-05-20 2020-09-22 Qorvo Us, Inc. Air-cavity module with enhanced device isolation
US10468329B2 (en) 2016-07-18 2019-11-05 Qorvo Us, Inc. Thermally enhanced semiconductor package having field effect transistors with back-gate feature
US10103080B2 (en) 2016-06-10 2018-10-16 Qorvo Us, Inc. Thermally enhanced semiconductor package with thermal additive and process for making the same
WO2018031994A1 (en) 2016-08-12 2018-02-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
WO2018031995A1 (en) 2016-08-12 2018-02-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
SG11201901196RA (en) * 2016-08-12 2019-03-28 Qorvo Us Inc Wafer-level package with enhanced performance
US10109502B2 (en) 2016-09-12 2018-10-23 Qorvo Us, Inc. Semiconductor package with reduced parasitic coupling effects and process for making the same
US10090339B2 (en) 2016-10-21 2018-10-02 Qorvo Us, Inc. Radio frequency (RF) switch
US10749518B2 (en) 2016-11-18 2020-08-18 Qorvo Us, Inc. Stacked field-effect transistor switch
US10068831B2 (en) 2016-12-09 2018-09-04 Qorvo Us, Inc. Thermally enhanced semiconductor package and process for making the same
DE102017105330B4 (de) 2017-03-14 2020-10-15 Infineon Technologies Austria Ag Leistungshalbleiterbauelement-Package und Verfahren zum Einbetten eines Leistungshalbleiter-Dies
US10490471B2 (en) 2017-07-06 2019-11-26 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
CN109300794B (zh) * 2017-07-25 2021-02-02 中芯国际集成电路制造(上海)有限公司 封装结构及其形成方法
US10784233B2 (en) 2017-09-05 2020-09-22 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10366972B2 (en) 2017-09-05 2019-07-30 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
EP3540766A1 (en) * 2018-03-12 2019-09-18 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Layer stack of component carrier material with embedded components and common high temperature robust dielectric structure
US11152363B2 (en) 2018-03-28 2021-10-19 Qorvo Us, Inc. Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
US10804246B2 (en) 2018-06-11 2020-10-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
US10964554B2 (en) 2018-10-10 2021-03-30 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11069590B2 (en) 2018-10-10 2021-07-20 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
JP7241518B2 (ja) * 2018-12-04 2023-03-17 株式会社ディスコ パッケージデバイスの製造方法
KR102595864B1 (ko) * 2018-12-07 2023-10-30 삼성전자주식회사 반도체 패키지
US11387157B2 (en) 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
CN113632209A (zh) 2019-01-23 2021-11-09 Qorvo美国公司 Rf半导体装置和其制造方法
US20200235040A1 (en) 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US20200235066A1 (en) 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US11121076B2 (en) 2019-06-27 2021-09-14 Texas Instruments Incorporated Semiconductor die with conversion coating
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS624351A (ja) 1985-06-29 1987-01-10 Toshiba Corp 半導体キヤリアの製造方法
FR2599893B1 (fr) 1986-05-23 1996-08-02 Ricoh Kk Procede de montage d'un module electronique sur un substrat et carte a circuit integre
JPH03155144A (ja) 1989-11-13 1991-07-03 Sharp Corp ベアー半導体icチップ実装方法
EP0604005A1 (en) 1992-10-26 1994-06-29 Texas Instruments Incorporated Device packaged in a high interconnect density land grid array package having electrical and optical interconnects
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5397921A (en) * 1993-09-03 1995-03-14 Advanced Semiconductor Assembly Technology Tab grid array
US5457299A (en) * 1993-10-29 1995-10-10 International Business Machines Corporation Semiconductor chip packaging method which heat cures an encapsulant deposited on a chip using a laser beam to heat the back side of the chip
JPH1092970A (ja) 1996-09-19 1998-04-10 Toshiba Corp 基板モジュール
US6025995A (en) 1997-11-05 2000-02-15 Ericsson Inc. Integrated circuit module and method
US6329224B1 (en) 1998-04-28 2001-12-11 Tessera, Inc. Encapsulation of microelectronic assemblies
US6239482B1 (en) 1999-06-21 2001-05-29 General Electric Company Integrated circuit package including window frame
US6232667B1 (en) * 1999-06-29 2001-05-15 International Business Machines Corporation Technique for underfilling stacked chips on a cavity MLC module
US6271469B1 (en) * 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6154366A (en) * 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
US6320127B1 (en) * 1999-12-20 2001-11-20 Lsi Logic Corporation Method and structure for reducing the incidence of voiding in an underfill layer of an electronic component package
US6423570B1 (en) * 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
US20020070443A1 (en) * 2000-12-08 2002-06-13 Xiao-Chun Mu Microelectronic package having an integrated heat sink and build-up layers
US6555906B2 (en) * 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102097337A (zh) * 2009-10-22 2011-06-15 英飞凌科技股份有限公司 使用重组晶圆的半导体器件制造的方法和设备
CN102097337B (zh) * 2009-10-22 2015-08-26 英飞凌科技股份有限公司 使用重组晶圆的半导体器件制造的方法和设备
CN105185718A (zh) * 2009-10-22 2015-12-23 英飞凌科技股份有限公司 使用重组晶圆的半导体器件制造的方法和设备
CN105185718B (zh) * 2009-10-22 2019-04-30 英飞凌科技股份有限公司 使用重组晶圆的半导体器件制造的方法和设备
CN103367169A (zh) * 2012-03-27 2013-10-23 通用电气公司 超薄包埋模模块及其制造方法
CN103367169B (zh) * 2012-03-27 2018-02-27 通用电气公司 超薄包埋模模块及其制造方法
CN107295746A (zh) * 2016-03-31 2017-10-24 奥特斯(中国)有限公司 器件载体及其制造方法
CN107295747A (zh) * 2016-03-31 2017-10-24 奥特斯(中国)有限公司 器件载体及制造器件载体的方法
CN107295747B (zh) * 2016-03-31 2021-03-12 奥特斯(中国)有限公司 器件载体及制造器件载体的方法
CN107295746B (zh) * 2016-03-31 2021-06-15 奥特斯(中国)有限公司 器件载体及其制造方法

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MY128217A (en) 2007-01-31
US20020137263A1 (en) 2002-09-26
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