CN105185718B - 使用重组晶圆的半导体器件制造的方法和设备 - Google Patents

使用重组晶圆的半导体器件制造的方法和设备 Download PDF

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CN105185718B
CN105185718B CN201510486211.5A CN201510486211A CN105185718B CN 105185718 B CN105185718 B CN 105185718B CN 201510486211 A CN201510486211 A CN 201510486211A CN 105185718 B CN105185718 B CN 105185718B
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frame
chip
opening
wafer
multiple opening
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CN105185718A (zh
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H-J.巴特
M.希尔勒曼
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明描述了使用重组晶圆的半导体器件制造的方法和设备。在一个实施例中，将切割好的半导体芯片放置在框架上的开口内。通过将模塑料填充到所述开口中来形成重组晶圆。所述模塑料被形成在所述芯片周围。在所述重组晶圆内形成完成的小片。将完成的小片与所述框架分离。

Description

使用重组晶圆的半导体器件制造的方法和设备
本申请是申请日为2010年10月22日、申请号为201010533726.3以及发明名称为“使用重组晶圆的半导体器件制造的方法和设备”的发明专利申请的分案申请。
技术领域
本发明一般涉及半导体器件，并且更具体地，涉及使用重组晶圆(reconstitutedwafer)的半导体器件制造的方法和设备。
背景技术
晶圆级封装(WLP)指的是在晶圆级封装集成电路的技术，而不是在晶圆切割(dice)之后组装每个单独的单元的封装的传统工艺。WLP最接近于是真正的芯片尺度封装(CSP)技术。晶圆级封装在晶圆级集成了晶圆制造、封装、测试和预烧(burn-in)，并且简化了生产工艺。晶圆级封装拓展了晶圆制造工艺以包括器件互连和器件保护工艺。WLP的使用已显著增长，这源于它在尺寸、性能、灵活性、可靠性和成本上胜过其他封装方法的优势。
WLP的难点之一在于接触部的数量和/或接触面积的限制。克服这些限制的方法会导致产品成本增加和/或可靠性变差以及成品率损失。因此，所需要的是用于倒装芯片封装的方法和设备，所述倒装芯片封装不仅节约成本而且允许有改进的接触构造(contactformation)。
发明内容
通过本发明的示意性实施例，这些及其他问题一般地被解决或被避免，而且技术优势一般地被获得。
本发明的实施例包括使用重组晶圆的半导体器件制造的方法和设备。按照本发明的实施例，用于制造半导体器件的方法包括将切割好的半导体芯片放置在被布置在框架(frame)上的开口(opening)内。通过将模塑料(mold compound)填充到所述开口中来形成重组晶圆，所述模塑料被形成在所述芯片周围。在所述重组晶圆内形成完成的小片(finished die)。将所述完成的小片与所述框架分离。
上述内容相当宽泛地概述了本发明的实施例的特点，以使下面对本发明的详细描述可以更好地被理解。本发明的实施例的另外的特点和优势将在下文中被描述，这些特点和优势形成本发明的权利要求的主题。本领域的技术人员应当理解的是所公开的概念和具体实施例能够容易地被用作为实现本发明的相同目的而修改或设计其他结构或工艺的基础。本领域的技术人员还应当理解的是这样的等效构造不背离在所附权利要求中所提出的本发明的精神和范围。
附图说明
为了更全面地理解本发明及其优势，现在对结合附图所得到的以下说明进行参考，其中：
图1包括图1A-1C，其示意了球栅阵列封装，该封装示意了按照本发明的实施例在处理完成之后分离成单独的集成电路之前的重组晶圆，其中图1A示意了俯视图并且图1B示意了沿图1A的线1B的截面图，而图1C示意了沿图1A的线1C的截面图并且示意了被布置在单个开口内的多个芯片。
图2示意了按照本发明的实施例用于制造重组晶圆的框架。
图3-7示意了在各个生产阶段中制造晶圆级球栅阵列封装的实施例，其中图3A和4A示意了俯视图，而图3B、4B和5-7示意了截面图。
图8包括图8A-8C，其示意了按照本发明的实施例在处理期间的重组晶圆，其中图8A示意了俯视图并且图8B示意了在晶圆级处理的中间状态期间对应的截面图，而图8C示意了在晶圆级封装工艺完成之后的截面图。
图9包括图9A和9B，其示意了按照本发明的实施例在处理期间的重组晶圆的截面图。
图10包括图10A和10B，其示意了按照本发明的实施例在制造期间的重组晶圆的截面图；以及
图11包括图11A和11B，其示意了球栅阵列封装，该封装示意了在处理完成之后分离成单独的集成电路之前的现有技术的重组晶圆，其中图11A示意了俯视图并且图11B示意了沿图11A的线11B的截面图。
不同的图中对应的数字和符号一般指的是对应的部分，除非另作说明。制图是为了清楚地示意实施例的有关方面而不一定是按比例绘制的。
具体实施例
各种实施例的得到和使用在下面详细论述。但是，应当理解的是本发明提供了许多适用的创造性概念，这些概念可以在各种不同的具体背景下被实施。所论述的具体实施例仅仅是得到和使用本发明的具体方式的示意，而不限制本发明的范围。
将相对于具体背景下的各种实施例来描述本发明，所述具体背景即晶圆级封装。但是，本发明也可以被应用于其他类型的封装技术。
晶圆级封装(WLP)是针对高速封装需求的有发展前途的解决方案。因为WLP上的互连线的长度受小片尺寸限制，所以WLP具有最小数量的电性寄生元件。在晶圆级封装(WLP)中，集成电路在晶圆级被封装，代替在晶圆切割之后组装每个单独的单元的封装的传统工艺。WLP是真正的芯片尺度封装技术，因为最终的封装与小片的尺寸大致相同。通过拓展晶圆制造工艺而包括器件互连和器件保护工艺，晶圆级封装在晶圆级把晶圆制造工艺与封装以及可能地与测试和预烧集成，简化和降低了生产成本。
在WLP中，WLP上的重分布线将片上(on-chip)焊垫(pad)连接于被用来放置焊球的凸块垫(bump pad)。使用器件制造本身所采用的标准光刻和薄膜沉积技术来形成这些重分布线。这个附加的互连层级使每个芯片的周边的(peripheral)接合垫(bonding pad)重新分布为均匀地部署在芯片表面上的凸块垫的面阵(area array)。在将所述器件连接于应用电路板时所用的焊球或焊料凸块随后被放置在这些凸块垫上。在一些实施例中，这些凸块垫含有铜或铜合金。在其他实施例中，这些凸块垫包含铝或铝合金或者任何其他适合的金属。在其他实施例中，这些凸块垫可以在焊垫金属和焊球之间具有凸块下金属化(UBM)。将焊垫金属与焊球分离的UBM可以含有不同的材料或材料组合。在一些实施例中，UBM包含Ni、Au、Cu、V、Cr、Mo、Pd、W、Ti、TiN、TiW或任何组合物(combination)，如Ni/Au、Ni/Pd、Ni/Pd/Cu、Ti/Cu、TiW/Cu、TiN/Cu、Ti/Ni/V、Cr/Cu或任何其他组合物。除了提供WLP的外部连接装置以外，这种重分布技术还通过允许将更大和更健壮的球用于互连以及允许对器件的I/O系统更好的热管理来提高芯片可靠性。
扇入型WLP指的是标准晶圆级封装，其中封装面积与芯片面积大致相同。因此，封装受输入/输出连接数量的限制。在扇出型WLP中，封装包括围绕芯片区域的附加的空间以形成附加的输入/输出(I/O)连接。该附加的空间允许形成WLP凸块垫用于与芯片的电路系统的连接。
在常规的扇出型WLP中，在前端和后端处理完成之后，晶圆被切割以形成单独的芯片。这些切割好的芯片被布置在胶带上，同时在这些芯片之间保持预定的间隔，所述胶带被布置在载体(carrier)上。这个预定的间隔比晶圆上芯片之间的间隔大。通常(但不一定)，在胶带上的被胶合的芯片仿效晶圆的形状以圆形的方式被布置。将模塑料或环氧化合物(epoxy compound)倒入以填充芯片间的空隙。模塑料例如通过退火被固化，以形成包含模塑料和单独的芯片的重构晶圆(reconfigured wafer)或重组晶圆。将重构晶圆与胶带分离并且接着进行随后的处理以形成重分布线、焊球等。
这种技术的难点之一在于单独的芯片和模塑料之间的热膨胀系数的差异。基于硅的芯片的热膨胀系数小于大约2ppm/℃，而模塑料通常有高得多的热膨胀系数，例如大于10ppm/℃。因此，在需要热循环的随后的处理期间，应力在重组晶圆内聚集。重组晶圆内的应力使得重组晶圆弯曲。
特别地，在电介质(模塑料、聚酰亚胺、WPR等)的固化期间的热处理导致重组晶圆的弯曲(bowing)和变形(warpage)。例如，对于200mm晶圆，这种弯曲和变形从晶圆的中心到边缘可能有若干毫米。对于300mm晶圆，问题更严重。
与典型的硅晶圆相比，重组晶圆的弯曲和变形程度远远更高，并且在自动生产设备中引起处理问题、在等离子工艺期间引起对准问题、非均匀层厚度以及非均匀电耦合。这些问题继而体现为减小的产品成品率和/或可靠性差的器件。
解决上述问题的一个途径是引入整平(flattening)步骤。这些整平步骤通过加热晶圆并随后迅速降温来执行，而由此暂时冻结重组晶圆的平面性(planarity)。但是，在该整平步骤之后的任何随后的热处理都会增加弯曲和变形并且需要另一整平步骤。
另外，在模塑(mold)的固化期间，为了形成重组晶圆，模塑材料收缩并且可能在小片放置之后使单独的小片偏移离开它们的初始位置。这种不利的效果被称为“小片偏移(die shift)”并且由于随后的光刻步骤相对于偏移的小片未对准而导致成品率问题。
在各种实施例中，本发明通过提供可重复使用的框架来形成重组晶圆而以节约成本的方式克服了这些和其他限制。在处理之后，所述框架被重复用于随后的处理。在各种实施例中，框架的使用减少了重组晶圆中模塑料的体积分数，由此直接减少了在随后的处理期间在重组晶圆内聚集的残余应力。
首先将用图1描述示出制造工艺期间的重组晶圆的、本发明的结构上的实施例。将用图2按照本发明的实施例来描述用于制造重组晶圆的框架。将结合图8和图9来描述所述框架的另外的结构上的实施例。将用图3-7按照本发明的实施例来描述生产晶圆级封装的制造工艺。将结合图10来描述制造工艺的可替换的实施例。
图1包括图1A-1C，其示意了按照本发明的实施例在晶圆级封装完成之后分成单独的集成电路之前的重组晶圆。图1A示意了俯视图而图1B示意了沿图1A的线1B的截面图，并且图1C示意了沿图1A的线1C的截面图。
参见图1A，重组晶圆1包含具有开口25的框架20。芯片50被布置在开口25内并且被填充以模塑料30。芯片50由包含有源器件、三极管、互连线和接触垫的前侧表面以及由裸硅构成的背侧表面组成。芯片的背侧硅表面可以接地(ground)或向内蚀刻到一定厚度。在一些实施例中，芯片的背侧表面可以被硅上面的电介质层或甚至是导电层覆盖。将芯片50面朝下布置在开口25内，使带有有源器件、互连线和焊垫的前侧表面与胶带接触。每个开口25可以包含多于一个芯片。例如，图1A示出两个芯片；第一芯片50a和第二芯片50b，它们一起被布置在一些开口25中。在各种实施例中，在芯片上制造系统时，通常所有开口都被填充以多个芯片。例如，在一个实施例中，第一芯片50a包含诸如处理器的功能芯片，而第二芯片50b包含存储部件。类似地，在各种实施例中，模拟的、数字的、高电压的、非易失性的芯片均可以被放置在开口25内。在各种实施例中，多个芯片可以被放置在开口25内。类似地，在一些实施例中，例如在制造微处理器芯片时，所述开口可以仅被填充以单个芯片。
图1B示意了截面图并且示出了被模塑料30围绕的芯片50。重分布线150被嵌入第一电介质层110中，并且被耦合于芯片50的最后的金属化层级(last metalization level)上的焊垫95。重分布线150耦合于焊料凸块170所附接的凸块垫。
如在图1A和1B中可见，与常规的重组晶圆相比，模塑料30的分数相对于芯片50显著地被降低，在常规的重组晶圆中模塑料而非框架被用于形成重组晶圆的大部分。事实上，如图1B所示，在本发明的各种实施例中，横向对比于重组晶圆1中的芯片50，模塑料30具有更低的体积分数。例如，在图1B中，沿图1A中的线1B-1B的模塑料30的分数(Fm)是大约6Lm/Lt，而沿图1A中的线1B-1B的芯片50的分数(Fc)是大约3Lc/Lt。由于模塑料的长度与重组晶圆1的总长度相比相对小，模塑料30的分数(Fm)显著地被减小。减小的模塑料的分数(Fm)减少了在随后的热处理期间的应力聚集。在各种实施例中，模塑料30的分数(Fm)小于0.5，并且在一个实施例中小于0.1。
另外，在本发明的各种实施例中，模塑料30的体积分数低于重组晶圆1中的芯片50的体积分数。模塑料30的体积分数被定义为重组晶圆1中的模塑料30的总体积除以重组晶圆1的总体积。类似地，芯片50的体积分数被定义为重组晶圆1中的所有芯片50的总体积除以重组晶圆1的总体积。在各种实施例中，模塑料30的体积分数小于0.5，并且在一个实施例中小于0.1。
在各种实施例中，框架20的热膨胀系数与芯片50的热膨胀系数大致相同。因此，与模塑料30不同，框架20在热循环时不释放任何应力。在一个实施例中，框架包含与芯片50相同的材料。在其他实施例里，框架20包含具有与芯片50相似的热膨胀系数的材料。在一个实施例中，热膨胀系数是芯片50的热膨胀系数的大约0.5倍到大约2倍。
图1C示意了按照本发明的实施例被布置在框架20的单个开口内的多个芯片，并且示意了沿图1A的线1C的截面图。
参见图1C，多个芯片50a和50b被布置在框架20的开口25内。该开口已被填充以模塑料，由此将芯片50a和芯片50b隔开。芯片50a和芯片50b通过重分布线150耦合在一起。
图2示意了按照本发明的实施例用于制造重组晶圆的框架。
框架20包含多个开口25，在每个开口25之间有预定的间隔。在各种实施例中，不同开口尺寸和不同间隔的框架可以被用于不同类型的芯片。在芯片的生产之前，框架20专门为所设计的每种芯片被开发。用于每种芯片设计的框架基于芯片的尺寸以及工艺技术流程被开发。在一些实施例中，如果芯片的尺寸相似，则具有不同设计的不同芯片可以使用共同的框架。例如，可以基于芯片尺寸将芯片分成不同的类别，而框架20可以被设计用于每个类别中的所有芯片。
在各种实施例中，在后端处理结束之后，框架20中的开口25的总数与晶圆中的芯片的总数大致相同。在一些实施例中，为了减小重组晶圆1的尺寸(例如为了也使生产有兼容性)，框架20中的开口25的数量可以小于晶圆中的芯片50的总数。
框架20中的开口25的总数取决于晶圆技术和芯片的尺寸。另外，框架20中的开口25的总数和开口25的尺寸也取决于模塑上的扇出区域(fan-out area)中所需要的凸块垫或I/O连接的数量。例如，用于300mm技术的框架20可以包含大约50到大约1000个开口，这取决于芯片的尺寸以及相应的产品的I/O需求(即凸块垫的数量)。类似地，例如，用于200mm技术的框架20取决于芯片的尺寸可以包含大约20到大约500个开口。
成图案地将开口25布置在框架20内并且在一个实施例中开口25可以有相等的尺寸。开口25之间的预定的间隔大于硅晶圆上芯片50之间的间隔。在各种实施例中，开口25之间的间隔是大约0.5mm到大约5mm。在各种实施例中，开口25之间的间隔是晶圆直径的大约0.2％到大约5％。
在图2中，框架按晶圆的形式包含单一分割的(singulated)小片开口。在各种实施例中，可以使用任何其他形式的框架(例如矩形板)和/或开口(例如圆形开口)。
在各种实施例中，框架20可以包含多个层，诸如带有另一材料(诸如二氧化硅)的顶部涂层的硅衬底。在一个实施例中，框架20包含硅。可替换地，框架20可以用具有与硅类似的热膨胀系数的其他材料制成。在一些实施例中，框架20可以包含其他半导体材料。例子包括SiC、InP、GaAs、钨、钼、铪、氧化锆、一碳化锆、氧化铝、氮化铝、矾土(alumina)、铝硅酸盐玻璃、石英、硼硅酸盐玻璃及其组合。
图3-7示意了在各个生产阶段制造晶圆级封装的实施例。图3A和4A示意了俯视图，而图3B、4B和5-7示意了制造期间的截面图。
参见图3A和3B，框架20被放置在胶带10上，该胶带可以被放置在载体上。框架20的底部表面8(图3B)被放置在胶带10上。芯片50接着被放置在框架20的开口25内。芯片50被放置使得芯片上的有源器件和用于重分布线的接触垫与框架20的底部表面8大致共面或稍微凹进入框架20的底部表面8。如图3A所示，在各种实施例中多个芯片可以被放置在单个开口25内。在各种实施例中，芯片50是静止的而在将芯片50放置在框架20内时框架20是移动的。可替换地，在一些实施例中，芯片50可以被移动并且被放入静止的框架20内。类似地，在所示的实施例中，只有芯片50被放置在开口25内。但是，在使用不同类型的封装技术的可替换的实施例中，附加的封装层或衬底可以被放置在开口25内。例如，在一些实施例中，芯片50的衬底可以被放置在开口25的每一个内。在这样的实施例中，衬底可以包含适用于电传导或热传导的装置/材料。
参见图4A和4B，芯片50周围的未被填充的开口被填充以模塑料30。在各种实施例中，通过任何适合的技术来沉积模塑料30，包括旋涂、喷射或印制。
在模塑料30的沉积之后，应当通过擦(wipe)、刮(scrap)或其他平面化工艺来移除框架的顶部表面7上任何多余的模塑。但是，在各种实施例中，重要的是在这个工艺期间，框架在任何情况下保持完好并且不被弄薄或修改。随后，模塑经受固化工艺，由此形成重组晶圆1。
另外，模塑可以先被固化，随后进行多余模塑的平面化，例如通过化学机械抛光(CMP)或回蚀工艺。同样地，在各种实施例中，框架20在CMP或蚀刻工艺期间不被弄薄或修改。
在形成重组晶圆1之后将胶带10移除。在各种实施例中，胶带10可以机械地被剥除或通过将胶带10加热到胶带10表面上的粘合剂失去粘性的温度而被移除。
由此形成的重组晶圆1可以与常规处理中的正规的晶圆(regular wafer)一样被处理。在各种实施例中，晶圆级处理被使用，但是在可替换的实施例中，其他封装技术可以被用于形成接触部。
类似于扇出型WLP，重组晶圆1在单独的芯片50之间包括更大的间隔并且包括围绕芯片50中的每一个的模塑料30的区域。因此，可以在模塑料30上和/或在芯片50上得到接触部，从而具有扇出型WLP中的接触构造的所有优势。可替换地，重组晶圆1可以被形成为不同形状，例如被形成为在表面面积方面效率更高的矩形。但是，非圆形的形状可能无法与现有设备兼容。
图5示意了在晶圆级封装期间重组晶圆1内相邻芯片的截面图。图5-7仅示意了几个芯片的截面图，但WLP工艺跨重组晶圆1一致地适用。
在可替换的实施例中，可以使用其他封装技术来处理重组晶圆1。例如，在一个实施例中，可以将芯片50和模塑料30与框架20分离并且使用诸如引线接合等可替换的封装技术继续随后的处理。
参见图5的截面图，芯片50被框架20的一部分隔开并且被模塑料30围绕。第一电介质层110被形成并且为了重分布线而被图形化。
第一电介质层110被形成在重组晶圆1的暴露的底部表面8上。在各种实施例中，第一电介质层110例如通过旋涂工艺被涂布，或通过使用化学气相沉积工艺被涂敷。在各种实施例中，第一电介质层110包含有机聚合物、BCB、聚酰亚胺、光电酰亚胺或无机电介质。
在一些实施例中，第一电介质层110也是光敏性的并且可以用光刻直接曝光。光敏性的第一电介质层110的例子包括可以直接被显影的光敏聚酰亚胺。在光敏性的电介质的这种情况下，可以通过光刻曝光和显影使电介质图形化，使得芯片上的接触部或接合垫以及框架可以在单一的光致步骤(photo step)中被展露(open)。这意味着将第一电介质层110从芯片上的接触部或接合垫上以及从框架区域上移除。
在非光敏性的聚酰亚胺的情况下，光致抗蚀剂被沉积。通过使用光刻工艺，第一电介质层110被图形化以展露接合垫95和框架区域。
在各种的实施例中，第一电介质层110没有被沉积在框架20上。可替换地，第一电介质层110被沉积并且使用光刻步骤来移除。在各种的实施例中，使用与用于展露接合垫95的图形化步骤相同的光刻步骤来移除第一电介质层110。例如，框架上的光敏性的第一电介质层110在形成展露接合垫95的图案的同时被移除。
在其他实施例中，可以在完成所有晶圆级封装步骤之后使用共同的蚀刻工艺将第一电介质层110连同第二电介质层155(其在图7中被形成)一起移除。因此，如图5所示，第一电介质层110仅被沉积在芯片50和模塑料30上。
参见图6，金属衬垫(metallic liner)120可选地被沉积在整个重组晶圆上(即在电介质110上面的芯片区域上以及直接在没有电介质110的框架上)。在各种的实施例中，使用沉积工艺来沉积金属衬垫120以形成包含Ti、Ta、Ru、W、其组合物，或者其氮化物、硅化物或碳化物的共形或近似共形的层。这样的组合物的例子包括TiN、TaN、WN和TiW。在各种的实施例中，使用化学气相沉积、等离子气相沉积、溅射工艺或原子层沉积来沉积金属衬垫120。在各种实施例中，金属衬垫120包含大约20nm到大约200nm的厚度。金属衬垫120是片上接合垫和随后的重分布层之间的扩散阻挡金属，并且防止铜从最后的金属线向外扩散以及防止与另外的金属层的任何混合。
另外的金属种子层(metallic seed layer)在一些实施例中被沉积。该金属种子层覆盖金属衬垫120。在各种实施例中，使用沉积工艺来沉积金属种子层以形成共形或近似共形的层。在各种实施例中，使用化学气相沉积、等离子气相沉积、溅射工艺或原子层沉积来沉积金属种子层。在各种实施例中，金属种子层包含大约20nm到大约200nm的厚度。金属种子层提供种子层以在电镀工艺期间生长。在各种实施例中，金属种子层包含铜或其他金属，像Al、W、Ag、Au、Ni或Pd。
如图6所示，厚的光致抗蚀剂层140被沉积。在各种实施例中，光致抗蚀剂层有若干微米厚，并且在一个实施例中从大约1μm到大约10μm不等。光致抗蚀剂层140被曝光并且被显影。图形化的光致抗蚀剂层140包含用于重分布金属线、焊垫通孔(pad vias)和凸块垫的图案。
如图7所示，包含重分布金属线150和接触垫的重分布层通过在金属衬垫120上沉积填充金属来形成。重分布层可以通过电镀、溅射来沉积，或通过其他任何适合的工艺来沉积。
在各种实施例中，重分布层的填充金属包含铜，但是在一些实施例中其他适合的导体被使用。在一个实施例中，金属衬垫和种子层120包含与随后的金属线的材料相同的材料以允许电镀。
在各种实施例中，重分布金属线150包含多个层，例如在一个实施例中包含Cu/Ni、Cu/Ni/Pd/Au、Cu/NiMoP/Pd/Au或Cu/Sn。在一个实施例中，重分布金属线150包含Ti/Cu/Ni层。
图形化的光致抗蚀剂层140被剥去以暴露出金属衬垫和种子层120。接着使用例如湿蚀刻化学反应(chemistry)将被暴露的金属衬垫和种子层120蚀刻掉(etch away)。第二电介质层155被沉积。在各种实施例中，第二电介质层155例如通过旋涂工艺被涂布，或使用化学气相沉积工艺被涂敷。在各种实施例中，第二电介质层155包含有机聚合物、BCB、聚酰亚胺、光电酰亚胺或无机电介质。
将第二电介质层155图形化以展露接触垫95和框架20。如在前面的步骤中所描述的，没有第二电介质层155留在框架20上。在一些实施例中，电介质膜的锥形侧壁可以被形成在接近框架交界面的、重构的小片的边缘(围绕芯片50的模塑料30的边缘)处。
凸块金属(未示出)被沉积在重分布层上的被暴露的接触垫或凸块垫上。凸块金属优选地以焊球的形式被放置到凸块垫上。凸块金属可替换地被电镀到重分布层上的种子层上，但是在其他实施例中，也可以使用其他工艺，诸如无电镀或诸如气相沉积的沉积工艺。凸块金属可以是单个层或包含带有不同成分的多个层。例如，在一个实施例中，凸块金属包含铅(Pb)层，随后是锡(Sn)层。在另一实施例中，Sn/Ag层可以作为凸块金属被沉积。其他例子包括SnPbAg、SnPb、PbAg、PbIn以及无铅材料，诸如SnBi、SnAgCu、SnTn和SiZn。在各种实施例中，其他适合的材料可以被沉积。
衬底被加热以回流(reflow)凸块金属，并且在重分布层上，该加热在接触垫95上形成焊料凸块170。在回流之后，均匀的焊料凸块170被形成。例如，在Pb/Sb层被沉积的实施例中，在回流之后，包括具有超过300℃的熔化温度的95Pb/5Sn(95/5)或90Pb/10Sn(90/10)的高铅合金被形成。在不同的实施例中，具有183℃的熔化温度的低共熔(eutectic)的63Pb/37Sn(63/37)被形成。类似地，包含97.5Sn/2.5Ag(97.5/2.5)的成分的无铅焊料凸块可以被形成。Sn和Ag或Sn、Ag和Cu的其他无铅焊料混合物可以被用在不同的实施例中。焊料凸块170包含均匀的材料并且具有明确定义的熔化温度。例如，高熔点的Pb/Sn合金是可靠的凸块冶金(bump metallurgies)，其特别地可抵抗材料疲劳。
如图7所示，在完成所有晶圆级封装步骤之后，将完成的小片与框架20分离。在这个处理阶段之后，每个小片包含芯片50、模塑料30、重分布层(例如重分布线150)和焊料凸块170。
在一个实施例中，通过把完成的小片从框架中推出而将框架20与小片分离。有利地，在各种实施例中，框架20在处理期间相对地未被改变。因此，在移除完成的小片后以及在验收和可选的清洗工艺之后，框架20如上文所述的那样被重新用于处理。
图8包括图8A-8C，其示意了按照本发明的实施例在分成小片之前的重组晶圆。图8A示意了俯视图而图8B示意了在使用晶圆级封装的、中间的制造阶段期间对应的截面图。就生产来说，图8A和8B对应于与结合图4所描述的相同的制造阶段。图8C示意了晶圆级封装完成之后的重组晶圆。
类似于结合图1A所描述的实施例，重组晶圆1包含具有开口25的框架20。芯片50被布置在开口25内，并且被填充以模塑料30。但是，在这个实施例中，框架20比芯片50厚。因此，如图8B所示，模塑料30覆盖芯片50的背侧。有利地，在框架20的顶部表面7上没有暴露芯片50，并且因此不需要附加的保护层来保护芯片50。
图8C示意了WLP工艺完成之后的晶圆级封装的截面图。
参见图8C，芯片50被模塑料30围绕。重分布线150被嵌入第一电介质层110中并且被耦合于芯片50的最后的金属化层级上的焊垫95。重分布线150耦合于焊料凸块170所附接的凸块垫。
如图8C所示，模塑料30在芯片50下形成保护层。厚的框架20还提供更好的机械支持并且很可能有更长的使用寿命(例如由于其更好的机械可靠性)，而且因此更经得起重复的处理。
图9包括图9A和图9B，其示意了按照本发明的实施例在晶圆级封装后完成之分成小片之前的重组晶圆的截面图。图9示出了在胶带10被移除之前的晶圆并且对应于与结合图4B所描述的相同的制造阶段。
参见图9A，框架20上的开口25包含锥形侧壁75以有利于在所有晶圆级处理(例如上文所描述的重分布层和焊球处理)完成之后从框架20中容易地移除完成的小片。
图9B示意了可替换的实施例，其中框架20的开口25的侧壁75包括第一和第二锥形部分76和77。第一锥形部分76允许更好的粘合，并且因此在晶圆级处理期间提供方便的使用。在处理之后，完成的小片由于第二锥形77而可以容易地被移除。
图10包括图10A和图10B，其示意了按照本发明的实施例在制造期间的重组晶圆的截面图。图10A示意了在填入模塑料之前的截面图，而图10B示出了在移除胶带10之前的晶圆，并且对应于与结合图4B所描述的相同的制造阶段。
制造工艺遵照之前的实施例，并且如结合图2所描述的那样使用框架20。参见图10A，框架20被放置在胶带10上，该胶带可以被放置在载体上。框架20的底部表面8被放置在胶带10上。芯片50接着如结合图3A和图3B所描述的那样被放置在框架20的开口25内。
在放置芯片50之后，弱粘合层(poor adhesion layer)85被沉积在开口25的侧壁上。在各种实施例中，弱粘合层85被涂布在开口25的侧壁上。在一些实施例中，弱粘合层85可以仅被形成在开口25的一些边缘或侧壁上。在各种实施例中，弱粘合层85也可以覆盖框架20的顶部表面。
弱粘合层85包含不强力粘合于框架20的材料。因此，在处理完成之后，弱粘合层85提高了从框架20中移除或分离完成的小片的容易性。相对于使用模塑料30，弱粘合层85易于剥除或破裂；这使得将完成的小片与框架20分离更加容易，并且使对框架20的任何潜在损害最小化。在各种实施例中，弱粘合层85与框架20比与模塑料30粘合地更好。因此，在分离之后，弱粘合层85的大部分仍然被布置在框架20上并且可以被清洗，例如使用湿化学蚀刻工艺。任何适合的材料都可被用作弱粘合层85，包括低k值的材料、有机聚合物、苯并环丁烯(BCB)、聚酰亚胺、无机电介质等。类似地，具有与模塑料30不同的成分的聚酰亚胺膜可以被用在实施例中。可以控制弱粘合层85的厚度来避免芯片50在处理完成之前的机械分离。
如图10B所示，模塑料填充芯片50和弱粘合层85之间剩余的开口。进一步的处理如在上文中例如结合图4-7所描述的那样继续进行。
图11包括图11A和11B，其示意了球栅阵列封装，该封装示意了在处理完成之后分离成单独的集成电路之前的现有技术的重组晶圆，其中图11A示意了俯视图并且图11B示意了沿图11A的线11B的截面图。
参见图11A和11B，重组晶圆1具有被模塑料30围绕的芯片50。图11B示意了耦合于芯片50的最后的金属化层级上的焊垫95的重分布线150。重分布线150耦合于焊料凸块170所附接的凸块垫。与本发明的实施例不同，重分布线150被嵌入布置于模塑料30上的连续的第一电介质层110中。
尽管已详细描述了本发明及其优势，应当理解的是，可以在此得到各种变化、替换和改动而不背离所附权利要求所定义的本发明的精神和范围。例如，本领域的技术人员将容易理解，在此所描述的特点、功能、工艺和材料中的许多可以被改变而仍保持在本发明的范围内。
此外，本申请的范围并无意图受限于在说明书中所描述的工艺、机器、产品、物质组成、装置、方法和步骤的特定实施例。如本领域的一个普通技术人员根据本发明的公开内容将容易地理解的那样，执行与在此所描述的对应的实施例大体上相同的功能或者获得与其大体上相同的结果的，现有的或以后要开发的工艺、机器、产品、物质组成、装置、方法或步骤可以按照本发明被利用。相应地，所附的权利要求意图是在其范围内包括这样的工艺、机器、产品、物质组成、装置、方法或步骤。

Claims (20)

1.一种可重复使用的框架，包括：
圆柱形硅衬底，其具有至少200 mm的直径；以及
被布置在所述硅衬底内的多个开口，其中所述多个开口具有锥形侧壁，其中所述多个开口被布置成多个行和列，其中沿行的开口数量对于沿所述直径对准的中心行具有最大值，其中所述多个开口中的每一个被所述框架的一部分隔开，其中所有所述多个开口具有相同的形状和尺寸。
2.根据权利要求1所述的框架，其中沿列的开口数量对于沿所述直径对准的中心列具有最大值，其中沿所述中心行的开口数量与沿所述中心列的开口数量相同。
3.根据权利要求1所述的框架，其中所述多个开口被配置成在所述多个开口的同一开口中保持第一类型的半导体芯片和第二类型的半导体芯片。
4.根据权利要求1所述的框架，其中所述多个开口中的每一个被配置成保持仅单个半导体芯片。
5.根据权利要求1所述的框架，其中所述多个开口被配置成保持多个半导体芯片，其中放置在所述框架中的一个开口内的半导体芯片与放置在所述框架中的邻近开口内的另一芯片被所述框架的一部分隔开。
6.根据权利要求1所述的框架，其中所述多个开口在底部表面处比在所述框架的相对的顶部表面与所述底部表面之间半程的距离处具有更大的直径。
7.根据权利要求1所述的框架，其中所述框架中的所述多个开口被配置成填充模塑料以形成重组晶圆。
8.一种可重复使用的框架，包括：
圆柱形半导体衬底，其具有至少200 mm的直径；以及
被布置在所述半导体衬底内的多个开口，其中所述多个开口具有锥形侧壁，其中所述多个开口被布置成多个行和列，其中沿行的开口数量对于沿所述直径对准的中心行具有最大值，其中所述多个开口中的每一个被所述框架的一部分隔开，其中所述可重复使用的框架被配置成：
在第一工艺步骤期间保持多个第一半导体芯片并且填充第一模塑料以形成第一重组晶圆，以及
在不同的第二工艺步骤期间保持多个第二半导体芯片并且填充第二模塑料以形成第二重组晶圆。
9.根据权利要求8所述的框架，其中所有所述多个开口具有相同的形状和尺寸。
10.根据权利要求8所述的框架，其中沿列的开口数量对于沿所述直径对准的中心列具有最大值，其中沿所述中心行的开口数量与沿所述中心列的开口数量相同。
11.根据权利要求8所述的框架，其中所述可重复使用的框架被配置成在所述多个开口中的每一个开口中保持多于一个半导体芯片。
12.根据权利要求8所述的框架，其中所述可重复使用的框架被配置成在所述多个开口中的每一个开口中保持仅一个半导体芯片。
13.根据权利要求8所述的框架，其中所述多个开口在底部表面处比在所述框架的相对的顶部表面与所述底部表面之间半程的距离处具有更大的直径。
14.一种制造半导体器件的方法，所述方法包括：
提供包含多个开口的可重复使用的框架；
将第一芯片和第二芯片放置在所述多个开口的开口中，其中所述开口中的所述第一芯片和所述第二芯片与放置在所述多个开口的邻近开口内的另一芯片被所述可重复使用的框架的一部分隔开；
将模塑料填充到所述多个开口中，所述模塑料被形成在所述第一芯片和所述第二芯片周围以及它们之间；
形成包含所述第一芯片和所述第二芯片的完成的小片；以及
将所述完成的小片与所述框架分离，同时保持所述框架完好。
15.根据权利要求14所述的方法，还包括切割第一半导体晶圆以形成所述第一芯片以及切割第二半导体晶圆以形成所述第二芯片。
16.根据权利要求14所述的方法，还包括将所述第一芯片和所述第二芯片通过导电层耦合在一起。
17.根据权利要求14所述的方法，其中所述框架包括硅衬底。
18.根据权利要求14所述的方法，还包括将所述框架放置在胶带上，所述芯片的具有有源器件的第一表面被布置在所述胶带上。
19.根据权利要求18所述的方法，其中所述多个开口具有锥形侧壁，其中所述多个开口在邻近所述胶带的底部表面处比在所述框架的相对的顶部表面与所述底部表面之间半程的距离处具有更大的直径。
20.根据权利要求14所述的方法，其中所述框架包含具有与所述第一芯片和所述第二芯片的热膨胀系数相同的热膨胀系数的材料。
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US20110095413A1 (en) 2011-04-28
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