CN1777976B - 形成通过加入硅来调整功函数的金属栅极结构的方法 - Google Patents

形成通过加入硅来调整功函数的金属栅极结构的方法 Download PDF

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CN1777976B
CN1777976B CN2004800110330A CN200480011033A CN1777976B CN 1777976 B CN1777976 B CN 1777976B CN 2004800110330 A CN2004800110330 A CN 2004800110330A CN 200480011033 A CN200480011033 A CN 200480011033A CN 1777976 B CN1777976 B CN 1777976B
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silicon
metal
work function
soaking
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C·伍
P·R·贝塞尔
M·V·努
J·N·潘
J·尹
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Abstract

本发明公开了一种形成具有功函数可控的金属栅极(30)的半导体结构的方法，所述方法包括形成前身结构的步骤，所述前身结构具有有源区(12)被沟道所分隔的基片(10)，以及在沟道之上和在介电层(20)之内的临时栅极(16)。去除临时栅极(16)以形成底部和侧壁在介电层(20)之内的凹沟(22)。在凹沟(22)内沉积不含硅的金属层(26)。将硅加入到金属层(26)中并在金属层(26)上沉积金属(28)。通过硅烷处理而获得硅的加入，所述硅烷处理是在沉积金属层(26)之前、之后或既之前又之后进行的。加入到金属层(26)中的硅的数量控制所形成的金属栅极(30)的功函数。

Description

形成通过加入硅来调整功函数的金属栅极结构的方法
技术领域
本发明涉及半导体工艺的领域，更具体地，涉及用替代栅极加工技术来形成金属栅电极。
背景技术
在集成电路(IC)产业中，一般用多晶硅栅电极来形成金属-氧化物-半导体(MOS)晶体管。优选用多晶硅材料作为MOS栅电极是由于其热阻特性(也就是，多晶硅能更好地抵抗后续的高温加工)。多晶硅在高温加工期间的强度(robustness)使得多晶硅可与源极区和漏极区一起在高温下退火。此外，多晶硅阻挡掺杂原子被离子注入到沟道区中的能力是有利的。由于多晶硅阻挡离子注入的潜能，所以多晶硅使得可在完成栅极图案化之后容易地形成自对准的源极和漏极结构。然而，多晶硅栅电极具有某些缺点。例如，多晶硅栅电极是由比大多数金属材料具有较高电阻率的半导体材料形成的。因此，相比于由金属材料所制成的栅极，多晶硅栅电极以低得多的速度工作。为了部分地补偿所述较高的电阻，多晶硅材料时常需要大量且昂贵的硅化物加工，以将它们的工作速度提高至可接受的水平。
产业上需要一种能替代多晶硅栅极器件的金属栅极器件。然而，金属栅极不能抵抗传统的多晶硅栅电极所能抵抗的较高温度和氧化环境。在避免多晶硅栅电极的某些问题的努力中，创造出了替代的镶嵌金属栅极过程(replacement damascene metal gate process)。镶嵌栅极过程使用可消除的栅极(disposable gate)，并且与在传统的加工中一样，是以源极、漏极、间隔物(spacer)、蚀刻终止层和消反射涂层来形成的。将可消除的栅极和电介质蚀刻掉，而暴露出原来的栅极氧化物。然后用金属栅极取代可消除的多晶硅栅极，以获得该金属材料所提供的较低的电阻率。
半导体技术中的一个设计考虑是功函数(work function)，功函数是激发电子越过临界值所需的能量。在硅基片上的多晶硅栅极提供了使得栅极可被充分控制的功函数。然而，与多晶硅栅极相比，用金属作为硅基片上的栅极材料可能会不理想地改变功函数。这降低了栅极的可控制性。
发明内容
需要一种半导体结构和制备该半导体结构的方法，在该半导体结构中栅极由金属制成，但是能用高度可控的方式将功函数调整至所希望的值。
提供了形成半导体结构的方法的本发明实施例可满足上述需求和其它需求，所述方法包括形成前身结构(precursor)的步骤，所述前身结构具有有源区被沟道所分隔的基片以及在沟道之上和在介电层之内的临时栅极(temporary gate)。去除临时栅极以形成底部和侧壁在介电层内的凹沟(recess)。然后在凹沟内沉积不含硅的金属层(non-siliconcontaining metal layer)。在金属层上沉积金属并将硅加入到金属层中。在本发明的某些实施例中，硅的加入包括热硅烷处理(thermal silanetreatment)。该热硅烷处理可包括预浸泡(pre-soak)、后浸泡(post-soak)或预浸泡和后浸泡的结合。在本发明的其它实施例中，热硅烷处理包括对所沉积的不含硅的金属层的等离子处理。等离子处理可结合热浸泡处理。
将硅加入到例如Ta、W、Mo、Ru、Ti和Co的金属层中，对凹沟中金属层的功函数提供了高度的控制。可用许多不同的方式来控制加入到金属层中的硅的数量(amount of silicon)，包括控制硅烷处理的次数。控制所加入的硅的数量的其它方法包括控制硅烷处理时间和控制硅烷处理温度。控制所加入的硅的数量的另一种方法是控制不含硅的金属层的厚度。层愈薄，则加入到金属层中的硅的百分比愈大。
提供了形成金属栅极半导体器件的方法的本发明其它实施例也可满足前述需求，所述方法包括在前身结构上形成金属栅极以及用硅烷热处理金属栅极以可控地调整金属栅极的功函数的步骤。
结合附图来阅读本发明的以下详细说明将使本发明的前述和其它的特征、方面和优点变得更为清楚。
附图说明
图1是依照本发明实施例的半导体结构的前身结构的示意性剖面图。
图2显示去除假栅极(dummy gate)和栅极电介质之后图1的结构。
图3a显示图2的结构依照本发明的某些实施例经历硅烷处理。
图3b显示依照本发明的某些其它实施例在沉积金属层之后的图2的结构。
图4a显示依照本发明的某些实施例在沉积金属层之后的图3a的结构。
图4b显示依照本发明的某些其它实施例在所沉积金属层的硅烷处理期间的图3b的结构。
图5显示依照本发明的实施例在金属层上沉积金属之后的图4a或图4b的结构。
图6显示在平坦化以形成金属栅极之后图5的结构。
图7显示在本发明的替代实施例中的加工步骤。
具体实施方式
本发明说明并解决关于在半导体结构中使用金属栅极的问题。在使用替代金属栅极的传统半导体结构中，由于在硅基片上使用金属，因此功函数从多晶硅栅极改变。本发明提供可调整的功函数，以生成具有特定调整至所希望的功函数值的金属栅极。这是通过以控制的方式进行硅烷处理以将硅加入到诸如钽的金属层中而实现的，所述金属层沉积在镶嵌栅极结构内。因此，本发明的金属栅极技术提供了修正非常小CMOS器件的临界电压的可能性，并且不用进行额外的调整注入。这是有利的，因为随着CMOS沟道长度的迅速按比例缩小(scaling)，沟道注入的自由度大幅降低。
图1是依照本发明实施例制备的半导体结构的前身结构的剖面图。在以下说明中，特征和附图就相对的大小或形状而言并不需精确地表示出，而仅为示意的目的。
在图1中，通过传统的掺杂技术将有源区12形成在硅基片10处。在基片10的表面上提供有栅极氧化物14。在有源区12上形成有硅化物区15。在栅极氧化物14之上提供有作为临时(或“假”)栅极的多晶硅栅极16。
间隔壁18提供在栅极16的侧壁上。间隔壁18可以由任何适当的材料而制成，诸如氮化硅、氧化硅、氮氧化硅或它们的不同层。介电层20提供在基片10之上。将图1的半导体结构通过例如化学机械平坦化(chemical mechanical planarization，CMP)而平坦化，以提供平坦化的上表面。
图1的结构是具有有源区和多晶硅栅极的传统半导体结构。然而，为了提供具有降低的电阻率的栅极，可以如本发明所示，去除多晶硅栅极16并代之以金属栅极。然而，如前所示，使用金属栅极结构会不理想地改变栅极的功函数。在本发明中可通过硅烷处理金属栅极以将功函数调整至期望值而避免这种情况。
在图2中，多晶硅栅极16已从间隔壁18之间的区域去除。图2所示的栅极氧化物14保留在由基片10的上部和间隔壁18形成的侧壁所形成的凹沟22内。在本发明的某些实施例中，去除栅极氧化物14并用高-k栅极介电材料来代替。可用于高-k栅极介电层的特定材料包括例如ZrO2、HfO2、InO2、LaO2、TaO2。可用其它多种的金属氧化物或者可用钙钛矿(perovskites)作为高-k栅极介电材料来代替传统的栅极氧化物。然而，在以下说明中，假设栅极氧化物14没有去除。
图3a和3b显示图2的结构依照本发明的不同实施例在过程的下一步骤中的结构。在图3a中，进行第一硅烷处理。这由图3a中的箭头24所指示。该硅烷处理被认为是预浸泡，并可依照以下参数进行：压力大约为3至6托(torr)；温度在大约250-550℃之间；SiH4的流量在大约400至1000sccm之间，以及处理时间在大约10至60秒之间。
接着图3a的预浸泡硅烷处理，然后在凹沟22内及介电层20之上形成金属层26。可用传统的过程来沉积金属层26，诸如利用物理气相沉积的溅射沉积。金属层26是由诸如Ta、W、Mo、Ru、Ti、TiN、TaN或Co的适当材料制成的。该相对较薄的层可沉积在例如大约至
Figure G2004800110330D00042
之间。
图3a中形成的预浸泡造成图4a的金属层26在沉积期间加入硅(Si)，而使得实际形成的金属层26包含硅。举例而言，接着图3a预浸泡形成之后的金属层26例如可以是TaSi、WSi、MoSi、RuSi、TiSi、TiNSi、TaNSi或CoSi。硅的加入将功函数变至设计者所设定的期望值。这提供了对将形成的金属栅极的功函数的精细调整。
在本发明的替代实施例中，如图3b和图4b所示，在任何硅烷处理之前先沉积金属层26。该金属层26可以与图4a的金属层26采用相同的材料，因此，对于该层提供相同的参考数字指示。然而，图3b中金属层26并没有加入任何的硅。
在图4b中，提供后浸泡或等离子硅烷处理以将硅加入到金属层26中。最终的金属层26因此将包含与图4a的金属层26相同的材料。预浸泡硅烷处理的相同参数可用于后浸泡硅烷处理。用于PECVD室内的硅烷等离子处理的参数如下：压力在大约2至4托之间；温度在大约350℃至450℃之间；RF功率在大约100至250W之间；SiH4流量在大约60至110sccm之间，以及时间在大约5至30秒之间。然而，这些参数仅是举例说明而已，因为可以使用其它的参数而并不会偏离本发明的范围。
在某些实施例中结合了图3a和4b的实施例，而使得过程包括预浸泡以及后浸泡或后等离子处理。改变对金属层26硅烷处理的总次数会改变加入到金属层26中的硅的数量。这具有对金属层26的功函数提供控制的效果，给设计者提供了选择功函数值的灵活性。
图5显示在具有所加入硅的金属层26上沉积另一金属层28之后图4a或4b的结构。金属层28包含与金属层26兼容的材料。例如，金属层28可由钽、或者铜或铜合金制成。可用传统的沉积技术来沉积金属层28，诸如物理气相沉积、化学气相沉积或无电镀沉积(用于铜)。用于金属层28的另一种适当材料是钨(W)并且可通过CVD而沉积。
接着金属层28的沉积，进行诸如化学机械平坦化(CMP)的平坦化过程，以生成包含金属层28和加入有硅的金属层26的金属栅极30。
本发明允许设计者通过控制加入到金属层26中的硅的数量而调整金属栅极30的功函数。例如，可改变硅烷处理的次数。可采用预处理(pre-treatment)，可采用后处理(post-treatment)，或可既采用预处理又采用后处理。处理的次数会影响金属层26中所加入的硅的数量，因此影响金属栅极的功函数。
硅烷处理时间还会影响硅加入的数量。硅烷处理时间愈长，则加入到金属层26中的硅的数量愈大。同样，硅烷处理的处理温度会影响硅加入的数量。温度愈高，则加入硅的数量愈大。本领域的普通技术人员可依据用于获得所希望的功函数的金属层26而改变温度。
另一因素是金属层26的厚度。较薄的金属层26允许将较多的硅加入到金属层26中。这提供了另一个可控制功函数的参数。
在本发明的替代实施例中，如图7所示，提供了形成加入有硅的层的另一种方法。在该方法中，如顺次接着图3b的图7所示，例如用物理气相沉积将硅层27沉积在晶片上。该步骤是用可在市场上购得的标准UHV多室溅射系统而原位(in-situ)进行的。然后，例如用快速热退火(rapid thermal anneal，RTA)而进行短暂的退火步骤。在该短暂的退火期间，温度维持在大约300℃至大约500℃之间。层27中的硅与金属层26反应，但是因为温度维持在硅化作用(silicidation)所需的温度之下，因此并不形成硅化物。在退火将层27中的硅加入到金属层26中之后，继续图5中沉积金属层28的制备过程，然后在图6中予以平坦化。
虽然已详细说明并示意了本发明，但是应清楚地了解，所述实施例仅仅是作为示意及例子，而并非要限制本发明，本发明的范围仅由所附的权利要求的条款而限定。

Claims (11)

1.一种形成半导体结构的方法，包括以下步骤：
形成前身结构，所述前身结构具有有源区(12)被沟道所分隔的基片(10)，以及在所述沟道之上和在介电层(20)之内的临时栅极(16)，其中该介电层(20)是提供在该基片(10)之上；
去除所述临时栅极(16)以形成底部和侧壁在所述介电层(20)之内的凹沟(22)；
用硅烷预浸泡所述凹沟(22)；
在所述凹沟(22)内沉积不含硅的金属层(26)；
将硅可控地加入到所述金属层(26)中，加入到所述金属层(26)中的
硅的数量可控地调整所述半导体结构的功函数；以及
在所述金属层(26)上沉积金属(28)。
2.如权利要求1所述的方法，其中，所述加入硅的步骤进一步包括在沉积所述不含硅的金属层(26)之后用硅烷后浸泡。
3.如权利要求1所述的方法，其中，所述加入硅的步骤包括在沉积所述不含硅的金属层(26)之后的等离子硅烷处理。
4.如前述权利要求中任一权利要求所述的方法，其中，加入到所述不含硅的金属层(26)中的硅的数量依赖于在沉积所述不含硅的金属层(26)的步骤之前或之后的各个预浸泡、后浸泡和等离子硅烷处理中的任一个或全部。
5.如权利要求1所述的方法，其中，所述不含硅的金属层(26)包含Ta、W、Mo、Ru、Ti、TiN、TaN和Co中的一种。
6.一种形成金属栅极半导体器件的方法，包括以下步骤：
提供前身结构，其中所述前身结构具有有源区(12)被沟道所分隔的基片(10)，以及在所述沟道之上和在介电层(20)之内的临时栅极(16)，而所述临时栅极(16)被去除以形成底部和侧壁在所述介电层(20)之内的凹沟(22)；
用硅烷对所述前身结构进行热处理；以及
在所述前身结构上形成包括金属层(26)的金属栅极(30)，加入到所述金属层中的硅的数量被改变以可控地调整所述金属栅极(30)的功函数。
7.如权利要求6所述的方法，其中，所述热处理的步骤包括热浸泡。
8.如权利要求7所述的方法，进一步包括控制热浸泡处理时间，以控制加入到所述金属栅极(30)中的硅的数量。
9.如权利要求8所述的方法，进一步包括在所述热浸泡期间控制温度，以控制加入到所述金属栅极(30)中的硅的数量。
10.如权利要求9所述的方法，其中，所述热处理的步骤包括等离子处理所述金属层(26)。
11.如权利要求10所述的方法，其中，所述金属栅极(30)包括由Ta、W、Mo、Ru、Ti、TiN、TaN和Co中的一种所组成的金属层(26)，以及其中，所述金属层(26)的所述热处理将硅加入到所述金属层(26)中。
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Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7332421B2 (en) * 2003-12-31 2008-02-19 Dongbu Electronics Co., Ltd. Method of fabricating gate electrode of semiconductor device
US6921691B1 (en) 2004-03-18 2005-07-26 Infineon Technologies Ag Transistor with dopant-bearing metal in source and drain
US7226826B2 (en) * 2004-04-16 2007-06-05 Texas Instruments Incorporated Semiconductor device having multiple work functions and method of manufacture therefor
US8399934B2 (en) 2004-12-20 2013-03-19 Infineon Technologies Ag Transistor device
US7592678B2 (en) 2004-06-17 2009-09-22 Infineon Technologies Ag CMOS transistors with dual high-k gate dielectric and methods of manufacture thereof
US8178902B2 (en) 2004-06-17 2012-05-15 Infineon Technologies Ag CMOS transistor with dual high-k gate dielectric and method of manufacture thereof
US7344934B2 (en) * 2004-12-06 2008-03-18 Infineon Technologies Ag CMOS transistor and method of manufacture thereof
US7253050B2 (en) 2004-12-20 2007-08-07 Infineon Technologies Ag Transistor device and method of manufacture thereof
US7160781B2 (en) 2005-03-21 2007-01-09 Infineon Technologies Ag Transistor device and methods of manufacture thereof
US7361538B2 (en) 2005-04-14 2008-04-22 Infineon Technologies Ag Transistors and methods of manufacture thereof
US8188551B2 (en) 2005-09-30 2012-05-29 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
US7462538B2 (en) 2005-11-15 2008-12-09 Infineon Technologies Ag Methods of manufacturing multiple gate CMOS transistors having different gate dielectric materials
US7495290B2 (en) 2005-12-14 2009-02-24 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
US7510943B2 (en) 2005-12-16 2009-03-31 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
KR101011867B1 (ko) 2006-06-21 2011-01-31 도쿄엘렉트론가부시키가이샤 ＴａＳｉＮ막의 성막 방법
US8796084B2 (en) * 2007-09-28 2014-08-05 Taiwan Semiconductor Manufacturing Company Ltd. Method for removing hard masks on gates in semiconductor manufacturing process
US7781321B2 (en) 2008-05-09 2010-08-24 International Business Machines Corporation Electroless metal deposition for dual work function
US8324090B2 (en) * 2008-08-28 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method to improve dielectric quality in high-k metal gate technology
US8012817B2 (en) 2008-09-26 2011-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor performance improving method with metal gate
US8124515B2 (en) * 2009-05-20 2012-02-28 Globalfoundries Inc. Gate etch optimization through silicon dopant profile change
US8232148B2 (en) * 2010-03-04 2012-07-31 International Business Machines Corporation Structure and method to make replacement metal gate and contact metal
US8283734B2 (en) * 2010-04-09 2012-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-threshold voltage device and method of making same
CN102339752A (zh) * 2010-07-14 2012-02-01 中国科学院微电子研究所 一种基于栅极替代工艺的制造半导体器件的方法
US8592266B2 (en) 2010-10-27 2013-11-26 International Business Machines Corporation Replacement gate MOSFET with a high performance gate electrode
US20120280288A1 (en) 2011-05-04 2012-11-08 International Business Machines Corporation Inversion thickness reduction in high-k gate stacks formed by replacement gate processes
CN103187448B (zh) * 2011-12-31 2016-03-16 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US11043386B2 (en) 2012-10-26 2021-06-22 Applied Materials, Inc. Enhanced spatial ALD of metals through controlled precursor mixing
US9230815B2 (en) 2012-10-26 2016-01-05 Appled Materials, Inc. Methods for depositing fluorine/carbon-free conformal tungsten
US9514983B2 (en) * 2012-12-28 2016-12-06 Intel Corporation Cobalt based interconnects and methods of fabrication thereof
US8846550B1 (en) * 2013-03-14 2014-09-30 Asm Ip Holding B.V. Silane or borane treatment of metal thin films
TWI582839B (zh) * 2013-04-17 2017-05-11 聯華電子股份有限公司 金屬閘極結構及其製作方法
EP2802003B1 (en) * 2013-05-07 2019-08-28 IMEC vzw Method for providing a gate metal layer of a transistor device
US9324710B2 (en) 2014-02-24 2016-04-26 International Business Machines Corporation Very planar gate cut post replacement gate process
KR102396085B1 (ko) 2015-10-28 2022-05-12 에스케이하이닉스 주식회사 매립금속게이트구조를 구비한 반도체장치 및 그 제조 방법, 그를 구비한 메모리셀, 그를 구비한 전자장치
US9741577B2 (en) 2015-12-02 2017-08-22 International Business Machines Corporation Metal reflow for middle of line contacts
KR102553260B1 (ko) 2016-08-03 2023-07-07 삼성전자 주식회사 집적회로 소자 및 그 제조 방법
US9960078B1 (en) 2017-03-23 2018-05-01 International Business Machines Corporation Reflow interconnect using Ru
CN109087887B (zh) * 2017-06-14 2021-04-02 中芯国际集成电路制造(北京)有限公司 半导体结构及其形成方法
US10672649B2 (en) 2017-11-08 2020-06-02 International Business Machines Corporation Advanced BEOL interconnect architecture
US10541199B2 (en) 2017-11-29 2020-01-21 International Business Machines Corporation BEOL integration with advanced interconnects
KR102495082B1 (ko) 2018-06-12 2023-02-01 삼성전자주식회사 반도체 장치
US11342225B2 (en) 2019-07-31 2022-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier-free approach for forming contact plugs
FR3104173B1 (fr) 2019-12-06 2023-07-21 Centre Nat Rech Scient : Procédé de production de nanoclusters de silicium et/ou germanium présentant un moment dipolaire électrique et/ou magnétique permanent
US11640983B2 (en) 2020-08-14 2023-05-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1349247A (zh) * 2000-10-13 2002-05-15 海力士半导体有限公司 金属栅极形成方法
US6420236B1 (en) * 1999-08-24 2002-07-16 Texas Instruments Incorporated Hydrogen treatment for threshold voltage shift of metal gate MOSFET devices

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6933021B2 (en) 1995-07-06 2005-08-23 Applied Materials, Inc. Method of TiSiN deposition using a chemical vapor deposition (CVD) process
US6017818A (en) 1996-01-22 2000-01-25 Texas Instruments Incorporated Process for fabricating conformal Ti-Si-N and Ti-B-N based barrier films with low defect density
JP3592451B2 (ja) * 1996-08-13 2004-11-24 富士通株式会社 半導体装置の製造方法
US6297152B1 (en) * 1996-12-12 2001-10-02 Applied Materials, Inc. CVD process for DCS-based tungsten silicide
US6528426B1 (en) 1998-10-16 2003-03-04 Texas Instruments Incorporated Integrated circuit interconnect and method
JP2001077355A (ja) 1999-08-13 2001-03-23 Texas Instr Inc <Ti> トランジスタを形成する方法
US6436825B1 (en) 2000-04-03 2002-08-20 Taiwan Semiconductor Manufacturing Company Method of copper barrier layer formation
US6271136B1 (en) 2000-04-04 2001-08-07 Taiwan Semiconductor Manufacturing Company Multi-step plasma process for forming TiSiN barrier
JP2002118175A (ja) * 2000-10-05 2002-04-19 Toshiba Corp 半導体装置及びその製造方法
US6436840B1 (en) * 2000-10-19 2002-08-20 Advanced Micro Devices, Inc. Metal gate with CVD amorphous silicon layer and a barrier layer for CMOS devices and method of making with a replacement gate process
US6518113B1 (en) * 2001-02-06 2003-02-11 Advanced Micro Devices, Inc. Doping of thin amorphous silicon work function control layers of MOS gate electrodes
US6518106B2 (en) * 2001-05-26 2003-02-11 Motorola, Inc. Semiconductor device and a method therefor
US6475908B1 (en) * 2001-10-18 2002-11-05 Chartered Semiconductor Manufacturing Ltd. Dual metal gate process: metals and their silicides
US6423619B1 (en) 2001-11-30 2002-07-23 Motorola, Inc. Transistor metal gate structure that minimizes non-planarity effects and method of formation
US6727560B1 (en) * 2003-02-10 2004-04-27 Advanced Micro Devices, Inc. Engineered metal gate electrode
TWI397765B (zh) * 2004-07-26 2013-06-01 Pentax Ricoh Imaging Co Ltd 平台設備及使用該平台設備的相機震動校正設備

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420236B1 (en) * 1999-08-24 2002-07-16 Texas Instruments Incorporated Hydrogen treatment for threshold voltage shift of metal gate MOSFET devices
CN1349247A (zh) * 2000-10-13 2002-05-15 海力士半导体有限公司 金属栅极形成方法

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