CN1776904A - 安装基板及电子机器 - Google Patents
安装基板及电子机器 Download PDFInfo
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- CN1776904A CN1776904A CNA2005101254078A CN200510125407A CN1776904A CN 1776904 A CN1776904 A CN 1776904A CN A2005101254078 A CNA2005101254078 A CN A2005101254078A CN 200510125407 A CN200510125407 A CN 200510125407A CN 1776904 A CN1776904 A CN 1776904A
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Abstract
本安装基板,包括:在电子器件上形成的多个器件电极,在基板上形成的多个基板电极,采用液滴喷出法形成的、将多个器件电极和多个基板电极电连接的多个连接布线。而且,多个基板电极,排列成交错状。
Description
技术领域
本发明涉及安装基板及电子机器。
背景技术
在现有技术的将半导体芯片(IC芯片)等电子器件安装到基板上的技术中,为了将电子器件的一个面上的端子电极(器件电极)与基板的布线图案电性连接,大多采用被称作“引线接合法(wire bonding)”的手法(例如,参照日本国特开2004-221257号公报)。
此外,作为上述电性连接的相关技术,有在连接对象的端子之间夹持导电性部件的手法(例如,参照日本国特开2000-216330号公报)。另外,作为同样的手法,还有在相对配置的电极之间,配置包含各向异性导电粒子的部件(各向异性导电薄膜(ACF:An-isotropic Conductive Film)及各向异性导电糊精(ACP:An-isotropic Conductive Paste))的技术(例如,参照日本国特开2000-068694号公报)。
此外,关于上述电性连接,有人提出使用液滴喷出法的技术(例如,参照日本国特开2004-281539号公报)。在该手法中,将导电性材料作为液滴状配置在基板上,使其硬化后形成连接布线。
采用上述液滴喷出法形成连接布线的技术,具有在形成布线的过程中给予电子器件的应力比较少的优点。进而,在上述技术中,因为可以实现高精度的材料配置,所以有利于布线的窄间距化(细密化)。
可是,尽管将电子器件的端子电极窄间距化,但基板的布线(基板电极)却往往不能与之相适应。就是说,与电子器件的电极相比,基板的电极受到各种制约,存在着排列间距的下限值较大的倾向。这就需要使布线迂回等,容易扩大基板上的布线区域,妨碍基板小型化。
发明内容
本发明就是针对上述情况研制的,其目的在于提供可以与器件电极的窄间距化对应的而且适应小型化要求的安装基板。
本发明的安装基板,是安装电子器件的基板,其特征在于,包括:在所述电子器件上形成的多个器件电极,在所述基板上形成的多个基板电极,采用液滴喷出法形成的、将所述多个器件电极和所述多个基板电极电连接的多个连接布线;所述多个基板电极,排列成交错状。
在这里,所述多个基板电极,既可以配置在所述基板中的大致同一个平面内,也可以在所述基板中分成非同一个平面的多个面后配置。
上述的安装基板,采用交错状排列后,相邻的2个基板电极的间隔就变的比较宽。因此,可以使基板电极的排列间距与器件电极的排列间距大体一致。而且使基板电极的排列间距与器件电极的排列间距大体一致后,可以减少布线的迂回,有利于基板中的布线区域的缩小化。
就是说,该安装基板能够令人满意地与器件电极的窄间距化对应,而且适合于小型化。
在上述的安装基板中,在所述多个器件电极和所述多个基板电极之间,形成具有斜面部的斜面部件,所述斜面部件的斜面部的长度,能够按照所述多个器件电极和所述多个基板电极之间的距离变化。
这时,例如,所述斜面部件的整体形状,可以包含梳形。
采用这种结构后,即使在器件电极和基板电极之间有阶差时,也能利用斜面部件使用液滴喷出法切实形成上述连接布线。就是说,采用液滴喷出法向物体的大致垂直的面配置材料,比较困难。可是,覆盖物体的大致垂直的面地配置斜面部件,再在该斜面部件的斜面部上配置材料后,就可以采用液滴喷出法容易而且切实地形成布线。
另外,斜面部件的斜面部的长度,按照器件电极和基板电极之间的距离变化后,对于交错排列的多个基板电极的每一个,都能采用液滴喷出法切实形成上述连接布线。
本发明的其它安装基板,是安装电子器件的基板,其特征在于,包括:在所述电子器件上形成的多个器件电极,在所述基板上形成的多个基板电极,采用液滴喷出法形成的、将所述多个器件电极和所述多个基板电极电连接的多个连接布线;所述多个基板电极,在所述基板中分成非同一个平面的多个面后配置。
在上述的安装基板中,通过将多个基板电极分成非同一个平面的多个面后配置,从而使相邻的2个基板电极的间隔变的比较宽。因此,可以使基板电极的排列间距与器件电极的排列间距大体一致。而且使基板电极的排列间距与器件电极的排列间距大体一致后,可以减少布线的迂回,有利于基板中的布线区域的缩小化。
就是说,该安装基板能够令人满意地与器件电极的窄间距化对应,而且适合于小型化。
在上述的安装基板中,所述多个面,包含在所述基板中安装所述电子器件的安装面及其背面。
这时,在所述基板上,设置将所述连接布线从所述安装面引导到所述背面的贯通孔;在所述基板的背面中,所述基板电极被配置成堵住所述贯通孔中的所述背面一侧的开口。
采用这种结构后,虽然布线形成区域包含物体的大致垂直面,但是基板的贯通孔中的背面侧的开口却被基板电极堵塞。因此,填埋贯通孔地配置连接布线的形成材料后,就能够采用液滴喷出法,切实形成所述连接布线。
本发明的电子机器,其特征在于:具备前文所述的安装基板。
采用该电子机器后,通过安装基板的小型化,从而能够实现小型化、轻量化。
附图说明
图1是表示本发明的安装基板的一种实施方式的局部平面图。
图2是图1所示的A-A剖面图。
图3是图1所示的B-B剖面图。
图4是表示实施方式涉及的安装基板的制造方法的局部平面图。
图5是表示实施方式涉及的安装基板的制造方法的局部平面图。
图6是表示实施方式涉及的安装基板的制造方法的局部平面图。
图7是表示实施方式涉及的安装基板的制造方法的局部平面图。
图8是表示实施方式涉及的安装基板的制造方法的局部平面图。
图9A是液滴喷出头的局部剖面图,图9B是液滴喷出头的局部剖面图。
图10A是表示安装基板的其它实施方式的局部平面图,图10B是图10A所示的C-C剖面图。
图11A是表示安装基板的其它实施方式的局部平面图,图11B是图11A所示的C-C剖面图。
图12A是表示电子机器的一个示例的立体结构图,图12B是具有该显示部的立体结构图。
具体实施方式
下面,参照附图,讲述本发明的实施方式。
图1是表示本发明的安装基板的一种实施方式的局部平面图。
如图1所示,安装基板10,具备在基板1上、面朝上接合的芯片部件(电子器件)2,将芯片部件2的电极(器件电极7)与基板1的电极(基板电极4)电连接的结构。
基板1是形成布线图案的多层或单层的布线基板,基体既可以呈刚性,也可以呈柔软性。在布线图案中,形成多个电极端子(基板电极4)。该多个基板电极4,除了镀覆法及溅射法等之外,还能够采用液滴喷出法形成。
在本例中,多个基板电极4,在俯视图中大体分别呈长方形。各基板电极4在俯视图中的长度方向(X方向),是离开器件电极7的方向,其宽度方向(Y方向),则是与上述离开方向正交的方向。
并且,多个基板电极4交错排列。就是说,多个基板电极4以所定的间距(P1)大致等间隔地在Y方向(各电极4的宽度方向)上排列,再沿着该排列方向,使有关X方向(各电极4的长度方向)的位置一个个交替错开地排列。换言之,多个基板电极4具有在X方向互相离开的2个电极组(基板电极4A…、基板电极4B…)。基板电极4A…的组和基板电极4B…的组,在Y方向上具有错开所定间距(P1)的关系。
作为芯片部件2,可以广泛使用一面具有外部连接端子的电子器件。就是说芯片部件2,既可以是不具备集成电路的半导体部件等的有源部件,也可以是无源部件(电阻器、电容器、电感器等)。
在芯片部件2的端子面2a上,排列形成多个电极端子(器件电极7)。这些器件电极7,例如在由从芯片部件2内的集成电路(未图示)引出的由铝合金构成的基层(未图示)上,按照Ni、Au的顺序镀覆后形成。此外,在器件电极7中,成为实质性的接合层的最外层(最上层),除了Au之外,例如还可以是Ag、Cu、Sn、In,进而还可以采用由它们的多个构成的层叠结构。
芯片部件2的电极7和基板1的电极4,通过多个连接布线11、12做媒介,被电连接。在这里,多个连接布线11、12中,连接布线11的一端与芯片部件2的一个电极4连接,另一端与基板1的一个基板电极4A连接。另一方面,连接布线12的一端与芯片部件2的一个电极4连接,另一端与基板1的一个基板电极4B连接。在本例中,这些连接布线11、12,采用液滴喷出法形成。
就是说,连接布线11、12是分别在器件电极7和基板电极4A、4B之间的线状区域,连续性地配置液滴状的布线材料,再使其硬化后形成的。在芯片部件2的周边,配置斜面部件15、16。在该斜面部件15、16的倾斜面上,形成连接布线11、12。由于存在斜面部件15、16,所以即使是在器件电极7和基板电极4A、4B之间存在阶差的结构,也能采用液滴喷出法切实地形成布线。此外,在本例中,按照多个基板电极4的交错状排列,连接布线11、12和基板电极4A、4B的多个连接部位,也是交错状排列。
图2是图1所示的A-A剖面图,图3是图1所示的B-B剖面图。
如图2及图3所示,芯片部件2通过由热硬化性的绝缘性树脂等构成的粘接层6做媒介,搭载在基板1上。在本例中,该芯片部件2是50μm以下的厚度的极薄的元件。该芯片部件2,将有源面——端子面2a朝着与基板1相反的一侧的状态安装(即面朝上接合)。作为粘接层6,可以使用导电性的粘接剂和绝缘性的粘接剂中的任何一个。作为粘接层6,使用导电性的粘接剂时,可以在芯片安装区域的布线图案和设置在芯片部件2的背面的电极的导电连接中利用该粘接层6。作为绝缘性的粘接剂,可以使用DAF(带模膜:die attach film)。另外,在粘接层6中,还可以使用使导电性粒子分散到绝缘矩阵中的各向异性导电糊精(ACP)及各向异性导电薄膜(ACF)。
如图2所示,与基板电极4A连接的连接布线11,沿着斜面部件15的表面形成。就是说,在芯片部件2的侧面部位,形成从端子面2a向外侧延伸、到达基板1的安装面1a(基板电极4A)上的具有斜面部15a的斜面部件15。经由该斜面部件15的斜面部15a的表面,形成连接器件电极7和基板电极4A的连接布线11。斜面部件15,起缓和芯片部件2的端子面2a和基板1的安装面1a的阶差的作用,进而还起防止采用液滴喷出法形成的连接布线11断线等的作用。就是说,在液滴喷出法中,在物体的大致垂直的面上配置材料比较困难。可是,覆盖物体的大致垂直的面地配置斜面部件15,再在该斜面部件15的斜面部15a上配置材料后,采用液滴喷出法就能够容易而且切实地形成布线。
另一方面,如图3所示,与基板电极4B连接的连接布线12,沿着斜面部件15及斜面部件16的表面形成。就是说,在芯片部件2的侧面部,在上述斜面部件15的基础上,还具有延长斜面部件15的斜面部15a的斜面部16a的斜面部件16。经由斜面部件15及斜面部件16的各斜面部15a、16a的表面,形成连接器件电极7和基板电极4B的连接布线12。在本例中,斜面部件16的斜面部16a,覆盖斜面部件15的斜面部15a的一部分,向离开芯片部件2的方向延伸,到达基板1的安装面1a(基板电极4B)之上地形成。在本例中,在形成斜面部件15之后,再形成斜面部件16。但并不局限于此,例如可以同时形成斜面部件15和斜面部件16。
斜面部件15、16,例如,可以采用分配器等液体材料涂敷单元,将聚酰亚胺树脂、硅变性聚酰亚胺树脂、环氧树脂、硅变性环氧树脂、苯并环丁烯(BCB:benzocyclobutene)、聚苯并恶唑(PBO:polybenzoxazole)等树脂材料喷到柔软基板1上后形成。或者,斜面部件15、16可以通过固定干薄膜后形成。
返回图1,将斜面部件15和斜面部件16合在一起的整体形状,在俯视图上呈梳状。就是说,多个基板电极4中,对于位于离芯片部件2(器件电极7)较远的位置的基板电极4B…每一个而言,从斜面部件15延伸,形成斜面部件16。该斜面部件16的延长部分,突出于斜面部件15。而且,对于位于离器件电极7(芯片部件2)较近的位置的基板电极4A而言,形成斜面部件15的比较短的斜面部。另一方面,对于位于离器件电极7(芯片部件2)较远的位置的基板电极4B而言,形成斜面部件15及斜面部件16的比较长的斜面部。就是说,斜面部件15、16的斜面部的长度,按照一个器件电极7和与之对应的一个基板电极4之间的距离变化,这样,直到各基板电极4的附近,形成阶差比较少的区域。其结果,对于交错状排列的每一个基板电极4,都能采用液滴喷出法切实形成连接布线11、12。
在这里,在本例的安装基板10中,由于多个基板电极4交错状排列,所以可以使相邻的2个基板电极之间的间隔变得比较大。就是说,多个基板电极4被分作在X方向上交替分离的2个电极组(基板电极4A…、基板电极4B…)后配置。在各组中相邻的基板电极4A…、4B…的间隔,是基板电极4的整体的排列间距的2倍(2×P1)。
这样,在本例的安装基板10中,利用交替状排列,使相邻的2个基板电极之间的间隔变得比较大。因此,可以使基板电极4的整体的排列间距(P1)与器件电极7的排列间距(P2)对应。在本例中,基板电极4的整体的排列间距(P1)和器件电极7的排列间距(P2)相同(例如40μm)。基板电极4的整体的排列间距(P1)和器件电极7的排列间距(P2)相同后,可以减少布线的迂回等,缩短布线路线,缩小基板1中的布线区域。
此外,安装基板10可以采用具有外部端子的BGA(Ball Grid Array)型的封装及CSP(Chip Size Package)等形态构成,或者安装基板10还可以采用不设置外部端子,使布线图案的一部分成为和外部进行电连接的电连接部的LGA(Land Grid Array)型的封装。
另外,在安装基板10上安装的芯片部件2,可以被密封材料密封。设置密封材料时,至少将器件电极7和连接布线11、12的电连接部与基板电极4和连接布线11、12的电连接部气密性地密封。另外,还可以采用将整个芯片部件2用密封材料密封的结构。
下面,参照图4~图8,讲述将芯片部件2安装到上述基板1上的方法。
本例的安装方法,包括将芯片部件2放置到基板1上的放置工序(图4)、形成斜面部件15、16的斜面部件形成工序(图5、图6)和采用液滴喷出法形成连接布线11、12的连接布线形成工序(图7、图8)。
<放置工序>
首先,如图4所示,将芯片部件2放置到形成所定的布线图案及导体图案的基板1上。例如,使用具备与控制部连接的照相机及真空吸盘(均未图示)的装置,根据用照相机观察芯片部件2的位置的结果,将芯片部件2安装到基板1上。此外,在基板1上,许多基板电极4(4A、4B),以交错状排列的形态形成。另外,在芯片部件2的端子面2a上,形成许多端子电极(器件电极7)。
芯片部件2通过涂敷在其背面或基板1上的粘接剂做媒介,被固定到基板1上。在粘接层6中,如前所述,可以使用DAF和树脂制粘接剂。在使芯片部件2与基板1粘接的状态下,对芯片部件2进行位置调整时,最好采用未硬化的树脂制粘接剂,以便使芯片部件2容易移动。
<斜面部件形成工序>
接着,如图5所示,形成与芯片部件2的侧面部位相接的斜面部件15。该斜面部件15,例如,可以采用分配器等液体材料涂敷单元,将聚酰亚胺树脂、硅变性聚酰亚胺树脂、环氧树脂、硅变性环氧树脂、苯并环丁烯(BCB:benzocyclobutene)、聚苯并恶唑(PBO:polybenzoxazole)等树脂材料喷到柔软基板1上后形成。或者还可以通过固定干薄膜后形成。斜面部件15,从芯片部件2的侧面,朝着外侧薄薄地形成(参照图2),在其表面,形成倾斜面。斜面部件15的一部分还可以延伸到芯片部件2的上面。
然后,如图6所示,覆盖斜面部件15的一部分地形成斜面部件16。斜面部件16从斜面部件15的端部附近,朝着电极4B薄薄地形成,以便填埋斜面部件15和许多电极4B的各自之间的区域(参照图3)。在其表面,形成倾斜面。斜面部件16的材料及形成方法,与上述的斜面部件15一样。这样,将斜面部件15和斜面部件16结合而成的整体形状,就包含俯视图的梳状。
<连接布线形成工序>
然后,如图7所示,形成直线状的、连接许多器件电极7和许多基板电极4的连接布线11。连接布线11,从芯片部件2的各器件电极7起,通过斜面部件15的斜面,到达各基板电极4之上后形成。具体地说,将包含金属微粒的液状体配置在器件电极7和基板电极4之间的线状区域,然后经过干燥工序、烧成工序,作成金属布线。
在本例中,在形成该连接布线11之际,采用液滴喷出法,利用喷出头,选择配置使导电性微粒分散到媒质中的液体材料。作为液滴喷出法,可以采用喷墨法及分配器法等。特别是喷墨法,由于能够在所需的位置,配置所需量的液态材料,所以是首选的方法,在本例中,采用喷墨法。
在这里,参照图9讲述采用喷墨法进行喷出而能够适当使用的液滴喷出头(喷墨头)。
如图9A所示,液滴喷出头134,例如具有不锈钢制的喷嘴板112和振动板113,通过隔离部件(容器挡板)114做媒介,将两者接合而成。在喷嘴板112和振动板113之间,利用隔离部件114形成多个空间115和贮液腔116。各空间115和贮液腔116的内部,装满液态材料。通过供给口117做媒介,将各空间115和贮液腔116连通。另外,在喷嘴板112中,以纵横排列的状态形成许多旨在从空间115喷射液态材料的喷嘴孔118。另一方面,在振动板113上,形成旨在向贮液腔116供给液态材料的孔119。
另外,在和与振动板113的空间115相对的面相反的面上,如图9B所示,与压电元件120接合。该压电元件120,位于一对电极121之间。一通电后,压电元件120就向外侧突出地挠曲。与压电元件120接合的振动板113,和压电元件120成为一体同时向外侧突出地挠曲。这样,空间115的容积就增大。其结果,相当于空间115内增大的容积部分的液态材料,就通过供给口117做媒介,从贮液腔116流入。另外,从这种状态解除向压电元件120的通电后,压电元件120和振动板113都返回原来的形状,空间115也返回原来的容积。其结果,空间115内部的液态材料的压力上升,从喷嘴孔118朝着基板喷出液态材料(液态体)的液滴122。
作为喷出的液态体,使用将金、银、铜、钯、镍等金属微粒分散到分散液中而成的材料。关于金属微粒,为了提高其分散性,可以使用在其表面涂敷有机物等的材料。作为向金属微粒的表面涂敷的材料,可以列举例如引发立体障碍及静电排斥之类的聚合物。另外,金属微粒的粒径最好在5nm以上(在本说明书中“以上”、“以下”均包含本数)、0.1μm以下。如果大于0.1μm,喷出头的喷嘴就容易堵塞,难以采用喷墨法进行喷出。另外,如果小于5nm,涂敷材料与金属微粒的体积比就要增大,得到的膜中的有机物的比例就会过多。
作为使金属微粒分散的分散液,最好是在室温中的蒸气压为0.001mmHg以上、200mmHg以下(约0.113Pa以上、26600Pa以下)。蒸气压高于200mmHg时,在喷出后分散液急剧蒸发,难以形成良好的膜(布线膜)。
另外,分散液的蒸气压,最好为0.001mmHg以上、50mmHg以下(约0.113Pa以上、6650Pa以下)。蒸气压高于50mmHg时,在用喷墨法(液滴喷出法)喷出液滴之际,由于干燥容易引起喷嘴堵塞,难以稳定地喷出。另一方面,在室温中的蒸气压低于0.001mmHg的分散液,干燥缓慢,分散液容易残留到膜中,在后道工序的加热处理后难以获得良好的导电膜(布线)。
作为使用的分散剂,是能够将所述金属微粒分散的物质,只要是不引起凝聚的物质即可,没有特别的限定。作为这种分散剂,除了水之外,还可以列举:甲醇、乙醇、丙醇、丁醇等酒精类,n-庚烷、n-辛烷、癸烷、十四烷、萘烷、甲苯、二甲苯、甲基异丙基苯、暗媒、茚、双戊烯、四氢化萘、十氢化萘、环己基苯等碳氢化合物,或乙二醇、二甲醚、乙二醇二乙醚、乙二醇甲基乙基醚、二甘醇二乙醚、二甘醇甲基乙基醚、甲氧基乙烷、双(2一甲氧基)乙醇、P一二恶烷等乙醇类化合物,以及碳酸丙烯脂、r一丁内脂、N一甲基一吡咯烷酮、二甲基甲酰胺、二甲亚砜、环己酮等极性化合物。其中,在微粒的分散性和分散液的稳定性或者在液滴喷出法中使用的容易程度方面上说,最好使用水、酒精类、碳氢化合物、乙醇类化合物。作为更理想的分散剂,可以列举水、碳氢化合物。这些分散液,既可以单独使用,也可以作为2种以上的混合物使用。
将所述金属微粒分散到分散液中的分散质的浓度即金属微粒浓度,在1质量%以上、80质量%以下,可以按照所需的金属布线的膜厚调整。小于1质量%时,在以后的采用加热的烧成处理中,就需要很长的时间。超过80质量%后,容易引起凝聚,难以获得均匀的膜。
将所述金属微粒分散到分散液中后构成的液态材料的表面张力,最好在0.02N/m以上0.07N/m以下的范围内。采用液滴喷出法,喷出液态材料之际,表面张力小于0.02N/m后,该液态材料对于喷嘴面的湿润性就要增大,所以容易出现飞行弯曲。表面张力超过0.07N/m后,喷嘴前端的弯液面的形状就不稳定,所以难以控制喷出量及喷出时刻。
上述液态材料的粘度,最好在1mPa·s以上50mPa·s以下。采用液滴喷出法喷出之际,如果粘度比1mPa·s小时,喷嘴的周边部位就容易被墨水(液态材料)污染。另外,如果粘度比50mPa·s大时,喷嘴堵塞的频度就要增大,难以圆滑地喷出液滴。
液态材料的配置结束后,为了除去配置在基板1上的液态材料包含的分散剂,进行干燥处理。该干燥处理,例如除了采用将基板1加热的通常的热板及电炉等进行处理外,还可以采用灯泡退火进行。作为灯泡退火使用的光的光源,没有特别限定,可以将红外线灯泡、氙灯泡、YAG激光器、氩激光器、二氧化碳激光器、XeF、XeCl、XeBr、KrF、KrCl、ArF、ArCl等受激准分子激光器作为光源使用。这些光源,通常使用的是输出10W以上5000W以下的范围的产品。在本实施方式中,灯泡退火使用的光的光源,例如是100W以上1000W以下的范围。
为了提高基板1上的干燥膜(导电微粒的集合体)的导电性,继上述干燥处理之后,实施由加热处理或光照射处理构成的烧成工序。通过该烧成工序,能够更加切实地除去分散剂。另外,在所述干燥体包含金属有机盐时,通过热分解,可以使分散剂变成金属。进而,在导电微粒被涂敷材料覆盖时,通过烧成工序,能够除去该涂敷材料。
上述的加热处理及/或光照射处理,通常在大气中进行,但根据需要,也可以在氮、氩、氦等惰性气体介质中进行。热处理及/或光处理的处理温度,可考虑分散剂的沸点(蒸气压)、气体介质的种类及压力、微粒的分散性及氧化性等热动态、金属有机盐的热及光学性的分解动态以及基材的耐热温度等适当决定。
然后,如图8所示,形成直线状的、连接许多器件电极7和许多基板电极4B的连接布线12。连接布线12,从芯片部件2的各器件电极7起,通过斜面部件15及斜面部件16的斜面,到达各基板电极4B之上后形成。连接布线12的形成材料及形成方法,与上述的连接布线11一样。
经过以上工序后,可以将芯片部件2安装到基板1上。此外,在安装的芯片部件2上,可以通过转移模型及浇注封装形成密封部件。
图10A是表示安装基板的其它实施方式的局部平面图,图10B是图10A所示的C-C剖面图。此外,在图10中,对具有和图1~图3所示的安装基板10相同功能的构成要素,赋予相同的符号,省略或简化其说明。
如图10A所示,安装基板20具有采用面朝上接合法将芯片部件2安装到基板1上,使芯片部件2的电极(器件电极7)与基板1的电极(基板电极4)电连接的结构。
在本例中,多个基板电极4分别交替地配置在基板1中的非同一个平面的安装面1a及其背面1b上(参照图10B)。就是说,多个基板电极4,在Y方向(各电极4的宽度方向)上,以所定的间距(P3)大致等间隔地排列配置的同时,还沿着其排列方向,一个个地分别交替地配置在基板1中的安装面1a和背面1b上。换言之,多个基板电极4具有分别配置在基板1的两面的两个电极组(基板电极4A…、基板电极4C…)。基板电极4A…的组和基板电极4C…的组,具有在X方向上互相分离、而且在Y方向上互相错开所定间距(P3)的位置关系。
芯片部件2的电极7和基板1的电极4,通过多个连接布线11、13做媒介被电连接。多个连接布线11、13中,连接布线11的一端与芯片部件2的一个电极4连接,另一端与基板1的安装面1a中的一个基板电极4A连接。另一方面,连接布线13的一端与芯片部件2的一个电极4连接,另一端与基板1的背面1b中的一个基板电极4C连接。在本例中,这些连接布线11、13采用液滴喷出法形成。
在这里,在基板1上,形成旨在将连接布线13从安装面1a引导到背面1b的多个贯通孔3A。贯通孔3A的直径,例如和基板电极4C的宽度大致相同。另外,在基板1的背面1b上配置的基板电极4C,被配置成堵塞贯通孔3A中的背面1b侧的开口。就是说,背面1b侧的多个基板电极4C的靠近芯片部件2一侧的端部,分别覆盖着贯通孔3A的开口。
如图10B所示,与基板电极4C连接的连接布线13,沿着斜面部件15及斜面部件16的表面形成。就是说,在芯片部件2的侧面部位,形成斜面部件15及具有延长斜面部件15的斜面部15a的斜面部16a的斜面部件16。经由斜面部件15及斜面部件16的各斜面部15a、16a的表面及贯通孔3A后,形成连接器件电极7和基板电极4的连接布线13。在本例中,斜面部件16的斜面部16a,覆盖斜面部件15的斜面部15a一部分,向离开芯片部件2的方向延伸,到达基板1的安装面1a上,更具体地说,到达靠近贯通孔3A位置地形成。
返回图10A,在本例中,也对位于离器件电极7(芯片部件2)较近的位置的基板电极4A,形成斜面部件15的比较短的斜面部;对位于较远的位置的基板电极4C,形成斜面部件15及斜面部件16的比较长的斜面部。就是说,斜面部件15、16的斜面部的长度,按照一个器件电极7和与其对应的一个基板电极4之间的距离变化。这样,就形成直到基板电极4附近为止的阶差比较少的区域。其结果,对于交错状排列的多个的基板电极4的每一个,都能采用液滴喷出法切实地形成连接布线11、13。
在本例的安装基板20中,由于分别在非同一面的多个面1a、1b中配置多个基板电极4,所以能够使相邻的两个基板电极的间隔变得比较宽。就是说,多个基板电极4被交替排列配置成在基板1的厚度方向互相离开的两个电极组(基板电极4A…、基板电极4C…)。因此,各组中的相邻的基板电极4A…、4C…的间隔,就成为基板电极4的整体排列的间距的2倍(2×P3)。
这样,在本例的安装基板20中,通过在两面交替排列基板电极4,从而使相邻的两个基板电极的间隔变得比较宽。因此,能够使基板电极4的整体的排列间距(P3)与器件电极7的排列间距(P2)对应。在本例中,基板电极4的整体的排列间距(P3)和器件电极7的排列间距(P2)相同(例如40μm)。基板电极4的排列间距(P3)和器件电极7的排列间距(P2)相同后,可以减少布线的迂回等,能够缩短布线路线,缩小布线区域。
在这里,在本例的安装基板20中,通过贯通孔3A做媒介,将连接布线13从安装面1a延伸到背面1B,所以布线形成区域包含大致垂直的面一一贯通孔3A的壁面。在采用液滴喷出法形成布线时,这样的阶差虽然不好,但在本例中,贯通孔3A中的背面1b侧的开口被基板电极4C堵塞。因此,填埋贯通孔3A地配置连接布线13的形成材料后,能够采用液滴喷出法切实形成连接布线13,能够避免布线不良。
就是说,在基板1的贯通孔3A的内部配置连接布线13的形成材料之际,在基板1的背面1b侧的基板电极4C上配置该材料后,就能够防止材料的落下。进而,在该部分积蓄该材料后,基板1的安装面的1a和背面1b的基板电极4C被连接布线13切实地连接。这时,既可以完全填埋贯通孔3A的内部空间地配置形成材料,还可以将该材料配置到能够在贯通孔3A的壁面上切实配置连接布线13的程度。
此外,基板1的贯通孔3A,例如能够利用腐蚀或光束照射后形成。这样的贯通孔3A的壁面摩擦阻力比较大,所以在所谓固定效应的作用下,即使在大致垂直的面上,材料也比较容易附着。
另外,将贯通孔3A倾斜地形成后,由于贯通孔3A的壁面具有和前文讲述的斜面部件的斜面部相同的作用,所以能够更加切实地形成连接布线13。
图11A是表示图10A及图10B所示的安装基板的变形例的局部平面图,图11B是图11A所示的C-C剖面图。此外,在图11中,对具有和图10所示的安装基板20相同功能的构成要素,赋予相同的符号,省略或简化其说明。
如图11A所示,安装基板30具有采用面朝上接合法将芯片部件2安装到基板1上,使芯片部件2的电极(器件电极7)与基板1的电极(基板电极4)电连接的结构。
多个基板电极4,和图10的示例一样,分别交替地配置在基板1中的非同一个平面的安装面1a及其背面1b上(参照图11B)。就是说,多个基板电极4,在Y方向(各电极4的宽度方向)上,以所定的间距(P4)大致等间隔地排列配置的同时,还沿着其排列方向,一个个地分别交替地配置在基板1中的安装面1a和背面1b上。换言之,多个基板电极4具有分别配置在基板1的两面的两个电极组(基板电极4A…、基板电极4D…)。
在本例中,基板电极4A…的组和基板电极4D…的组,虽然和图10的示例一样,具有在Y方向上互相错开所定间距(P4)的位置关系。但和图10的示例不同,在X方向上具有大致相同的位置关系。
芯片部件2的电极7和基板1的电极4,通过多个连接布线11、14做媒介被电连接。多个连接布线11、14中,连接布线11的一端与芯片部件2的一个电极4连接,另一端与基板1的安装面1a中的一个基板电极4A连接。另一方面,连接布线14的一端与芯片部件2的一个电极4连接,另一端与基板1的背面1b中的一个基板电极4D连接。在本例中,这些连接布线11、14也采用液滴喷出法形成。
在基板1上,形成旨在将连接布线14从安装面1a引导到背面1b的多个贯通孔3B。贯通孔3B的直径,例如和基板电极4D的宽度大致相同。另外,在基板1的背面1b上配置的基板电极4D,被配置成堵塞贯通孔3B中的背面1b侧的开口。就是说,背面1b侧的多个基板电极4D的靠近芯片部件2一侧的端部,分别覆盖着贯通孔3B的开口。
在本例中,和图10的示例不同,斜面部件在俯视图中成为矩形,不包含梳形。就是说,本例的安装基板30,成为省去图10的安装基板20中的延长用的斜面部件16的结构。
如图11B所示,与基板电极4D连接的连接布线13,沿着斜面部件15的表面形成。就是说,在芯片部件2的侧面部位,形成斜面部件15。经由斜面部件15的斜面部15a的表面及贯通孔3B后,形成连接器件电极7和基板电极4D的连接布线14。
在本例的安装基板30中,也分别在非同一面的多个面1a、1b中配置多个基板电极4。所以能够使相邻的两个基板电极的间隔变得比较宽。就是说,多个基板电极4被交替排列配置成在基板1的厚度方向互相离开的两个电极组(基板电极4A…、基板电极4D…)。其结果,各组中的相邻的基板电极4A…、4D…的间隔,就成为基板电极4的整体排列的间距的2倍(2×P4)。
这样,在本例的安装基板20中,通过在两面交替排列基板电极4,从而使相邻的两个基板电极的间隔变得比较宽。因此,能够使基板电极4的整体的排列间距(P4)与器件电极7的排列间距(P2)对应。在本例中,基板电极4的整体的排列间距(P4)和器件电极7的排列间距(P2)相同(例如40μm)。基板电极4的排列间距和器件电极7的排列间距相同后,可以减少布线的迂回等,能够缩短布线路线,缩小布线区域。
另外,在本例中,因为多个基板电极4在X方向上大致处于相同的位置,所以能够缩小X方向的布线区域。同时,与图10的示例相比,在本例中具有减少斜面部件的优点。
(电子机器)
图12A是表示本发明涉及的电子机器的一个示例的立体图。该图所示的手机1300,在机体的内部或显示部1301中,具有采用上述方法获得的安装基板。图中,符号1302表示操作按钮,符号1303表示听筒,符号1304表示话筒。
图12B是图12A所示的显示部1301的立体结构图。显示部1301具有在由液晶显示装置及有机EL显示装置构成的显示屏1311的一个边端与安装了电子器件1312的安装基板1313连接的结构。而且,在该安装基板1313中,适当地使用了采用本发明的安装方法安装电子器件的安装基板。在安装基板上安装薄形的电子器件后,能够实现手机1300的薄形化、小型化。
所述实施方式的安装基板,不限于所述手机,可以在电子笔记本、个人用电子计算机、数码相机、液晶电视机、取景器型或监视型的磁带录放机、导航装置、页式阅读机、电子笔记本、台式电子计算机、字处理机、工作台、可视电话、POS终端、具有触摸屏的产品等各种电子机器中适当采用。无论在哪种电子机器中,采用本发明的安装基板后,都能够实现薄形化、小形化。另外,所述实施方式的安装基板,不局限于液晶装置,能够作为有机EL装置、等离子体显示装置(PDP)、电场释放显示器(FED)等电光学装置等的电子机器的部件等,适当采用。
以上,讲述了本发明的理想的实施示例,但本发明并不局限于这些实施示例。在不违背本发明的宗旨的范围内,可以附加、省略、置换结构以及其它变更。本发明并不局限于以上的讲述,它只由附加的权利要求书的范围限定。
Claims (8)
1、一种安装基板,是安装有电子器件的基板,其特征在于,包括:
在所述电子器件上形成的多个器件电极,
在所述基板上形成的多个基板电极,以及
采用液滴喷出法形成的、将所述多个器件电极与所述多个基板电极电连接的多个连接布线;
所述多个基板电极,排列成交错状。
2、如权利要求1所述的安装基板,其特征在于:所述多个基板电极,配置在所述基板中的大致同一个平面内,或者分开配置在所述基板中的非同一个平面的多个面。
3、如权利要求1或2所述的安装基板,其特征在于:在所述多个器件电极与所述多个基板电极之间,形成具有斜面部的斜面部件;
所述斜面部件的斜面部的长度,按照所述多个器件电极与所述多个基板电极之间的距离而变化。
4、如权利要求3所述的安装基板,其特征在于:所述斜面部件的整体形状,包含梳形。
5、一种安装基板,是安装有电子器件的基板,其特征在于,包括:
在所述电子器件上形成的多个器件电极,
在所述基板上形成的多个基板电极,以及
采用液滴喷出法形成的、将所述多个器件电极与所述多个基板电极电连接的多个连接布线;
所述多个基板电极,分开配置在所述基板中的非同一个平面的多个面。
6、如权利要求5所述的安装基板,其特征在于:所述多个面,包含所述基板中安装所述电子器件的安装面及其背面。
7、如权利要求6所述的安装基板,其特征在于:在所述基板上,设置将所述连接布线从所述安装面引导到所述背面的贯通孔;
在所述基板的背面,所述基板电极被配置成堵住所述贯通孔中的所述背面一侧的开口。
8、一种电子机器,具备权利要求1~7中的任一项所述的安装基板。
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JP2004331962A JP4613590B2 (ja) | 2004-11-16 | 2004-11-16 | 実装基板及び電子機器 |
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CN1776904A true CN1776904A (zh) | 2006-05-24 |
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Country | Link |
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US (1) | US7964955B2 (zh) |
JP (1) | JP4613590B2 (zh) |
KR (1) | KR100739851B1 (zh) |
CN (1) | CN100386874C (zh) |
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US7964955B2 (en) | 2011-06-21 |
JP4613590B2 (ja) | 2011-01-19 |
JP2006147647A (ja) | 2006-06-08 |
US20060103000A1 (en) | 2006-05-18 |
KR100739851B1 (ko) | 2007-07-16 |
KR20060055325A (ko) | 2006-05-23 |
TWI286361B (en) | 2007-09-01 |
CN100386874C (zh) | 2008-05-07 |
TW200623289A (en) | 2006-07-01 |
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