CN1790696A - 安装基板及电子仪器 - Google Patents

安装基板及电子仪器 Download PDF

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Publication number
CN1790696A
CN1790696A CNA2005101200326A CN200510120032A CN1790696A CN 1790696 A CN1790696 A CN 1790696A CN A2005101200326 A CNA2005101200326 A CN A2005101200326A CN 200510120032 A CN200510120032 A CN 200510120032A CN 1790696 A CN1790696 A CN 1790696A
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China
Prior art keywords
base plate
electronic device
installation base
flexible substrate
face
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CNA2005101200326A
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English (en)
Inventor
伊藤涉
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Seiko Epson Corp
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Seiko Epson Corp
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Publication of CN1790696A publication Critical patent/CN1790696A/zh
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Abstract

一种在挠性基板上安装具有具备连接端子的端子形成面的电子器件构成的安装基板，所述连接端子直接或介由导电构件电连接在所述挠性基板上形成的配线图案，与在该安装基板的厚度方向上的中立面几乎一致地配置有所述端子形成面。

Description

安装基板及电子仪器
技术领域
本发明涉及一种安装基板及电子仪器。
背景技术
近年来，以卡大小的电子仪器为首，各种电子仪器变得薄而轻起来。随着这样的电子仪器的薄厚度化、轻量化，要求在其上安装的各种电子器件仍以薄的状态被安装。作为电子器件的一实例，以硅制的IC芯片(半导体芯片)为例，近来可在硅晶片的状态下削切背面，形成厚度为50μm以下的极薄的IC芯片。
可是，作为在这样的电子器件和安装其的基板之间构成电连接的连接方法，现在已知使用各向异性导电材料(ACF或ACP)的方法或基于引线接合的方法(WB)。但是，在使用各向异性导电材料的方法中，因该各向异性导电材料不同，厚度增加了10～30μm左右，使安装了该装置的电子仪器或电子零件的厚度变厚这部分厚度。另外，在基于引线接合的方法中，由于为了缠绕引线，需要1mm以上的空间，所以安装了该电子器件的电子仪器或电子零件的厚度也同样变厚。
因此，在这些现有方法中，不能充分实现电子仪器或成为其零件的电子零件的薄厚度化、进而随之的轻量化。另外，在这些方法中，尤其是在适用于所述极薄的IC芯片的情况下，担心因接合时的超声波或压力，引起极薄IC芯片(极薄电子器件)的破坏或连接可靠性的降低。
在这样的背景基础上，在特开2001-230001号公报中，提议使用有弹性的导电材料进行端子间的电连接，提高连接构成的可靠性的安装方法。
可是，即便是上述现有技术文献中所述的安装方法，也存在对安装基板弯曲的耐性不够，因而降低反复使用的可靠性的课题。
若薄层化IC芯片至厚度50μm大小，则除芯片本身薄外，由于加工导致的细微不妥也与半导体芯片的破损有关，所以尤其希望提高芯片附近的弯曲耐性。
发明内容
本发明鉴于上述问题作出，其目的在于提供一种安装了搭载于电子仪器或电子零件上的安装了电子器件的安装基板，在实现薄厚度化的同时，具有柔性，对于弯曲的耐性强。
为了解决上述课题，本发明提供一种安装基板，在挠性基板上安装具有具备连接端子的端子形成面的电子器件构成，其特征在于：所述连接端子直接或介由导电材料电连接在所述挠性基板上形成的配线图案上，与该安装基板的厚度方向上的中立面几乎一致地配置在所述端子形成面。
该安装基板由于使用挠性基板作为基体，所以具有弹性，可比较自由地弯曲。而且，由于使所述电子器件的端子形成面和安装基板的中立面几乎一致地安装电子器件，所以弯曲安装基板时产生的变形在配置于中立面的电子器件的端子形成面中几乎为零。因此，在电连接电子器件的连接端子和安装基板上的配线图案之部位没有弯曲应力作用。由此，可实现对弯曲的耐性良好、可靠性良好的安装基板。
在本发明的安装基板中，最好是在该安装基板的厚度方向，夹持所述电子器件的端子形成面、在两侧分别配置的构成构件具有大致相等的弯曲弹性模数。由于所述中立面的位置，相当于在安装基板的厚度方向弯曲弹性模数平衡的位置，所以通过采用这样的构成，可以使所述端子形成面与中立面几乎一致。
在本发明的安装基板中，所述电子器件可构成为：以面向所述挠性基板侧的状态安装所述端子形成面，所述电子器件具有：与使所述挠性基板、和在该挠性基板和所述端子形成面之间形成的构成构件合在一起的弯曲弹性模数大致相等的弯曲弹性模数，在电子器件面向基板侧(下侧)安装其端子形成面时，由于该电子器件本身的弯曲弹性模数与安装电子器件的基板侧之构成构件(例如，挠性基板与在其表面上形成的绝缘层的层叠体)的弯曲弹性模数大致相等，所以可使所述端子形成面与中立面几乎一致。
在本发明的安装基板中，可构成为在所述配线图案上形成有向所述电子器件侧突出的导体柱，所述电子器件介由以包围所述导体柱的方式设置的粘着层安装于所述挠性基板上，使所述电子器件的连接端子电连接于所述导体柱。通过采用这样的构成，可以不使用ACF(各向异性导电膜)或ACP(各向异性导电浆)等就在基板上安装电子器件，尤其是如果所述导体柱是烧结金属微粒子而构成的，则难以在电子器件的安装时产生电子器件的破损等，还可得到连接端子与配线图案的良好接合性。
在本发明的安装基板中，最好是在所述挠性基板上的、所述电子器件外侧的区域，形成有覆盖所述配线图案的绝缘层。如果采用这样的构成，则可通过所述绝缘层保护配线图案，可提高安装基板的可靠性。
在本发明的安装基板中，也可构成为：在所述电子器件上也形成所述绝缘层。通过采用这样的构成，可通过所述绝缘层保护所述电子器件，还可有效地防止电子器件的脱离等。
在本发明的安装基板中，所述电子器件可构成为：在面向与所述挠性基板相反侧安装所述端子形成面的同时，形成覆盖该电子器件的绝缘层，在所述电子器件上形成的绝缘层具有：与使所述电子器件、所述挠性基板、设置在该电子器件和挠性基板间的构成构件合在一起的弯曲弹性模数大致相等的弯曲模性模数。也可面向与挠性基板相反侧配置电子器件的端子形成面。这时，由于在端子形成面的挠性基板侧配置电子器件的主体和挠性基板，所以可通过使在电子器件上设置的绝缘层之弯曲弹性模数与使两者合在一起的弯曲弹性模数一致，使中立面与端子形成面一致。
在本发明的安装基板中，最好是构成为：在所述电子器件的侧面形成有具有从该侧面向外侧延伸的斜面部之倾斜件，所述连接端子与配线图案，介由与所述倾斜件的斜面部抵接设置的连接配线而电连接的。若采用这样的构成，则由于可利用所述倾斜件缓和载置于挠性基板上的电子器件之端子形成面与挠性基板的阶差(台阶高差)，所以可在从连接端子经由倾斜件的斜面部到配线图案的基板上缠绕配线，可实现电子器件的安装结构的薄型化。
在本发明的安装基板中，最好是在所述电子器件外侧的区域中，夹持该电子器件的端子形成面之延长面、在两侧分别配置的该安装基板的构成构件，具有互相大致相等的弯曲弹性模数。即，最好是既便在安装电子器件的区域的外侧，也在与电子器件的端子形成面共面的位置上配置中立面。由此，可抑制弯曲应力引起的晶体管特性的变化，进一步得到更好的连接可靠性。
在本发明的安装基板中，最好是所述电子器件的厚度为50μm以下。若采用这样的构成，则在整个安装基板中得到良好的弹性。
下面，本发明提供一种安装基板的制造方法，制造前面所述的本发明的安装基板，其特征在于，包含：在所述挠性基板上形成包含配线图案的配线层的工序；在所述配线图案上和/或所述电子器件的连接端子上，使用液滴喷出法配置包含金属微粒子的液体状的工序；介由所述液状体接合所述配线图案和所述连接端子的工序；和通过干燥固化所述液状体来形成导电体，使所述配线图案与连接端子导通的工序。根据该制造方法，由于通过烧成配置在配线图案的连接部与电子器件的连接端子之间的液状体，并烧成其金属微粒子，在连接所述配线图案的连接部与所述电子器件的连接端子的同时电导通，所以连接及导通所需的厚度为金属微粒子烧成体部分的极薄的厚度，因而可使得到的安装结构的薄厚度化。另外，基本上可仅通过不加压电子器件的烧成处理，来确保所述连接部与端子之间的导通，因而，例如在安装极薄的半导体芯片时，也可进行不加压芯片的安装处理。因此，可避免加压导致的半导体芯片的破坏或连接可靠性的降低等不妥。因此，可确保得到的安装结构之弯曲性及连接可靠性。
在本发明的安装基板制造方法中，最好是通过在所述配线图案上和/或所述连接端子上配置所述液状体，从而在所述配线图案或所述连接端子上竖设导体柱。若采用这样竖设的导体柱，则得到安装电子器件时容易对准的优点。
在本发明的安装基板制造方法中，最好是通过在露出所述导体柱的状态下形成覆盖所述配线图案的粘着层，并在该粘着层上载置所述电子器件，从而在所述挠性基板上安装电子器件。若为这样的制造方法，则可使电子器件与挠性基板的粘着性良好，可提高得到的安装基板的可靠性。另外，由于在露出导体柱上面的状态下形成粘着层，所以可相对导体柱容易地对准电子器件的连接端子，可正确且容易地进行制造。
另外，本发明为解决上述课题，提供一种安装基板，在挠性基板上安装具有具备连接端子的端子形成面的电子器件，其特征在于：所述电子器件朝向所述挠性基板的相反侧配置有所述端子形成面，与该安装基板的厚度方向上的中立面几乎一致地配置有与所述电子器件的端子形成面相反侧的载置面。
该安装基板由于使用挠性基板作为基体，所以具有弹性，可比较自由地弯曲。而且，由于与所述电子器件的端子形成面相反侧的载置面与安装基板的中立面几乎一致地安装了电子器件，所以弯曲安装基板时产生的变形在配置于中立面的电子器件的载置面上几乎为零。因此，在与薄层化电子器件时作为磨削面的端子形成面相反侧的载置面上，无弯曲应力作用。由此，可防止在磨削时有可能导入细微裂纹(磨削裂纹)的载置面产生起因于磨削裂纹的伸展等的破损，可实现对弯曲的耐性良好、可靠性良好的安装基板。
在本发明的安装基板中，最好是在该安装基板的厚度方向，夹持所述电子器件的载置面、在两侧分别配置的构成构件具有大致相等的弯曲弹性模数。由于所述中立面的位置相当于在安装基板的厚度方向弯曲弹性模数平衡的位置，所以通过采用这种构成，可使所述载置面与中立面几乎一致。
在本发明的安装基板中，最好是在所述挠性基板上的、所述电子器件的外侧的区域中，形成覆盖所述配线图案的绝缘层。若采用这样的构成，则可利用所述绝缘层保护配线图案，可提高安装基板的可靠性。
在本发明的安装基板中，也可构成为在所述电子器件上也形成所述绝缘层。通过采用这样的构成，可利用所述绝缘层保护所述电子器件，还可有效地防止电子器件的脱离等。
在本发明的安装装置中，最好是采用如下构成：即，在所述电子器件的侧面部，形成有具有从该侧面部向外侧延伸的斜面部的倾斜件，所述连接端子和配线图案，介由与所述倾斜件的斜面部抵接设置的连接配线来电连接着。若采用这样的构成，则由于利用所述倾斜件缓和载置于挠性基板上的电子器件之端子形成面与挠性基板表面的阶差，所以可在从连接端子经由倾斜件的斜面部到配线图案的基板上缠绕配线，可实现电子器件的安装结构的薄型化。
在本发明的安装基板中，最好是所述电子器件的厚度为50μm以下。若采用这样的构成，则在整个安装基板中得到良好的弹性。
下面，本发明的安装基板的制造方法在挠性基板上安装采用一面具备连接端子的端子形成面的电子器件，其特征在于，包含：在所述挠性基板上介由粘着层载置电子器件的工序；在所述电子器件的侧面，形成具有从所述端子形成面向挠性基板上延伸的斜面部之倾斜件的工序；和形成经由所述倾斜件的斜面部的表面，电连接所述连接端子与所述配线图案的连接配线的工序，其中，使夹持所述电子器件的载置面、分别在两侧配置的构成构件的弯曲弹性模数互相大致相等。
下面，本发明的电子仪器的特征在于，具备前面记载的本发明的安装基板。根据该构成，通过在薄型下具有挠性、电连接的可靠性良好的安装基板，提供薄型、高可靠性的电子仪器。
附图说明
图1是第1实施方式的安装基板的部分截面图。
图2是第2实施方式的安装基板的部分截面图。
图3是表示第1实施方式的安装基板制造方法的截面构成图。
图4是液滴喷出头的说明图。
图5是第3实施方式的安装基板的部分截面构成图。
图6是表示第3实施方式的安装基板制造方法的截面构成图。
图7是电子仪器之一实例和其具备的显示部的立体构成图。
具体实施方式
下面，参照附图来详细说明本发明的实施方式。
(实施方式1)
图1是表示本发明的安装基板的一实施方式的部分截面构成图。如图1所示，安装基板10FD具备在挠性基板1上安装了半导体芯片(在一面具备连接端子的电子器件)2的构成。由于挠性基板1由聚酰亚铵等树脂构成，所以使用形成带状或片状等各种形状。
在挠性基板1上，形成金属配线(配线图案)4。该金属配线4是在挠性基板上形成的配线、或如后述使用液滴喷出法形成的配线，由银微粒子等金属微粒子的烧成体来形成的。另外，该金属配线4在挠性基板1的端缘侧连接于未图示的配线，介由该配线，连接于挠性基板1之外的外部端子(未图示)。另外，该金属配线4变为挠性基板1的中央部侧的端部连接半导体芯片2的端子的连接部4a，在该连接部4a上形成有高度为数十μm大小的、具有导电性的柱状导体柱5。
导体柱5通过液滴喷出法来形成，是烧成银微粒子等金属微粒子后形成的。
另外，在挠性基板1上，形成有由热固化性的绝缘性树脂构成的粘着层6。该粘着层6如后述，在露出所述导体柱5上面的状态下覆盖金属配线4，由此，粘着挠性基板1和半导体芯片2之间。作为形成该粘着层6的热固化性树脂，例如使用环氧系树脂材料等。
而且，在该粘着层6上，半导体芯片2在面向挠性基板1侧的状态下配设了其端子形成面(有源面)2a。在本实施方式中，半导体芯片2是在50μm以下厚度下形成的极薄的芯片，在面向挠性基板1侧的状态下安装、即倒装焊接衬垫(连接端子)7的。该半导体芯片2的衬垫(pad)7例如在由从半导体芯片2内的集成电路(未图示)引出的铝合金构成的基层上，依次电镀Ni、Au形成的。另外，就衬垫7中作为实质性接合层的最外层(最上层)而言，除Au以外，例如也可为Ag、Cu、Sn、In，以及由多种这些元素构成的层叠构成。
该衬垫7通过直接抵接、接合于所述导体柱5，形成与所述金属配线4的导电连接构成。另外，这样，衬垫7在介由导体柱5连接于金属配线4的同时，半导体芯片2的下面介由粘着层6连接于挠性基板1，从而半导体芯片2坚固地紧固于挠性基板1上。
另外，形成有由丙烯基树脂或环氧树脂等有机绝缘材料构成的绝缘层8，以覆盖半导体芯片2的外侧区域的金属配线4。该绝缘层8是取得保护金属配线4的功能的、所谓钝化膜，防止与外部接触导致的金属配线4短路、或环境水分或反应性气体导致的金属配线4腐蚀等。另外，也可形成该绝缘层8，使其不仅覆盖金属配线4，还覆盖半导体芯片2的表面。即，也可采用在绝缘层8与挠性基板1之间密封半导体体芯片2。这时，还取得防止半导体芯片2破损或脱离的功能。
具备了上述构成的本实施方式的安装基板10FD，由于在具有弹性的挠性基板1上安装了薄层的半导体芯片2，所以例如可在侧面看弯曲成U形的状态下安装于电子仪器、或适用于电子标签等可变形的显示装置的控制部中。而且，如图1所示，在本实施方式的安装基板10FD中，其中立面(在使弯曲应力作用于安装基板10FD是时，变形ε为零的面)np与半导体芯片2的端子形成面2a几乎一致。即，调整为在安装基板10FD的厚度方向，夹持端子形成面2a、在两侧分别配置的构成构件(挠性基板1、半导体芯片2、粘着层6等)的弯曲弹性模数大致相等。通过采用这样的构成，本实施方式的安装基板10FD，在半导体芯片2和导体柱5的连接部分弯曲基板时的变形几乎为零，没有因变形而产生的晶体管特性的变化，还可有效地防止损坏该连接部分中的电连接。由此，采用具备良好弯曲耐性的高可靠性的安装基板。
上述弯曲弹性模量可使用3点弯曲试验中求出的负荷—弯曲曲线计算出的弹性模数Eb，由下式(1)算出。其中，在公式(1)中，L为支点(支持滚)间的距离，W为试验片的宽度，t为试验片的厚度，F为在负荷—弯曲曲线的弹性变形区域中任意选择的负荷，Y为所述负荷F的弯曲(位移)。另外，在式(1)中，也可设负荷F为2点负荷P1、P2的差(P1-P2)，设Y为分别对应于所述负荷P1、P2的位移y1、y2的差(y1-y2)。
Eb＝L3F/4wt3Y                 (1)
在图1示出的安装基板10FD的情况下，调整为由从端子形成面2a起图示下侧配置的粘着层6和挠性基板1构成的层叠结构物的弯曲弹性模数、与半导体芯片2的弯曲弹性模数大致相等。弯曲弹性模数可通过挠性基板1的厚度或杨氏模量来调整。另外，在本实施方式中，如果使用液滴喷出法来形成所述金属配线4，则由于极薄地形成其膜厚，所以基本不影响上述弯曲弹性模数。
另外，在本实施方式的安装基板10FD中，最好是既便在半导体芯片2外侧的区域，在与半导体芯片2的端子形成面2a共面的位置上也配置安装基板的中立面。这是由于若因安装基板上的部位不同而中立面的位置不同，则在弯曲安装基板时，因部位不同产生位移的大小不同，担心不能得到均匀的弯曲性，且局部产生大的负荷。
如图所示，半导体芯片2外侧的区域，在挠性基板1上层叠金属配线4和绝缘层8，与端子形成面2a共面的中立面np位于绝缘层8中。因此，可主要通过绝缘层8的厚度调整来调整调整中立面的位置所用的弯曲弹性模数。
如上述说明，本实施方式的安装基板10FD由于采用具有与半导体芯片2的端子形成面2a几乎一致的中立面，所以在弯曲基板时的端子形成面2a中几乎没有变形。由此，成为在半导体芯片2和金属配线4的导电连接部中可得到对弯曲应力良好耐性的高可靠性的安装基板。
(实施方式2)
下面参照图2说明本发明实施方式2的安装基板的构成。图2是本实施方式的安装基板的部分截面构成图。
另外，本实施方式的安装基板10FU，除作为电子器件的半导体芯片2的安装结构不同以外，与前面的实施方式1的安装基板10FD为相同的结构，所以在图2中，附以与图1共同符号的构成要素作为相同的构成要素，省略说明。
图2示出的安装基板10FD具备在挠性基板1上形成金属配线4，介由粘着层6安装半导体芯片2的构成。半导体芯片2在面向与挠性基板1相反侧的状态下粘着其端子形成面2a，相对挠性基板1正装焊接的。
在半导体芯片2的侧面部，形成具备从端子形成面2a向外侧延伸至挠性基板1上的斜面部的倾斜件9，经由该倾斜件9的斜面部的表面，形成了电连接衬垫7和金属配线4的连接配线4c。连接配线4c使用液滴喷出法来形成，是烧结金属微粒子构成的薄膜。倾斜件9取得缓和半导体芯片2的端子形成面2a与挠性基板1表面的阶差的作用，取得防止使用液滴法形成的连接配线4c断线等功能。
倾斜件9，可使用分配器(dispenser)等液体材料涂布机构，在挠性基板1上涂布例如聚酰亚胺树脂、硅变性聚酰亚胺树脂、环氧树脂、硅变性环氧树脂、苯并环丁烯(BCB；benzocyclobutene)、聚苯并噁唑(PBO；polybenzoxazole)等的树脂材料形成。或者，也可通过液滴喷出法或紧固干膜的方法来形成。
在包含半导体芯片2、金属配线4、连接配线4c等的挠性基板1上，形成由丙烯基树脂或环氧树脂等有机绝缘材料构成的绝缘层8a。绝缘层8a如图所示，在半导体芯片2上和其外侧区域中膜厚不同，本实施方式的情况下，形成为在半导体芯片2上薄、在半导体芯片2的外侧厚。
在具备上述构成的本实施方式的安装基板10FU上，调整各构成构件的弯曲弹性模数，以使半导体芯片2的端子形成面2a与安装基板10FU的中立面np几乎一致。本实施方式的情况下，在端子形成面2a的图示下方，配置挠性基板1、粘着层6和半导体芯片2，在图示上方仅配置绝缘层8a，所以当调整上述中立面时，可主要通过绝缘层8a的材质变更和/或厚度调整来进行。
另外，在本实施方式的安装基板10FU上，最好是半导体芯片2的外侧区域的中立面调整为与半导体芯片2的端子形成面2a为共面。该区域的中立面的调整也可通过绝缘层8a的材质变更和/或厚度调整来进行。
这样，在实施方式2的安装基板10FU上，由于半导体芯片2的端子形成面2a与安装基板的中立面np几乎一致，所以在弯曲安装基板10FU时，连接配线4c和衬垫的接合部中几乎没有变形，得到良好的连接可靠性。另外，由于连接配线4c使用液滴喷出法形成，所以与引线接合相比，可安装极薄的电子器件，对安装该安装基板的电子仪器的薄型化起到很大作用。
(安装基板的制造方法)
下面，参照图3说明图1示出的实施方式1的安装基板10FD的制造方法。
首先，如图3(a)所示，准备挠性基板1，在挠性基板1上的规定位置上，通过液滴喷出法喷出配置使金属微粒子分散到分散液中而构成的液状体。作为液滴喷出法，可采用喷墨法或分配器法等，但尤其最好是喷墨法，因为可在期望位置上配置期望量的液状材料。在本实施方式中设使用喷墨法。
这里，说明适用于进行基于喷墨法的喷出的液滴喷出头(喷墨头)。液滴喷出头34如图4(a)所示，例如具备不锈钢制的喷嘴板12和振动板13，介由间隔构件14(贮藏板)接合两者。在喷嘴板12和振动板13之间，由间隔构件14形成多个空间15和贮液部16。由液状材料充满各空间15和贮液部16，各空间15和贮液部16介由供给口17连通。另外，在喷嘴板12上，在纵横排列的状态下形成有多个用于从空间15喷射液状材料的喷嘴孔18。另外，在振动板13上，形成有用于向贮液部16供给液状材料的孔19。
另外，在与振动板13相对向于空间15的面相反侧的面上，如图4(b)所示，接合着压电元件(压电元件)20。该压电元件20构成为位于一对电极21之间，一旦通电，该元件就向外侧突出地弯曲。而且，在这种构成的基础上，接合压电元件20的振动板13与压电元件20为一体，同时向外侧弯曲，由此，空间15的容积增大。因此，相当于增大的容积大小的液状材料从贮液部16介由供给口17流入空间15中。另外，若从这种状态解除对压电元件20的通电，则压电元件20和振动板13同时回到原来的形状。因此，由于空间15也回到原来的容积，所以空间15内部的液状材料的压力上升，从喷嘴孔18向挠性基板1喷出液状材料(液状体)的液滴22。
作为喷出的液状体，使用使金、银、铜、钯、镍等金属微粒子分散到分散液中构成的液状体。这里，就金属微粒子而言，为提高其分散性，可在表面涂层有机物等来使用。作为涂层于金属微粒子表面的涂层材料，例如举出引起立体障碍或静电排斥那样的聚合物。另外，最好是金属微粒子的粒径为5nm以上，0.1μm以下。这是由于若比0.1μm大，则容易引起喷出头的喷嘴堵塞，基于喷墨法的喷出变得困难。还由于若比5nm小，则涂层材料与金属微粒子的体积比变大，得到的膜中的有机物的比例过大。
作为使金属微粒子分散的分散液，最好是室温下的蒸气压为0.001mmHg以上、200mmHg以下(约0.133Pa以上、26600Pa以下)。这是由于在蒸气压比200mmHg高时，喷出之后分散液急剧地蒸发，难以形成良好的膜(配线膜)。
另外，更好是分散液的蒸气压为0.001mmHg以上、50mmHg以下(约0.133Pa以上、6650Pa以下)。这是由于在蒸气压比50mmHg高时，利用喷墨法(液滴喷出法)喷出液滴时，容易引起干燥导致的喷嘴堵塞，难以稳定的喷出。另外，是由于在室温下的蒸气压比0.001mmHg低的分散液的情况下，干燥变慢，分散液容易残留在膜中，在后面工序的加热处理之后难以得到优质的导电膜(配线)。
作为使用的分散液，可分散所述金属微粒子，如果不引起凝聚，则不特别地限定，但除水之外，还可举出甲醇、乙醇、丙醇、丁醇等醇类、正庚烷、正辛烷、癸烷、十四烷、十氢化萘、甲苯、二甲苯、甲基异丙基苯、杜烯、茆、双茂烯、四氢化萘、十氢化萘、环己基苯等烃类化合物；或乙二醇二甲醚、乙二醇二乙醚、乙二醇甲基乙基醚、二甘醇二甲醚、二甘醇二乙醚、二甘醇甲基乙基醚、1，2-二甲氧基乙烷、二(2-甲氧基乙基)醚、p-二噁烷等醚类化合物；进而聚丙烯碳酸脂、γ-丁内酯、N-甲基-2-吡咯烷酮、二甲基甲酰胺、二甲亚矾、环己酮等极性化合物。其中，在微粒子的分散性和分散液的稳定性、或易适用于喷墨法的方面上，水、醇类、烃类化合物、醚类化合物最好，作为更好的分散液，可举出水、烃类化合物。这些分散液可单独或作为2种以上的混合物来使用。
分散所述金属微粒子到分散液时的分散质浓度、即金属微粒子浓度为1质量％以上、80质量％以下，可对应期望的金属配线4的膜厚来调整。这是由于若不足1质量％，则在后述加热的烧成处理时要求长时间，另外，若超过80质量％，则容易引起凝聚，难以得到均匀的膜。
最好是使所述金属微粒子分散到分散液构成的液状体的表面张力在0.02N/m以上、0.07N/m以下的范围内。这是由于在利用喷墨法喷出液状体时，若表面张力不足0.02N/m，则因该液体对喷嘴面的可润性增大，易产生飞行弯曲；若超过0.07N/m，则因在喷嘴前端的液面凹凸面的形状不稳定，所以难以控制喷出量、喷出计时。
最好是上述液状体的粘度为1mPa.s以上、50mPa.s以下。这是由于在利用喷墨法喷出时，粘度比1mPa.s小时，喷出头的喷嘴周围因墨水(液状体)流出而易被污染，另外，在粘度比50mPa.s大时，喷嘴孔中的堵塞频率变高，难以顺利地喷出液滴。
在本实施方式中，如图3(a)所示，从液滴喷出头34喷出使用银微粒子作为金属微粒子构成的液状体的液滴22，在挠性基板1上的应形成配线处滴下，在烧成后形成成为金属配线4的中间结构体4b。本实施方式的情况下，该中间结构体4b是指滴下到基板上的液状体或该液状体的干燥物。最好是在所述液状体的喷出配置时，控制连续喷出的液滴的重叠程度，以使不产生贮液(隆起)。另外，可采用在第一次喷出中互相不连接地离间喷出多个液滴，利用第二次以后的喷出，埋藏其间隔的喷出方法。
这样，若形成金属配线4的中间结构体4b，则通过在200℃左右下进行加热来烧成该中间结构体4b，烧结金属微粒子(银微粒子)，如图3(b)所示形成金属配线4。另外，就金属配线4的中间结构体4b而言，也可不限于烧结金属微粒子(银微粒子)的固化真固化处理，而停留于使液状体中的分散液蒸发程度的临时固化处理。
接着，在得到的金属配线4的连接部4a、即由挠性基板1中央部的端部构成的连接部4a上，与金属配线4的形成相同，从液滴喷出喷嘴34喷出配置所述液状体成柱状，形成导体柱5的中间结构体5a。接着，通过干燥该中间结构体5，在连接部4a上保持柱状。作为该干燥处理，还可采用数十℃左右下的加热处理、利用吹风机等吹出温风或热风的处理、及减压处理等。
这样，如果干燥导体柱5的中间结构体5a，则在挠性基板1上，在覆盖所述金属配线4的状态下涂布所述的热固化性树脂，如图3(c)所示，在未固化的状态下形成粘着层6。就涂布法而言，不特别地限定，可采用辊涂法或液滴喷出法等已知的涂布方法。另外，在该粘着层6a形成时，特别使之露出于所述导体柱5的中间结构体5a的上面。
接着，在该未固化状态的粘着层6a上定位半导体芯片2，如图3所示，在使衬垫接合于所述导体柱5的中间结构体5a的状态下载置该半导体芯片2。这时，对半导体芯片2不加压，几乎仅利用其自重的压力，使该衬垫7与所述柱5的前驱体5a接合。于是，由于中间结构体5a为临时固化状态，所以尽管半导体芯片2是在50μm以下厚度下形成的极薄的芯片，轻量，但在其自重的压力下也容易变形，良好地抵接于衬垫7。同样，由于粘着层6a是未固化状态，所以良好地抵接于半导体芯片2的下面。
之后，通过200℃下加热处理2小时左右，烧成干燥状态的所述中间结构体5a，烧结金属微粒子(银微粒子)，作为导体柱5。由此，在介由该导体柱5连接所述金属配线4的连接部4a和所述半导体芯片2的衬垫7的同时电导通。另外，与此同时使粘着层6a固化，作为粘着层6，介由该粘着层6，密接固定半导体芯片2的下面于挠性基板1上，得到具备图1示出的安装结构安装基板10FD。
另外，在对如前所述的金属配线4的中间结构体4b不是固化真固化处理而只限于临时固化处理时，通过这里的导体柱5的中间结构体5a的烧成处理，还烧结中间结构体4a的金属微粒子。
在通过上述工序得到的安装基板10FD的制造时，通过适当选择、调整挠性基板1的材质及板厚、粘着层6的材质及膜厚、及半导体芯片2的板厚等，安装基板10FD的中立面与半导体芯片2的端子形成面2a几乎一致。而且，在得到的安装基板10FD上，在弯曲基板时，在衬垫7与导体柱5的抵接部几乎没有变形，所以得到非常良好的连接可靠性。
因此，该安装基板10FD在可确保整体的弯曲性的同时，还可确保其连接可靠性。
另外，由于采用了介由导体柱5电连接金属配线4的连接部4a和衬垫7的结构，形成未固化的粘着层6a，使导体柱5(中间结构体5a)的上面露出，所以在安装半导体芯片2时，使衬垫7连接于连接部4a上的对准变得容易，并且，由于导体柱5由金属微粒子的烧结体构成，因而增强了连接部4a与衬垫7的连接强度，提高了连接可靠性。另外，具有通过在挠性基板1与半导体芯片2之间配置的粘着层6，在挠性基板1和半导体芯片2之间可得到良好的接合性及密封性的优点。
另外，在这样的安装基板的制造方法中，通过烧成作为在金属配线4的连接部4a与半导体芯片2的衬垫7之间配置的导体柱的中间结构体5a的液状体，并烧结其金属微粒子，从而使所述连接部4a与所述衬垫7同时电导通，因此，导电连接所需的厚度变为金属微粒子烧结体部分的极薄的厚度，因此，可使得到的安装结构的薄厚度化。
另外，基本上仅通过未加压半导体芯片2的烧成处理，就可确保所述连接部4a与衬垫7之间的导通，因此，例如在安装极薄的半导体芯片2时，也可进行不加压芯片的安装处理。因而，可避免加压导致的半导体芯片2破坏或连接可靠性降低等不妥。因此，本发明尤其适用于各种电子仪器或其零件(电子零件)中的超薄型组件的制造上。
另外，在金属配线4的连接部4a上，通过配置由液滴喷出法使金属微粒子分散的液状体，来形成柱状的导体柱5，在连接所述连接部4a和所述衬垫7的同时电导通，所以在安装半导体芯片2时，可容易地采用使衬垫7连接于连接部4a上的对准，并且，可增强连接部4a和衬垫7的连接强度，提高连接可靠性。
另外，由于通过使用使金属微粒子分散的液状体之液滴喷出法来形成所述金属配线4，所以该金属配线4可充分地薄厚度化，因此，可进一步推进安装结构整体的薄厚度化。另外，由于可利用与喷出接合金属配线4和所述衬垫7所用的液状体相同的装置连续形成金属配线4，所以可提高生产率。
另外，由于在介由所述液状体接合所述金属配线4的连接部4a和所述半导体芯片2的衬垫7的工序之前，在露出所述连接部4a的状态下形成了由热固化性的绝缘性树脂构成的粘着层6a，所以通过用于连接及导通的液状体的烧成处理，同时固化由热固化性树脂构成的粘着层6a，所以可更好地进行挠性基板1和半导体芯片2之间的接合及密封，并且，与通过不充满(underfill)的使用来进行密封的情况相比，由于无固化处理时间，所以可提高生产率。
另外，在所述实施方式中，在金属配线4的连接部4a上形成导体柱5，介由该导体柱5连接并导通连接部4a和衬垫7，但本发明不限于此，也可在连接部4a上配置包含金属微粒子的液状体，直接连接衬垫7于该液状体上。这时，就液状体而言，无论配置于接合部4a，还是配置于衬垫7上都可以。在其任一情况下，由于使金属微粒子分散的液状体对由相同金属构成的连接部4a或衬垫7之任一，可润性良好，所以通过利用液滴喷出法等选择地配置，良好地涂布在连接部4a或衬垫7上。
另外，就导体柱5而言，也可以不通过使用包含金属微粒子的液状体的液相法来形成，利用电镀等由金属导电体形成，这时，只要仍然在该导体柱上配置使金属微粒子分散的液状体，介由该液状体连接衬垫7即可。
另外，在所述实施方式中，在挠性基板1上形成粘着层6，由此进行挠性基板1与半导体芯片2之间的接合及密封，本发明不限于此，例如也可利用不充满材料来进行挠性基板1与半导体芯片2之间的密封。
(实施方式3)
下面，参照图5说明本发明实施方式3的安装基板的构成。图5是本实施方式的安装基板的部分截面构成图。
另外，在本实施方式中，附以与前面实施方式的安装基板共同符号的构成要素作为相同的构成要素，省略说明。
如图5所示，安装基板110具备在挠性基板1上安装了半导体芯片2的结构。由于挠性基板1由聚酰亚胺等树脂构成，所以使用形成带状或片状等等各种形状的树脂。
在挠性基板1上形成金属配线4，使之介由连接配线4c与半导体芯片2的衬垫7连接。另外，在挠性基板1上，形成有由热固化性的绝缘性树脂构成的粘着层6。该粘着层6粘着挠性基板1和半导体芯片2之间，作为形成粘着层6的热固化性树脂，例如使用了环氧系树脂材料等。
而且，在该粘着层6上，半导体芯片2在面向挠性基板1侧的状态下粘接着与其端子形成面(有源面)2a相反侧的载置面2b。由于半导体芯片2在本实施方式中是在50μm以下的厚度下形成的极薄的芯片，所以在面向与挠性基板1相反侧的状态下安装作为有源面的端子形成面2a、即正装焊接的。
半导体芯片2的衬垫7例如在由从半导体芯片2的集成电路(未图示)引出的铝合金构成的基层(未图示)上，Ni、Au依次电镀后形成。另外，就在衬垫7中为实质性接合层的最外层(最上层)而言，除Au以外，例如也可为Cu、Sn、In，并且也可采用由多种这些元素构成的层叠结构。
在半导体芯片2的侧面部，形成从端子形成面2a向外侧延伸至挠性基板1上的斜面部的倾斜件9，经由该倾斜件9的斜面部的表面，形成有连接衬垫7和金属配线4的连接配线4c。连接配线4c使用液滴喷出法来形成，是烧结金属微粒子构成的配线。倾斜件9取得缓和半导体芯片2的端子形成面2a与挠性基板1表面的阶差的作用，取得防止使用液滴喷出法形成的连接配线4c断线等的功能。
倾斜件9可使用分配器等液体材料涂布零件，在挠性基板1上涂布例如聚酰亚胺树脂、硅变性聚酰亚胺树脂、环氧树脂、硅变性环氧树脂、苯并环丁烯(BCB；benzoclobutene)、聚苯并噁唑(PBO；polybenzoxazole)等树脂材料来形成。或者，也可通过液滴喷出法或紧固干膜的方法来形成。
在包含半导体芯片2、金属配线4、连接配线4c等的挠性基板1上，形成有由丙烯基树脂或环氧树脂等有机绝缘材料构成的绝缘层8a。绝缘层8a是保护金属配线4及半导体芯片2的、所谓钝化膜，取得防止与外部接触导致的金属配线4短路、水分或反应性气体导致的金属配线4、连接配线4c等腐蚀及在半导体芯片2破损等功能。绝缘层8a如图所示，在半导体芯片2上和其外侧区域膜厚不同，本实施方式的情况下，形成为半导体芯片2上薄，半导体芯片2外侧厚。
具备上述构成的本实施方式的安装基板110，由于在具有弹性的挠性基板1上安装了薄层的半导体芯片2，所以例如可在侧面看弯曲成U形的状态下安装于电子仪器中，或适用于电子标签等可变形的显示装置的控制部等。而且，如图5所示，在本实施方式的安装基板110中，其中立面(在使弯曲应力作用于安装基板110时，变形ε为零的面)np，与半导体芯片的端子形成面2a几乎一致。即，调整为在安装基板110的厚度方向，夹持端子形成面2a、在两侧分别配置的构成构件(挠性基板1、半导体芯片2、粘着层6、绝缘层8a等)的弯曲弹性模数大致相等。
通过将上述中立面np调整为与半导体芯片2的载置面2b几乎一致，本实施方式的安装基板110取得良好的弯曲耐性。半导体芯片2是薄层化至50μm左右的极薄的电子器件，但在其薄层化时，通常使用从端子形成面(有源面)2a的相反侧磨削半导体基板的方法。因此，有时通过使用磨石等磨削零件的加工，在半导体芯片2的载置面2b上产生微小的裂纹。该磨削裂纹对半导体芯片2的动作本身不产生影响，但假如如本实施方式的安装基板那样在使用时被弯曲，则担心在使半导体芯片2弹性变形时磨削裂纹发展、芯片破损。因此，在本实施方式中，通过调整各构成构件的材质和/或厚度，使半导体芯片2的载置面2b与安装基板110的中立面np几乎一致，从而在弯曲安装基板110时的变形，在载置面2b中几乎为零，有效地防止弯曲应力导致的磨削裂纹的延伸。
图5所示的安装基板110的情况下，调整为从与端子形成面2a相反侧的载置面2b起在图示下侧配置的由粘着层6和挠性基板1构成的层叠结构物之弯曲弹性模数、与由半导体芯片2和绝缘层8a构成的层叠结构物之弯曲弹性模数几乎一致。弯曲弹性模数可通过挠性基板1或粘着层6的厚度或杨氏模量来调整。
另外，本实施方式的情况下，由于金属配线4使用液滴喷出法来形成，所以形成为极薄的厚度，基本不影响上述弯曲弹性模数。
另外，在本实施方式的安装基板110中，最好是既便在半导体芯片2的外侧区域，在与半导体芯片2的端子形成面2a为共面的位置上，也配置安装基板的中立面。这是由于若因安装基板上的部位不同，而中立面的位置不同，则担心在弯曲安装基板时，因部位不同，产生位移的大小不同，不能得到均匀的弯曲性，或局部产生大的负荷。
如图所示，半导体芯片2的外侧区域中，在挠性基板1上层叠金属配线4和绝缘层8a，与端子形成面2a共面的中立面np位于绝缘层8a中。因此，用于调整中立面位置的弯曲弹性模数调整可主要通过绝缘层8a的厚度调整来进行。
如上所述，本实施方式的安装基板110由于采用具有与半导体芯片2的端子形成面2a几乎一致的中立面，所以在弯曲基板时的端子形成面2a中几乎没有变形。由此，变成在半导体芯片2和金属配线4的导电连接部可得到对弯曲应力良好耐性的高可靠性的安装基板。
(安装基板的制造方法)
下面，参照图6说明图5示出的实施方式3之安装基板110的制造方法。
首先，如图6(a)所示，准备挠性基板1，在该挠性基板1上的规定位置上，如图6(a)所示，利用液滴喷出法喷出配置使金属微粒子分散至分散液中构成的液状体。作为液滴喷出法，可采用喷墨法或分配器法等，但尤其最好是喷墨法，可在期望位置上配置期望量的液状材料。在本实施方式中使用与前面实施方式相同的喷墨法。
在本实施方式中，如图6(a)所示，从液滴喷出头34喷出作为金属微粒子使用银微粒子构成的液状体的液滴22，在挠性基板1上应形成配线处滴下，形成烧成后为金属配线4的中间构造体4b。本实施方式的情况下，该中间构造体4b指滴下到基板上的液状体或该液状体的干燥物。最好是在所述液状体的喷出配置时，控制连续喷出的液滴的重量大小，以不产生贮液部(凸出)。还可采用在第一次喷出中互相不挨着地隔开喷出多个液滴，利用第2次以后的喷出，埋藏其间隔的喷出方法。
这样，如果形成了金属配线4的中间构造体4b，则通过在200℃左右下加热该中间构造体4b，烧结金属微粒子(银微粒子)，如图6(b)所示形成金属配线4。另外，对中间构造体4b而言，也可以不是烧结金属微粒子(银微粒子)而作成金属配线4的真固化处理，而停留于蒸发液状体中的分散液程度的临时固化处理。
接着，在所述挠性基板1上涂布热固化性树脂，如图6(b)所示，形成未固化状态下的粘着层6a。就涂布法而言，未特别地限定，可采用滚筒涂布法或液滴喷出法等已知的涂布法。在本实施方式中，虽然在未与金属配线4重叠的位置上形成粘着层6，但也可覆盖一部分金属配线4那样在基板中央侧的端部形成粘着层6。这时，在介由粘着层6粘着的半导体芯片2的下侧(挠性基板1侧)配置连接配线4。另外，在该构成中，如果在半导体芯片2的载置面2b上不形成连接端子，则可在半导体芯片2的安装区域内连接金属配线4和载置面2b侧的连接端子。
接着，在该未固化状态的粘着层6a上对位半导体芯片2，如图6(c)所示，与粘着层6平面重叠地载置。接着，如图6(d)所示，形成用于缓和半导体芯片的端子形成面2a与金属配线4之间的阶差的倾斜件9。该倾斜件30例如可通过使用分配器等液体材料涂布零件，涂布聚酰亚胺树脂、硅变性聚酰亚胺树脂、环氧树脂、硅变性环氧树脂、苯并环丁烯(BCB；benzoclobutene)、聚苯并噁唑(PBO；polybenzoxazole)等树脂材料来形成。
如图所示，倾斜件9形成为从半导体芯片2的侧面向外侧变薄，具有从半导体芯片2的端子形成面2a至金属配线4的倾斜面。另外，倾斜件9也可在不覆盖衬垫7的限度下其一部分搭在端子形成面2a上。
接着，如图6(e)所示，形成连接配线4c。连接配线4c形成为从在端子形成面2a上形成的衬垫7的上面、通过倾斜件9的斜面上到达金属配线4上。该连接配线4c可通过与前面金属配线4相同的方法来形成。具体地说，如图6(e)所示，从喷出头34向规定位置喷出包含金属微粒子(银微粒子)的液状体的液滴后，在基板上选择配置，之后，经干燥工序、烧成工序采用金属配线。
另外，与上述连接配线4c的烧成同时使粘着层6a固化而作成粘着层6，介由该粘着层6密接挠性基板1固定半导体芯片2的载置面2b。之后，通过形成覆盖半导体芯片2及金属配线4的绝缘层8a，得到具备图5示出的安装结构的安装基板110。
另外，如上所述，对金属配线4的中间结构体4b而言，在不是真固化处理而停留于临时固化处理时，通过连接配线4c的烧成处理，烧结中间结构体4a的金属微粒子。
在制造由上述工序得到的安装基板110时，通过适当选择、调整挠性基板1的材质及板厚、粘着层6的材质及膜厚、及半导体芯片2的板厚等，安装基板110的中立面与半导体芯片2的载置面2b几乎一致。而且，作为得到的安装基板110，在弯曲基板时，在有可能产生磨削裂纹的载置面2b上几乎没有变形，所以可有效地防止半导体芯片2的破损，得到极好的可靠性。
另外，采用介由连接配线4c电连接金属配线4和衬垫7的构成，基本上仅通过不加压半导体芯片2的烧成处理，可确保金属配线4与衬垫7之间的导通。因此，例如在安装极薄的半导体芯片2时，可进行不加压芯片的安装处理。因此，可避免加压导致的半导体芯片2的破坏或连接可靠性的降低等不妥。因此，本发明尤其适用于各种电子仪器或其零件(电子零件)的超薄型组件的制造中。
另外，由于通过使用使金属微粒子分散了的液状体之液滴喷出法形成所述金属配线4及连接配线4c，所以这些金属配线4及连接配线4c也可充分薄厚度化，因此，可进一步推进安装结构整体的薄厚度化。另外，由于利用相同的装置喷出形成金属配线4或连接配线4c所用的液状体，所以可提高生产率。
另外，在介由所述液状体接合所述金属配线4和所述半导体芯片2的衬垫7的工序之前，在半导体芯片2的下侧形成由热固化性的绝缘性树脂构成的粘着层6a，所以，通过连接及导通用的液状体的烧成处理，同时固化由热固化性树脂构成的粘着层6a，所以，可更好地进行挠性基板1与半导体芯片2之间的接合及密封，并且，与利用不充满的使用进行密封的情况等相比，由于没有固化处理时间，所以可提高生产性。
(电子仪器)
图7(a)是表示本发明的电子仪器的一实例的立体图。该图示出的移动电话机1300，在框体的内部或显示部1301中具备使用上述方法得到的安装基板。图中，符号1302表示操作按钮1302，符号1303表示听筒，符号1304表示话筒。
图7(b)是(a)中示出的显示部1301的立体构成图。显示部1301具备在由液晶显示装置或有机EL显示装置构成的显示面板1311的一端，连接安装了电子器件1312的安装基板1313构成的构成。而且，在该安装基板1313上，适用使用本发明的安装方法安装电子器件的安装基板，在安装基板上薄型地安装电子器件，所以可实现移动电话机1300的薄型化、小型化。
所述实施方式的安装基板不限于所述移动电话机，还可适用于电子图书、个人计算机、数码摄像机、液晶电视、取景器型或监听直视型录像机、汽车驾驶导向装置、寻呼机、电子记事本、台式计算器、文字处理机、终端站、可视电话、POS终端、具备触摸面板的仪器等各种电子仪器。既便在任一电子仪器中，通过适用本发明的安装基板，也可实现薄型化、小型化。另外，所述实施方式的安装基板不限于液晶装置，可作为有机EL装置、等离子体光显示装置(PDP)、电场放射显示器(FED)等光电学装置等电子仪器的零件等而适用。

Claims (16)

1、一种安装基板，在挠性基板上安装具有具备连接端子的端子形成面的电子器件而构成，其特征在于：
所述连接端子直接或介由导电构件电连接在所述挠性基板上形成的配线图案；
与该安装基板的厚度方向上的中立面几乎一致地配置有所述端子形成面。
2、根据权利要求1所述的安装基板，其特征在于：
在该安装基板的厚度方向上，夹持所述电子器件的端子形成面、在两侧分别配置的构成构件，具有大致相等的弯曲弹性模数。
3、根据权利要求2所述的安装基板，其特征在于：
所述电子器件在面向所述挠性基板侧的状态下安装着所述端子形成面；
所述电子器件具有：与使所述挠性基板、和在该挠性基板与所述端子形成面之间形成的构成构件合在一起的弯曲弹性模数大致相等的弯曲弹性模数。
4、根据权利要求3所述的安装基板，其特征在于：
在所述配线图案上，形成有向所述电子器件侧突出的导体柱；
所述电子器件，介由以包围所述导体柱的方式设置的粘着层，安装于所述挠性基板上；
所述电子器件的连接端子电连接于所述导体柱上。
5、根据权利要求1至权利要求4的任一项所述的安装基板，其特征在于：
在所述挠性基板上的所述电子器件外侧的区域，形成有覆盖所述配线图案的绝缘层。
6、根据权利要求5所述的安装基板，其特征在于：
在所述电子器件上也形成有所述绝缘层。
7、根据权利要求2所述的安装基板，其特征在于：
所述电子器件，在面向与所述挠性基板相反侧安装所述端子形成面的同时，形成有覆盖该电子器件的绝缘层，
在所述电子器件上形成的绝缘层，具有与使所述电子器件、所述挠性基板、和在该电子器件与挠性基板之间设置的构成构件合在一起的弯曲弹性模数大致相等的弯曲弹性模数。
8、根据权利要求7所述的安装基板，其特征在于：
在所述电子器件的侧面部，形成有具有从该侧面部向外侧延伸的斜面部的倾斜件；
所述连接端子与配线图案，介由抵接所述倾斜件的斜面部设置的连接配线来电连接着。
9、根据权利要求2至权利要求8的任一项所述的安装基板，其特征在于：
在所述电子器件外侧的区域中，夹持该电子器件的端子形成面的延长面、在两侧分别配置的该安装基板的构成构件，互相具有大致相等的弯曲弹性模数。
10、一种安装基板，在挠性基板上安装具有具备连接端子的端子形成面的电子器件而构成，其特征在于：
所述电子器件相对所述挠性基板面向相反侧配置有所述端子形成面；
与所述电子器件的端子形成面相反侧的载置面，配置为与在该安装基板的厚度方向上的中立面几乎一致。
11、根据权利要求10所述的安装基板，其特征在于：
在该安装基板的厚度方向，夹持所述电子器件的载置面、在两侧分别配置的构成构件，具有大致相等的弯曲弹性模数。
12、根据权利要求10或权利要求11所述的安装基板，其特征在于：
在所述挠性基板上的所述电子器件外侧的区域中，形成有覆盖所述配线图案的绝缘层。
13、根据权利要求12所述的安装基板，其特征在于：
在所述电子器件的安装区域外侧的区域中，夹持延长所述载置面而构成的面、在两侧分别配置的构成构件具有大致相等的弯曲弹性模数。
14、根据权利要求12或权利要求13所述的安装基板，其特征在于：
在所述电子器件上也形成有所述绝缘层。
15、根据权利要求10至权利要求14的任一项所述的安装基板，其特征在于：
在所述安装基板的所述电子器件的侧面部，形成有具有从该侧面部向外侧延伸的斜面部的倾斜件；
所述连接端子和配线图案，介由与所述倾斜件的斜面部抵接设置的连接配线来电连接着。
16、一种电子仪器，其特征在于：
具备权利要求1～15的任一项所述的安装基板。
CNA2005101200326A 2004-11-11 2005-11-08 安装基板及电子仪器 Pending CN1790696A (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111047992A (zh) * 2013-06-13 2020-04-21 三星显示有限公司 具有改进的弯曲属性的显示装置及其制造方法
WO2020220595A1 (zh) * 2019-04-30 2020-11-05 云谷（固安）科技有限公司 一种显示面板及显示装置

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100862149B1 (ko) * 2007-02-06 2008-10-09 성균관대학교산학협력단 선택적 무전해 도금을 이용한 플렉서블 기판의 미세 금속배선 형성 방법
JP4273356B2 (ja) * 2007-02-21 2009-06-03 セイコーエプソン株式会社 半導体装置の製造方法
US7838410B2 (en) 2007-07-11 2010-11-23 Sony Corporation Method of electrically connecting element to wiring, method of producing light-emitting element assembly, and light-emitting element assembly
JP4396754B2 (ja) * 2007-07-11 2010-01-13 ソニー株式会社 配線への素子の電気的接続方法及び発光素子組立体の製造方法
JP4940063B2 (ja) * 2007-08-28 2012-05-30 株式会社東芝 半導体装置およびその製造方法
TWI387073B (zh) * 2007-10-08 2013-02-21 Chipmos Technologies Inc 晶片承載帶及晶片封裝結構
KR101004842B1 (ko) 2008-07-25 2010-12-28 삼성전기주식회사 전자 칩 모듈
CN101685212B (zh) * 2008-09-26 2012-08-29 群康科技(深圳)有限公司 液晶显示面板
JP2011009653A (ja) * 2009-06-29 2011-01-13 Seiko Epson Corp 半導体装置及びその製造方法
WO2012141246A1 (ja) * 2011-04-12 2012-10-18 凸版印刷株式会社 Ｉｃモジュールおよびｉｃカード
JP2013098184A (ja) * 2011-10-27 2013-05-20 Kyocera Corp 実装基板および電子装置
US20130181227A1 (en) * 2012-01-12 2013-07-18 King Dragon International Inc. LED Package with Slanting Structure and Method of the Same
US9276140B1 (en) * 2014-09-16 2016-03-01 Amazon Technologies, Inc. Imager module with interposer chip
KR101990148B1 (ko) * 2015-04-14 2019-06-19 에스케이하이닉스 주식회사 반도체 패키지
US10206288B2 (en) * 2015-08-13 2019-02-12 Palo Alto Research Center Incorporated Bare die integration with printed components on flexible substrate
WO2018142577A1 (ja) * 2017-02-03 2018-08-09 株式会社Ｆｕｊｉ 回路形成方法、および回路形成装置
US11690415B2 (en) 2018-01-19 2023-07-04 Feel The Same, Inc. Soft sensor and manufacturing method therefor, and hand-wearable device having soft sensor and manufacturing method therefor
US10908685B2 (en) * 2018-02-20 2021-02-02 Feel The Same, Inc. Hand-wearable device and manufacturing method therefor
FR3084556B1 (fr) 2018-07-30 2020-11-06 Commissariat Energie Atomique Structure electronique souple et son procede d'elaboration.
FR3126259A1 (fr) 2021-08-23 2023-02-24 Commissariat A L'energie Atomique Et Aux Energies Alternatives Structure électronique comprenant un film d’interconnexion

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02198896A (ja) 1989-01-27 1990-08-07 Toshiba Corp 携帯可能電子機器
US5474958A (en) * 1993-05-04 1995-12-12 Motorola, Inc. Method for making semiconductor device having no die supporting surface
JP3268615B2 (ja) 1993-12-27 2002-03-25 三菱電機株式会社 パッケージ部品の製造方法
US5719437A (en) * 1996-04-19 1998-02-17 Lucent Technologies Inc. Smart cards having thin die
KR100447035B1 (ko) * 1996-11-21 2004-09-07 가부시키가이샤 히타치세이사쿠쇼 반도체 장치의 제조방법
AU1174197A (en) * 1996-12-26 1998-07-31 Hitachi Limited Semiconductor device and method of manufacturing the same
US6255599B1 (en) 1997-08-18 2001-07-03 Ibm Relocating the neutral plane in a PBGA substrate to eliminate chip crack and interfacial delamination
US6829149B1 (en) * 1997-08-18 2004-12-07 International Business Machines Corporation Placement of sacrificial solder balls underneath the PBGA substrate
JPH11317067A (ja) 1999-02-19 1999-11-16 Seiko Epson Corp 携帯式半導体装置
JP3368876B2 (ja) * 1999-11-05 2003-01-20 株式会社東京精密 半導体チップ製造方法
JP3622665B2 (ja) 1999-12-10 2005-02-23 セイコーエプソン株式会社 接続構造、電気光学装置および電子機器
JP2001230001A (ja) 1999-12-10 2001-08-24 Seiko Epson Corp 接続構造、電気光学装置および電子機器
KR20010044277A (ko) * 2001-01-31 2001-06-05 김영선 방열지붕이 몰딩된 플라스틱 패캐지(피피엠시)
US7190008B2 (en) * 2002-04-24 2007-03-13 E Ink Corporation Electro-optic displays, and components for use therein
JP4243077B2 (ja) 2002-07-23 2009-03-25 株式会社ルネサステクノロジ 半導体装置およびその製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111047992A (zh) * 2013-06-13 2020-04-21 三星显示有限公司 具有改进的弯曲属性的显示装置及其制造方法
CN111047992B (zh) * 2013-06-13 2021-11-12 三星显示有限公司 具有改进的弯曲属性的显示装置及其制造方法
WO2020220595A1 (zh) * 2019-04-30 2020-11-05 云谷（固安）科技有限公司 一种显示面板及显示装置

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