CN1761056A - 互连结构及其形成方法 - Google Patents

互连结构及其形成方法 Download PDF

Info

Publication number
CN1761056A
CN1761056A CNA2005100798239A CN200510079823A CN1761056A CN 1761056 A CN1761056 A CN 1761056A CN A2005100798239 A CNA2005100798239 A CN A2005100798239A CN 200510079823 A CN200510079823 A CN 200510079823A CN 1761056 A CN1761056 A CN 1761056A
Authority
CN
China
Prior art keywords
dielectric layer
opening
lining
interconnection structure
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2005100798239A
Other languages
English (en)
Other versions
CN100536124C (zh
Inventor
L·A·克莱文杰
T·J·多尔顿
L·C·休
C·E·默里
C·拉登斯
黄洸汉
杨智超
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Core Usa Second LLC
GlobalFoundries Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN1761056A publication Critical patent/CN1761056A/zh
Application granted granted Critical
Publication of CN100536124C publication Critical patent/CN100536124C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844Bottomless liners
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865Selective removal of parts of the layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
    • H01L23/53295Stacked insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

本发明提供了一种可以在BEOL中制造的互连结构,该互连结构与上述常规的互连结构相比,在正常芯片操作中表现良好的机械接触,并在各种可靠性测试中不发生故障。本发明的互连结构在位于层间介质层中的过孔底部具有弯折界面。具体地,本发明的互连结构包括:第一介质层,其中嵌有至少一个金属互连;第二介质层,位于所述第一介质层上,其中所述第二介质层具有至少一个开口,所述开口具有上线路区域和下过孔区域,所述下过孔区域包括弯折界面;至少一对衬里,位于所述至少一个开口的至少垂直壁上;以及导电材料,填充所述至少一个开口。

Description

互连结构及其形成方法
技术领域
本发明涉及半导体集成电路(ICs),尤其涉及具有修改的过孔底部结构的后段制程(BEOL)互连,该过孔底部结构增强了IC的可靠性。尤其是,本发明提供了具有弯折过孔互连结构的BEOL互连。本发明还涉及用于制造包括修改的过孔底部结构的半导体IC结构的方法。
背景技术
在半导体工业中,互连结构用于提供在IC芯片上的器件和整个封装之间的布线。参考例如美国专利5,071,518、5,098,860、5,354,712、5,545,927、5,891,802、5,899,740、5,904,565、5,933,753、6,181,012以及6,465,376。在该技术中,在半导体衬底表面上首先形成例如场效应晶体管(FET)的器件,然后在BEOL中形成互连结构。通常的互连结构包括至少一种介电常数为约4.0或更低的介质材料,其中嵌有过孔和/或线路形式的金属图形。所述互连结构可以是单镶嵌结构或双镶嵌结构。
图1A-1D示出了各种现有技术的双镶嵌结构。所示的每种双镶嵌结构包括第一介质100,其包括垂直于纸面延伸的金属互连或线路110。在第一介质100的表面上还包括第一构图的覆盖层120。第二介质130位于第一介质100的上面。第二介质130具有双镶嵌开口,其包括形成于其中的下部148和上部150。在现有技术中称下部148为过孔,而称上部150为线路。用于各级的介质通常包括二氧化硅、热固性聚亚芳基树脂、如掺碳氧化物(SiCOH)的有机硅酸盐玻璃或任何其它类型的混合的相关介质。过孔148与下面的互连110接触,而线路150延伸较长的距离以如特定设计布局的要求与IC的其它元件接触。在附图中,通常通过与用于蚀刻第二介质130不同的蚀刻化学试剂,已经除去了在过孔148的底部的覆盖层120的部分。构图的硬掩模122位于第二介质130的上面。
在现有技术中,通常在金属化之前,在所述结构的整个内部上沉积衬里140。衬里140可以是如图1A和1C所示的单层,或者是如图1B和1D所示的多层140、145。在图1C和1D中,衬里140不位于过孔148的底部水平表面上。衬里140、145由例如Ta、Ti和W的难熔金属、或例如TaN、TiN和WN的难熔金属氮化物构成。可以使用未具体示出的可选粘合层以增强衬里与第二介质层130的接合。
然后沉积例如Al、W、Cu或其合金的导电材料(未具体示出),以完全填充开口,而提供导电填充的过孔和导电填充的线路。
在图1A-1D中示出的现有技术的互连结构的一个主要问题是,在正常芯片工作温度下难于获得良好的机械接触。另外,现有技术的互连结构在可靠性测试中时常表现开路或高阻接合。从而,需要提供新的改进的互连结构以避免上述问题。也就是说,需要互连结构在正常芯片工作中具有并保持良好的机械接触,并在例如热循环和高温烘烤的各种可靠性测试中不出现故障。
发明内容
本发明提供了一种可以在BEOL中制造的互连结构,该互连结构与上述常规的互连结构相比,在正常芯片操作中表现良好的机械接触,并在各种可靠性测试中不发生故障。本发明的互连结构在位于层间介质层中的过孔底部具有弯折界面。
概括的说,本发明的互连结构包括:
第一介质层,其中嵌有至少一个金属互连;
第二介质层,位于所述第一介质层上,其中所述第二介质层具有至少一个开口,所述开口具有上线路区域和下过孔区域,所述下过孔区域包括弯折界面;
至少一对衬里,位于所述至少一个开口的至少垂直壁上;以及导电材料,填充所述至少一个开口。
这里使用的术语“弯折界面”表示如图8和9所示的台阶形状的界面结构80。
本发明还提供了一种用于制造上述过孔弯折界面互连结构的方法。具体地,概括的说,本发明的方法包括以下步骤:
在其中嵌有金属互连的第一介质层上形成第二介质层;
在所述第二介质层中形成至少一个开口,所述开口延伸到所述第一介质层中的所述金属互连;
在所述至少一个开口中形成衬里材料;
在所述至少一个开口的底部表面上局部除去所述衬里材料,以形成弯折界面,而同时沉积第二衬里;以及
在包括所述弯折界面的所述至少一个开口中形成导电材料。
附图说明
图1A-1D(通过截面图)示出了各种现有技术的双镶嵌互连结构。
图2(通过截面图)示出了在第二介质层中形成至少一个开口之后的本发明的双镶嵌结构。
图3(通过截面图)示出了在至少一个开口中形成衬里材料之后的图2的双镶嵌结构。
图4(通过截面图)示出了在同时进行蚀刻和沉积工艺期间的图3的双镶嵌结构。
图5(通过截面图)示出了在已经进行了图4中的同时蚀刻和沉积工艺之后的双镶嵌结构。
图6(通过截面图)示出了在可选的溅射工艺期间的图5的双镶嵌结构。
图7(通过截面图)示出了在已经进行了图6中的可选溅射步骤之后的双镶嵌结构。
图8是图6所示的双镶嵌结构的放大图,强调了在用导电材料填充至少一个开口之后,在底部过孔表面中形成的弯折界面。
图9是图7所示的开放底部的双镶嵌结构的放大图,强调了在用导电材料填充至少一个开口之后,在底部过孔表面中形成的弯折界面。
图10(通过截面图)示出了在重复如图4所示的同时蚀刻和沉积工艺以在至少一个开口中沉积三层衬里之后的实施例。
具体实施方式
下面将通过参考图2-10更详细地描述本发明,本发明提供了一种互连结构及其制造方法,该互连结构具有修改的过孔底部结构用于提高可靠性。注意,图2-10用于说明性目的,从而没有按比例绘制。
首先参考如图2所示的局部互连结构,其包括第一(或下)介质层100以及可选的构图的覆盖层120,在第一介质层100的表面中嵌有导电互连110,覆盖层120具有暴露在第一介质层100中设置的导电互连110的表面的开口。图2中所示的局部互连结构还包括第二介质层130,其具有可选的构图的硬掩模122,所述硬掩模122位于第二介质层130的表面上。第二介质层130具有至少一个开口,所述开口包括上线路区域150和底部过孔区域148。
通过首先在包括至少一个半导体器件(未示出)的衬底(未示出)上形成第一介质层100,形成局部互连结构。所述至少一个半导体器件包括例如PFET、NFET或其组合。通过沉积工艺形成第一介质层100,所述工艺包括例如化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)、化学溶液沉积或旋涂。
第一介质层100包括介电常数k为约4.0或更小的任何绝缘体(多孔或无孔)。介电常数在上述范围中的所述介质材料的说明性实例包括但不限于:SiO2、热固性聚亚芳基树脂、有机硅酸盐玻璃(OSG)及其它类似绝缘体,其中所述有机硅酸盐玻璃例如包括Si、C、O和H原子的掺碳氧化物。这里使用的术语“聚亚芳基”表示芳基片段或惰性取代的芳基片段,其通过键、稠合环、或例如氧、硫、砜、亚砜、羰基等的惰性连接基而连接。
第一介质层100的厚度可以根据采用的绝缘体的类型以及用于沉积所述绝缘体的工艺的类型而变化。通常,第一介质层100的厚度为从约50至约500nm,尤其为从约100至约300nm。
嵌入第一介质层100中的金属互连100垂直于纸面延伸。金属互连110由包括如下的导电金属构成:例如铜(Cu)、铝(Al)、以及钨(W)、或包括至少一种导电金属的合金。在优选实施例中,金属互连110由Cu构成。
通过光刻和蚀刻在第一介质层100的表面中形成金属互连110。光刻步骤包括:在第一介质层100的表面上形成抗蚀剂材料的覆盖层(未示出),将覆盖抗蚀剂材料暴露于辐射图形,并利用常规抗蚀剂显影剂将图形显影到抗蚀剂中。蚀刻步骤包括任何蚀刻工艺,其选择性地除去下面的第一介质层100的一些暴露部分。例如,在本发明此处使用的蚀刻包括干蚀刻工艺,例如反应离子蚀刻、离子束蚀刻、等离子体蚀刻或其组合。光刻和蚀刻步骤在第一介质层100中限定了开口,随后将在所述开口中形成金属互连110。
接着,利用常规的沉积工艺在至少一个开口中形成如上述的导电金属,所述工艺包括但不限于:CVD、PECVD、溅射、化学溶液沉积或镀覆。在沉积导电金属后,可以采用例如化学机械抛光(CMP)或研磨的常规平面化工艺。所述平面化工艺提供了这样的结构,其中金属互连110的上表面基本与第一介质层100的上表面共面。
在一些实施例中,当采用Cu时,在形成金属互连110后,在第一介质层100的表面上沉积覆盖层120。可选的覆盖层120包括氮化物、氧氮化物或其任意组合。通过沉积工艺或热氮化或氧氮化工艺形成可选的覆盖层120。可选覆盖层120的厚度通常为约5至约90nm,尤其为约20至约60nm。
当在第一介质层100中设置导电互连110(包括或不包括覆盖层120)后,形成第二介质层130,其包括与第一介质层100相同或不同的介质材料。利用用于形成第一介质层100的上述沉积工艺中的一种形成第二介质层130。第二介质层130的厚度可以根据采用的介质材料的类型以及用于形成所述介质层的工艺而变化。通常,第二介质层130的厚度为约200至约900nm,尤其为约400至约700nm。
然后,在第二介质层130上形成可选硬掩模122。通常当在第二介质层130中嵌入Cu时使用可选硬掩模层122。可选硬掩模122由与覆盖层120相同或不同的材料构成。可选硬掩模122的厚度在上述覆盖层120的厚度范围内。
然后,在可选硬掩模层122或第二介质层130上形成另一抗蚀剂材料(未示出),并然后使用光刻以提供构图的抗蚀剂材料。此处形成的图形为过孔图形。然后,将过孔图形转移到可选硬掩模122(如果存在),并接着转移到第二介质层130。通常在蚀刻可选硬掩模122后除去构图的抗蚀剂。过孔148延伸到导电互连110的表面。因此,如果存在覆盖层120,其在本发明的该步骤中被蚀刻。该蚀刻步骤类似于上述在形成导电互连110中的蚀刻步骤。尤其是,该蚀刻步骤选择性地蚀刻硬掩模122、第二介质层130、以及覆盖层120(如果存在),并停止于导电互连110的表面上。
然后通过光刻施加并构图另一抗蚀剂材料,以提供利用蚀刻工艺转移到硬掩模122和部分第二介质层130的线路图形。在第二介质层130的上部形成线路图形。在图2中,标号150表示线路。注意,线路150和过孔148在第二介质130中形成延伸到导电互连110的上表面的开口。
在本发明的一些实施例中,可以首先形成线路150,然后形成过孔148。
然后,在上述开口中的所有暴露表面(垂直和水平)上形成第一衬里140,以提供如图3所示的结构。通过包括但不限于如下的任何沉积工艺形成第一衬里140:CVD、PECVD、溅射、化学溶液沉积或镀覆。第一衬里140由任何可以用作阻挡层的材料构成,以防止导电材料通过其扩散。该阻挡层材料的说明性实例包括例如Ta、Ti、W、Ru的难熔金属,或其氮化物,例如TaN、TiN、WN。第一衬里140还可以包括TiNSi。第一衬里140的厚度通常为约5至约60nm,尤其为约10至约40nm。
图4示出了当同时从开口中的基本所有水平表面蚀刻第一衬里140并沉积第二衬里材料时的结构。在图4中,标号50表示用于从开口中的基本所有水平表面蚀刻第一衬里140的溅射离子,而标号75表示将要沉积的第二衬里的金属中性粒子。尤其是,在离子轰击的同时沉积第二衬里,所述离子轰击用于从开口中的基本所有水平表面蚀刻第一衬里。用于离子轰击中的气体包括如下的一种:Ar、He、Ne、Xe、N2、H2、NH3、或N2H2。在该步骤中形成的第二衬里包括Ta、TaN、Ti、TiN、TiNSi、W、WN、或Ru。
因为场区(field)和沟槽底部比过孔底部148'具有更高的金属中性粒子沉积速率,因此在这些区域中可以获得负蚀刻速率,而在过孔底部148’中保持正蚀刻速率。从而,气体溅射从过孔底部局部除去第一沉积衬里140和下面的互连110,而没有破坏其它区域,即场区和沟槽底部。
图5示出了在同时进行图4中所示的离子蚀刻和金属中性粒子沉积工艺后的互连结构。如图所示,离子轰击即蚀刻没有从底部过孔表面148完全除去第一衬里140。而是,在过孔的底部壁上保留部分衬里140。在过孔148的底部壁内保留的部分第一衬里提供了本发明结构中的弯折界面80。图5还示出了在沉积第二衬里145后的互连结构。第二衬里145覆盖线路150的延伸水平表面,以适当地限制导电材料以使其随后形成于开口(例如弯折过孔148和线路150)中。可以使少量的第一衬里140保留在沟槽底部150中(未示出)。现在弯折过孔148的底部表面被示为只是局部地被第二衬里145覆盖,以说明在该区域不必完全覆盖。也就是说,不需要完全覆盖弯折过孔148,即,可以用第二衬里145完全覆盖或局部覆盖。因为在上衬里区域150中的沉积速率通常比在过孔148的底部的大,因此,第二衬里145通常在线路150中具有比过孔148更好(更厚)的覆盖。
图6示出了可选的第二方向离子轰击步骤,其可以用于从弯折过孔148的底部壁除去第二衬里145,以提供如图7所示的结构。可选的第二离子轰击步骤从而提供了如图7所示具有开口的弯折过孔底部的结构。因为第二衬里145通常比随后将要沉积在开口(过孔148和线路150)中的导电材料具有更大的电阻,并可能在过孔底部沉积杂质,这都增加了接点的电阻,因此优选采用该可选的第二离子轰击步骤。
利用上述的一种气体进行可选的第二离子轰击步骤,并且用于可选步骤的条件包括5至30nm的氧化硅等同去除厚度。
然后,如在图8和9中所示,在开口内沉积导电材料以完全填充弯折过孔148和线路150。在这些附图中以标号170表示导电材料。导电材料170包括多晶硅、导电金属、包括至少一种导电金属的合金、导电金属的硅化物或其组合。优选,导电材料170是例如Cu、W或Al的导电金属。在一个尤其优选的实施例中,导电材料170由Cu构成。利用包括但不限于如下的常规沉积工艺在开口中形成导电材料170:CVD、PECVD、溅射、化学溶液沉积或镀覆。在沉积后,可以采用平面化工艺,使得导电材料170的上表面基本与第二介质层130的上表面或与可选硬掩模122(如果存在)的上表面共面。注意,图8和9是强调弯折过孔148的放大图,从而未示出互连结构的上部区域。
图10示出了在重复图4所示的工艺两次后的所得结构。在该实施例中,在互连结构中存在三个衬里140、145和147。注意,在包括衬里140和145的过孔底部形成弯折界面。衬里147由与衬里145相同或不同的材料构成。注意,本发明不局限于只将同时蚀刻和金属中性粒子沉积工艺重复两次,而是可以将该步骤重复任何次数。然而,对重复蚀刻和沉积步骤的限制为,其受限于弯折过孔148的宽度。
注意,在上述附图中只示出了单个互连110和单个开口。尽管示出存在单个互连110和单个开口,但是本发明考虑在互连结构中形成多个互连和开口。而且,本发明还考虑在如图8和9所示的结构上面形成附加的包括嵌入导电材料的介质层,以提供多级互连结构。
尽管参考本发明的优选实施例具体示出和描述了本发明,但是本领域的技术人员应该理解,在不偏离本发明的精神和范围的情况下,可以进行形式和细节上的上述和其它变化。因此,本发明并不局限于上述和示出的具体形式和细节,而落入所附权利要求书的范围中。

Claims (30)

1.一种互连结构,包括:
第一介质层,其中嵌有至少一个金属互连;
第二介质层,位于所述第一介质层上,其中所述第二介质层具有至少一个开口,所述开口具有上线路区域和下过孔区域,所述下过孔区域包括弯折界面;
至少一对衬里,位于所述至少一个开口的至少垂直壁上;以及
导电材料,填充所述至少一个开口。
2.根据权利要求1的互连结构,其中所述金属互连包括导电金属或金属合金。
3.根据权利要求2的互连结构,其中所述金属为Cu、W或Al。
4.根据权利要求1的互连结构,其中所述金属互连包括Cu。
5.根据权利要求1的互连结构,其中所述第一介质层的介电常数为约4.0或更小。
6.根据权利要求5的互连结构,其中所述第一介质层包括SiO2、聚亚芳基树脂或有机硅酸盐玻璃。
7.根据权利要求1的互连结构,还包括在所述第一介质层的表面上的构图的覆盖层,所述构图的覆盖层具有暴露所述金属互连的表面部分的开口。
8.根据权利要求7的互连结构,其中所述构图的覆盖层包括氮化物、氧氮化物或其组合。
9.根据权利要求1的互连结构,其中所述第二介质层的介电常数为约4.0或更少。
10.根据权利要求9的互连结构,其中所述第二介质层包括SiO2、聚亚芳基树脂或有机硅酸盐玻璃。
11.根据权利要求1的互连结构,还包括在所述第二介质层的表面上的构图的硬掩模。
12.根据权利要求11的互连结构,其中所述构图的硬掩模包括氮化物、氧氮化物或其组合。
13.根据权利要求1的互连结构,其中所述至少一对衬里包括第一衬里和第二衬里,所述第一衬里和第二衬里包括选自如下的相同或不同的扩散阻挡材料:难熔金属、难熔金属的氮化物以及TiNSi。
14.根据权利要求13的互连结构,还包括第三衬里,所述第三衬里包括与所述第一或第二衬里相同或不同的扩散阻挡材料。
15.根据权利要求1的互连结构,其中所述至少一对衬里在所述金属互连的表面部分上延伸。
16.根据权利要求1的互连结构,其中所述至少一对衬里基本不存在于所述下过孔区域的底部壁上。
17.根据权利要求1的互连结构,其中所述导电材料包括多晶硅、导电金属、包括一种导电金属的合金或导电金属的硅化物。
18.根据权利要求1的互连结构,其中所述导电材料包括Cu。
19.一种互连结构,包括:
第一介质层,其中嵌有至少一个Cu互连;
构图的覆盖层,位于所述第一介质层上,所述构图的覆盖层具有暴露所述Cu互连的表面的开口;
第二介质层,位于所述构图的覆盖层上,其中所述第二介质层具有至少一个开口,所述开口具有上线路区域和下过孔区域,所述下过孔区域包括弯折界面;
至少一对衬里,位于所述至少一个开口的至少垂直壁上;
构图的硬掩模,位于所述第二介质层上;以及
Cu,填充所述至少一个开口。
20.一种形成具有修改的过孔底部结构的互连结构的方法,包括以下步骤:
在其中嵌有金属互连的第一介质层上形成第二介质层;
在所述第二介质层中形成至少一个开口,所述开口延伸到所述第一介质层中的所述金属互连;
在所述至少一个开口中形成衬里材料;
在所述至少一个开口的底部表面上局部除去所述衬里材料,以形成弯折界面,而同时沉积第二衬里;以及
在包括所述弯折界面的所述至少一个开口中形成导电材料。
21.根据权利要求20的方法,其中所述形成所述至少一个开口的步骤包括形成过孔开口和线路开口,其中在形成所述线路开口之前形成所述过孔开口。
22.根据权利要求20的方法,其中所述形成所述至少一个开口的步骤包括形成过孔开口和线路开口,其中在形成所述过孔开口之前形成所述线路开口。
23.根据权利要求20的方法,其中在形成所述第二介质层之前,在所述第一介质层的表面上形成构图的覆盖层。
24.根据权利要求20的方法,其中所述局部除去所述衬里材料并同时沉积的步骤包括离子轰击和溅射。
25.根据权利要求24的方法,其中所述离子轰击包括以下的一种:Ar、He、Ne、Xe、N2、H2、NH3或N2H2
26.根据权利要求24的方法,其中所述离子轰击保留在所述过孔的底部壁上的部分所述第一衬里,以形成所述弯折界面。
27.根据权利要求20的方法,其中将所述局部除去所述衬里材料并同时沉积的步骤重复至少一次。
28.根据权利要求20的方法,还包括溅射工艺,其在所述局部除去所述衬里材料并同时沉积的步骤之后进行。
29.根据权利要求20的方法,还包括在所述形成所述至少一个开口的步骤之前,在所述第二介质层上形成构图的硬掩模。
30.根据权利要求20的方法,其中所述金属互连和所述导电材料都包括Cu。
CNB2005100798239A 2004-10-14 2005-06-29 互连结构及其形成方法 Expired - Fee Related CN100536124C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/964,882 2004-10-14
US10/964,882 US7282802B2 (en) 2004-10-14 2004-10-14 Modified via bottom structure for reliability enhancement

Publications (2)

Publication Number Publication Date
CN1761056A true CN1761056A (zh) 2006-04-19
CN100536124C CN100536124C (zh) 2009-09-02

Family

ID=36179885

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005100798239A Expired - Fee Related CN100536124C (zh) 2004-10-14 2005-06-29 互连结构及其形成方法

Country Status (3)

Country Link
US (3) US7282802B2 (zh)
CN (1) CN100536124C (zh)
TW (1) TWI349989B (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101257000B (zh) * 2007-02-27 2010-06-09 国际商业机器公司 包括通孔的结构及其制造方法
CN101937902A (zh) * 2009-06-15 2011-01-05 瑞萨电子株式会社 半导体器件和用于制造半导体器件的方法
CN108172560A (zh) * 2016-11-29 2018-06-15 台湾积体电路制造股份有限公司 集成电路和用于制造集成电路的方法
CN109524348A (zh) * 2017-09-20 2019-03-26 格芯公司 基本规则区域中的完全对准的过孔
CN113228831A (zh) * 2018-10-29 2021-08-06 塞林克公司 柔性混合互连电路

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070126120A1 (en) * 2005-12-06 2007-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device
DE102006004412B3 (de) * 2006-01-31 2007-08-30 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Erhöhen der Ätzselektivität in einer Kontaktstruktur in Halbleiterbauelementen
US7439624B2 (en) 2006-05-18 2008-10-21 International Business Machines Corporation Enhanced mechanical strength via contacts
DE102007004860B4 (de) * 2007-01-31 2008-11-06 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer Kupfer-basierten Metallisierungsschicht mit einer leitenden Deckschicht durch ein verbessertes Integrationsschema
US8030778B2 (en) * 2007-07-06 2011-10-04 United Microelectronics Corp. Integrated circuit structure and manufacturing method thereof
JP2009111251A (ja) * 2007-10-31 2009-05-21 Tohoku Univ 半導体装置およびその製造方法
US20090179328A1 (en) * 2008-01-14 2009-07-16 International Business Machines Corporation Barrier sequence for use in copper interconnect metallization
US7892968B2 (en) * 2008-01-21 2011-02-22 International Business Machines Corporation Via gouging methods and related semiconductor structure
US20090200674A1 (en) * 2008-02-07 2009-08-13 International Business Machines Corporation Structure and method of forming transitional contacts between wide and thin beol wirings
US8283250B2 (en) * 2008-12-10 2012-10-09 Stats Chippac, Ltd. Semiconductor device and method of forming a conductive via-in-via structure
US7956463B2 (en) * 2009-09-16 2011-06-07 International Business Machines Corporation Large grain size conductive structure for narrow interconnect openings
US8551877B2 (en) * 2012-03-07 2013-10-08 Tokyo Electron Limited Sidewall and chamfer protection during hard mask removal for interconnect patterning
US9105638B2 (en) 2013-11-11 2015-08-11 International Business Machines Corporation Via-fuse with low dielectric constant
US20150255388A1 (en) 2014-03-09 2015-09-10 International Business Machines Corporation Enhancement of iso-via reliability
US20160071791A1 (en) * 2014-09-09 2016-03-10 Globalfoundries Inc. Multimetal interlayer interconnects
KR20160141034A (ko) * 2015-05-27 2016-12-08 삼성전자주식회사 반도체 소자 및 반도체 소자의 제조 방법
US10170358B2 (en) 2015-06-04 2019-01-01 International Business Machines Corporation Reducing contact resistance in vias for copper interconnects
US10586732B2 (en) 2016-06-30 2020-03-10 International Business Machines Corporation Via cleaning to reduce resistance
US9786603B1 (en) * 2016-09-22 2017-10-10 International Business Machines Corporation Surface nitridation in metal interconnects
KR102402670B1 (ko) 2017-06-26 2022-05-26 삼성전자주식회사 저항 구조체를 포함하는 반도체 소자
US10559492B2 (en) 2017-11-15 2020-02-11 Taiwan Semiconductor Manufacturing Company, Ltd. Patterning methods for semiconductor devices and structures resulting therefrom
US10886226B2 (en) * 2018-07-31 2021-01-05 Taiwan Semiconductor Manufacturing Co, Ltd. Conductive contact having staircase barrier layers
TWI764388B (zh) * 2020-04-27 2022-05-11 台灣積體電路製造股份有限公司 積體電路晶片及其形成方法
US11694926B2 (en) * 2020-04-27 2023-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier free interface between beol interconnects

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4495220A (en) * 1983-10-07 1985-01-22 Trw Inc. Polyimide inter-metal dielectric process
US4484979A (en) * 1984-04-16 1984-11-27 At&T Bell Laboratories Two-step anisotropic etching process for patterning a layer without penetrating through an underlying thinner layer
US4560436A (en) * 1984-07-02 1985-12-24 Motorola, Inc. Process for etching tapered polyimide vias
EP0241480B1 (en) * 1985-09-27 1991-10-23 Unisys Corporation Method of fabricating a tapered via hole in polyimide
US4902377A (en) * 1989-05-23 1990-02-20 Motorola, Inc. Sloped contact etch process
US5071518A (en) * 1989-10-24 1991-12-10 Microelectronics And Computer Technology Corporation Method of making an electrical multilayer interconnect
US5098860A (en) * 1990-05-07 1992-03-24 The Boeing Company Method of fabricating high-density interconnect structures having tantalum/tantalum oxide layers
US5354712A (en) * 1992-11-12 1994-10-11 Northern Telecom Limited Method for forming interconnect structures for integrated circuits
US5308415A (en) * 1992-12-31 1994-05-03 Chartered Semiconductor Manufacturing Pte Ltd. Enhancing step coverage by creating a tapered profile through three dimensional resist pull back
US5498889A (en) * 1993-11-29 1996-03-12 Motorola, Inc. Semiconductor device having increased capacitance and method for making the same
US5545927A (en) * 1995-05-12 1996-08-13 International Business Machines Corporation Capped copper electrical interconnects
US5933753A (en) * 1996-12-16 1999-08-03 International Business Machines Corporation Open-bottomed via liner structure and method for fabricating same
KR100243286B1 (ko) * 1997-03-05 2000-03-02 윤종용 반도체 장치의 제조방법
TW417249B (en) * 1997-05-14 2001-01-01 Applied Materials Inc Reliability barrier integration for cu application
US5904565A (en) * 1997-07-17 1999-05-18 Sharp Microelectronics Technology, Inc. Low resistance contact between integrated circuit metal levels and method for same
US5891802A (en) * 1997-07-23 1999-04-06 Advanced Micro Devices, Inc. Method for fabricating a metallization stack structure to improve electromigration resistance and keep low resistivity of ULSI interconnects
TW359884B (en) * 1998-01-07 1999-06-01 Nanya Technology Co Ltd Multi-level interconnects with I-plug and production process therefor
US6576547B2 (en) * 1998-03-05 2003-06-10 Micron Technology, Inc. Residue-free contact openings and methods for fabricating same
US6181012B1 (en) * 1998-04-27 2001-01-30 International Business Machines Corporation Copper interconnection structure incorporating a metal seed layer
US6203863B1 (en) * 1998-11-27 2001-03-20 United Microelectronics Corp. Method of gap filling
US6465376B2 (en) * 1999-08-18 2002-10-15 International Business Machines Corporation Method and structure for improving electromigration of chip interconnects
US6498091B1 (en) * 2000-11-01 2002-12-24 Applied Materials, Inc. Method of using a barrier sputter reactor to remove an underlying barrier layer
US6764940B1 (en) * 2001-03-13 2004-07-20 Novellus Systems, Inc. Method for depositing a diffusion barrier for copper interconnect applications
US20020171147A1 (en) * 2001-05-15 2002-11-21 Tri-Rung Yew Structure of a dual damascene via
US6613666B2 (en) * 2001-12-07 2003-09-02 Applied Materials Inc. Method of reducing plasma charging damage during dielectric etch process for dual damascene interconnect structures
US6887786B2 (en) * 2002-05-14 2005-05-03 Applied Materials, Inc. Method and apparatus for forming a barrier layer on a substrate
US6686662B2 (en) * 2002-05-21 2004-02-03 Agere Systems Inc. Semiconductor device barrier layer
US6713402B2 (en) * 2002-05-31 2004-03-30 Texas Instruments Incorporated Methods for polymer removal following etch-stop layer etch
KR100475931B1 (ko) * 2002-07-02 2005-03-10 매그나칩 반도체 유한회사 반도체 소자의 다층 배선 형성방법
JP2004063556A (ja) * 2002-07-25 2004-02-26 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US6784096B2 (en) * 2002-09-11 2004-08-31 Applied Materials, Inc. Methods and apparatus for forming barrier layers in high aspect ratio vias
US6905958B2 (en) * 2003-07-25 2005-06-14 Intel Corporation Protecting metal conductors with sacrificial organic monolayers
US20050064701A1 (en) * 2003-09-19 2005-03-24 International Business Machines Corporation Formation of low resistance via contacts in interconnect structures
US20050118796A1 (en) * 2003-11-28 2005-06-02 Chiras Stefanie R. Process for forming an electrically conductive interconnect
US20060024953A1 (en) * 2004-07-29 2006-02-02 Papa Rao Satyavolu S Dual damascene diffusion barrier/liner process with selective via-to-trench-bottom recess

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101257000B (zh) * 2007-02-27 2010-06-09 国际商业机器公司 包括通孔的结构及其制造方法
CN101937902A (zh) * 2009-06-15 2011-01-05 瑞萨电子株式会社 半导体器件和用于制造半导体器件的方法
CN108172560A (zh) * 2016-11-29 2018-06-15 台湾积体电路制造股份有限公司 集成电路和用于制造集成电路的方法
CN108172560B (zh) * 2016-11-29 2020-09-22 台湾积体电路制造股份有限公司 集成电路和用于制造集成电路的方法
CN109524348A (zh) * 2017-09-20 2019-03-26 格芯公司 基本规则区域中的完全对准的过孔
CN109524348B (zh) * 2017-09-20 2023-05-30 格芯美国公司 基本规则区域中的完全对准的过孔
CN113228831A (zh) * 2018-10-29 2021-08-06 塞林克公司 柔性混合互连电路
US12052814B2 (en) 2018-10-29 2024-07-30 Cellink Corporation Flexible hybrid interconnect circuits

Also Published As

Publication number Publication date
US20080220608A1 (en) 2008-09-11
US20060081986A1 (en) 2006-04-20
US20070281469A1 (en) 2007-12-06
TW200629519A (en) 2006-08-16
US7282802B2 (en) 2007-10-16
US7906428B2 (en) 2011-03-15
TWI349989B (en) 2011-10-01
CN100536124C (zh) 2009-09-02

Similar Documents

Publication Publication Date Title
CN100536124C (zh) 互连结构及其形成方法
JP5089575B2 (ja) 相互接続構造体及びその製造方法
US6972254B1 (en) Manufacturing a conformal atomic liner layer in an integrated circuit interconnect
CN100576494C (zh) 利用保护性通路盖层形成半导体器件的双镶嵌布线的方法
US8110342B2 (en) Method for forming an opening
CN1728358A (zh) 双金属镶嵌互连的制造方法
CN101079409A (zh) 互连结构及其制造方法
US10431542B2 (en) Low resistance seed enhancement spacers for voidless interconnect structures
JP2007251164A (ja) 相互接続構造体、半導体構造体および相互接続構造体の形成方法(相互接続用途のための耐酸化性シード層の形成)
CN101038905A (zh) 具有阻挡层冗余特征的互连结构
JP2008004939A (ja) デバイス、方法(mimキャパシタおよびその製造方法)
US6495448B1 (en) Dual damascene process
CN1956165A (zh) 互连中的气隙的横向分布控制
CN1324677C (zh) 改善蚀刻中止层与金属导线间的粘着性的工艺与结构
TWI231564B (en) Cu damascene process and structure
JP5285612B2 (ja) 半導体デバイスおよび相互接続構造体の形成方法
US7196423B2 (en) Interconnect structure with dielectric barrier and fabrication method thereof
KR20010019643A (ko) 저유전율 절연막을 갖는 다층 금속배선의 형성방법
US10665541B2 (en) Biconvex low resistance metal wire
CN101640184A (zh) 半导体器件及其制造方法
US20090057271A1 (en) Manufacturing method of metal interconnection
US20070210406A1 (en) Semiconductor device and method of manufacturing the same
TW492144B (en) Manufacturing method of metal interconnect
KR100784105B1 (ko) 반도체 소자의 제조 방법
Balakrishnan et al. Process integration of interconnects

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20171103

Address after: Grand Cayman, Cayman Islands

Patentee after: GLOBALFOUNDRIES INC.

Address before: American New York

Patentee before: Core USA second LLC

Effective date of registration: 20171103

Address after: American New York

Patentee after: Core USA second LLC

Address before: American New York

Patentee before: International Business Machines Corp.

TR01 Transfer of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090902

Termination date: 20190629

CF01 Termination of patent right due to non-payment of annual fee