CN1741274A - 集成电路元件及其形成方法 - Google Patents

集成电路元件及其形成方法 Download PDF

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CN1741274A
CN1741274A CNA2005100646823A CN200510064682A CN1741274A CN 1741274 A CN1741274 A CN 1741274A CN A2005100646823 A CNA2005100646823 A CN A2005100646823A CN 200510064682 A CN200510064682 A CN 200510064682A CN 1741274 A CN1741274 A CN 1741274A
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layer
integrated circuit
contact hole
circuit component
barrier layer
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CN100403540C (zh
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吴振诚
蔡宏骏
林大文
张文
郑双铭
梁孟松
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明是有关于一种集成电路元件及其形成方法，在基材上形成闸介电层和闸电极。接着沿着闸介电层和闸电极两侧形成一对间隙壁，间隙壁的较佳的基本组成材质为SiCO或SiCN。接着形成源极和汲极。在源极/汲极及间隙壁区域形成接触窗蚀刻阻绝层(CES)，CES层较佳的基本组成材质为SiCO或SiCN。接着形成层间介电层(ILD)在CES层上。此外，此种具有低k值的SiCO和SiCN材料可在较高的沉积速率及较低的沉积温度下进行沉积。使用含SiCO和SiCN的材料的MOS元件特性，不管是在外缘电容、接触电阻、片电阻、起始电压和遗漏电流等方面，和过去习知工艺相比较均有获得改善。

Description

集成电路元件及其形成方法
技术领域
本发明涉及一种一般的半导体元件，特别是涉及一种关于半导体元件中的接触窗蚀刻阻绝层(contact etch stop，CES)的集成电路元件及其形成方法。
背景技术
在深次微米微电子制造中，氮化硅(silicon nitride，SiN)于接触窗蚀刻过程中被广泛地应用为阻绝层(stop layer)。在现有习知的技术中，层间介电层(inter-layer dielectric，ILD)是做为金属氧化物半导体(metal-oxide semiconductor，MOS)元件和位于其上的金属线之间的绝缘材料。接触窗孔洞(contact openings)则穿过ILD层到源极/汲极(source/drain)和闸极(gate)。由于ILD层相当地厚，因此难以控制蚀刻过程而没有过蚀刻(over etch)。形成ILD层之前，先形成接触窗蚀刻阻绝层。因此施行第一高选择性蚀刻来蚀刻ILD层，并停止在蚀刻阻绝层(etchstop)上。然后施行第二选择性蚀刻，在蚀刻阻绝层后，以曝露出位于其下层。
在传统的技术领域中使用氮化硅膜当蚀刻阻绝层有许多的缺点。一般所知氮化硅具有高介电质常数(即所谓的k值)，约为7.5～8。高k值会增高寄生电容(parasitic capacitance)而降低元件的性能。此外，氮化硅膜的低沉积速率以及高沉积温度并不是理想的制程特性。
由此可见，上述现有的使用氮化硅膜当蚀刻阻绝层在结构、方法与使用上，显然仍存在有不便与缺陷，而亟待加以进一步改进。为了解决现有的使用氮化硅膜当蚀刻阻绝层存在的问题，相关厂商莫不费尽心思来谋求解决之道，但长久以来一直未见适用的设计被发展完成，而一般产品又没有适切的结构能够解决上述问题，此显然是相关业者急欲解决的问题。
有鉴于上述现有的使用氮化硅膜当蚀刻阻绝层存在的缺陷，本发明人基于从事此类产品设计制造多年丰富的实务经验及专业知识，并配合学理的运用，积极加以研究创新，以期创设一种新的集成电路元件及其形成方法，能够改进一般现有的使用氮化硅膜当蚀刻阻绝层，使其更具有实用性。经过不断的研究、设计，并经反复试作样品及改进后，终于创设出确具实用价值的本发明。
发明内容
本发明的目的在于，克服现有使用氮化硅膜当蚀刻阻绝层存在的缺陷，而提供一种新型的集成电路元件及其形成方法，所要解决的技术问题是使具有低k值的SiCO和SiCN材料可在较高的沉积速率及较低的沉积温度下进行沉积，从而更加适于实用。
本发明的目的及解决其技术问题是采用以下技术方案来实现的。依据本发明提出的一集成电路元件，其包含：一基材有一表面；一闸介电层位于该基材表面上；一闸电极位于在该闸介电层上；一对间隙壁位于沿着该闸电极及该闸介电层的两侧；一对源极/汲极区域位于该闸电极的相反两侧；一接触窗蚀刻阻绝层位于该源极/汲极区及该间隙壁上，其中该接触窗蚀刻阻绝层的材料是选自由氧碳化硅(SiCO)和氮碳化硅(SiCN)所组成的族群；一金属层间介电质层位于该接触窗蚀刻阻绝层上方；以及一传导插塞位于该金属层间介电质层上方。
本发明的目的及解决其技术问题还采用以下技术措施来进一步实现。
前述的集成电路元件，其中所述的元件更包括一粘着层位于该接触窗蚀刻阻绝层上方。
前述的集成电路元件，其中所述的粘着层材料为碳化硅。
前述的集成电路元件，其中所述的粘着层厚度约为20埃到50埃。
前述的集成电路元件，其中所述的接触窗蚀刻阻绝层的k值约小于7.0。
前述的集成电路元件，其中所述的接触窗蚀刻阻绝层的厚度约100埃到1000埃。
前述的集成电路元件，其中所述的接触窗蚀刻阻绝层内应力约-3Gpa到3Gpa。
本发明的目的及解决其技术问题还采用以下技术方案来实现。依据本发明提出的一种集成电路元件的形成方法，其至少包括：形成一闸介电层在一基材表面上；形成一闸电极在该闸介电层上；形成一对间隙壁于沿着该闸电极及该闸介电层的两侧；形成一对源极/汲极区域于邻近的该些间隙壁；形成一接触窗蚀刻阻绝层于该源极/汲极区域上方，其中该接触窗蚀刻阻绝层的材料是选自由氧碳化硅(SiCO)和氮碳化硅(SiCN)所组成的族群；形成一金属层间介电层于该接触窗蚀刻阻绝层上方；以及形成一导体于该金属层间介电质层内。
本发明的目的及解决其技术问题还采用以下技术措施来进一步实现。
前述的集成电路元件的形成方法，其中形成所述的接触窗蚀刻阻绝层的方法为一化学气相沉积法。
前述的集成电路元件的形成方法，其中沉积所述的接触窗蚀刻阻绝层的一前驱物为含碳的材料。
前述的集成电路元件的形成方法，其中所述的前驱物包含四甲基硅甲烷和三甲基硅甲烷。
前述的集成电路元件的形成方法，其中所述的化学气相沉积法沉积温度约为300℃到800℃。
前述的集成电路元件的形成方法，其更包含一氢电浆预处理步骤执行于形成该接触窗蚀刻阻绝层之前。
前述的集成电路元件的形成方法，其更包含一氨电浆预处理步骤执行于形成该接触窗蚀刻阻绝层之前。
前述的集成电路元件的形成方法，其更包含形成一含SiC的粘着层于形成该接触窗蚀刻阻绝层之前。
本发明与现有技术相比具有明显的优点和有益效果。由以上技术方案可知，本发明的主要技术内容如下：
为了达到上述目的，本发明提供了一种集成电路元件及其形成方法。在本发明的较佳实施例中，形成接触窗蚀刻阻绝层的基本组成材料为氧碳化硅(silicon oxycarbide，SiCO；或称硅碳含氧化物)，以及氮碳化硅(silicon carbonitride，SiCN；或称硅碳含氮化物)，例如碳掺杂氧化物(carbon doped oxide，CDO)和氮掺杂碳化硅物(nitride doped siliconcarbide，NDC)。
SiCO和SiCN材料的k值比SiN材料的k值低。此外，此种具有低k值的材料可在较高的沉积速率及较低的沉积温度下进行沉积。使用含SiCO和SiCN的材料的MOS元件特性，不管是在外缘电容(outer fringingcapacitance)、接触电阻(contact resistance)、片电阻(sheetresistance)、起始电压(threshold voltage)和遗漏电流(leakagecurrent)等方面，和过去习知工艺相比较均有获得改善。
本发明的一较佳实施例中，在基材上形成闸介电层(gate dielectric)和闸电极(gate electrode)，接着沿着闸介电层和闸电极两侧形成一对间隙壁(spacers)，然后形成源极/汲极。CES层形成在源极/汲极及间隙壁区域，CES层较佳的基本组成材质为SiCO或SiCN，接着形成ILD层在CES层上，再形成接触窗孔洞，并于接触孔洞中形成接触窗插塞(contact plugs)。
以SiCO或SiCN为基本组成材质的材料，也可用于形成MOS元件中的其他部分，例如间隙壁、闸阶梯外形(gate step features)和ILD层。
经由上述可知，本发明集成电路元件及其形成方法，在基材上形成闸介电层和闸电极。接着沿着闸介电层和闸电极两侧形成一对间隙壁，间隙壁的较佳的基本组成材质为SiCO或SiCN。接着形成源极和汲极。在源极/汲极及间隙壁区域形成接触窗蚀刻阻绝层(CES)，CES层较佳的基本组成材质为SiCO或SiCN。接着形成层间介电层(ILD)在CES层上。
借由上述技术方案，本发明集成电路元件及其形成方法至少具有下列优点：
其具有低k值的SiCO和SiCN材料可在较高的沉积速率及较低的沉积温度下进行沉积。使用含SiCO和SiCN的材料的MOS元件特性，不管是在外缘电容、接触电阻、片电阻、起始电压和遗漏电流等方面，和过去习知工艺相比较均有获得改善。
综上所述，本发明特殊的集成电路元件及其形成方法，其具有上述诸多的优点及实用价值，并在同类产品及方法中未见有类似的结构设计及方法公开发表或使用而确属创新，其不论在产品结构、方法或功能上皆有较大的改进，在技术上有较大的进步，并产生了好用及实用的效果，且较现有的使用氮化硅膜当蚀刻阻绝层具有增进的多项功效，从而更加适于实用，而具有产业的广泛利用价值，诚为一新颖、进步、实用的新设计。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂，以下特举较佳实施例，并配合附图，详细说明如下。
附图说明
图1到图7所示为依照本发明一较佳实施例的MOS晶体管制造阶段的剖面图。
图8a和图8b所示为边缘电容的示意图。
图9所示为边缘电容为复晶硅和源极/汲极间之间隔距离的函数图形。
图10所示为累积或然率为n+掺杂源极/汲极和接触插塞之间接触电阻的函数图形。
图11所示为累积或然率为p+掺杂源极/汲极和接触插塞之间接触电阻的函数图形。
2：硅基材                   4：闸介电层
6：闸电极                   8：间隙壁
9：源极                     10：半导体材料
11：汲极                    14：粘着层
16：接触窗蚀刻阻绝层        18：层间介电层层
20：图案化之的抗微影材料    24：接触窗插塞
30：边缘电容                32：边缘电容
42：复晶硅                  46：接触窗蚀刻阻绝层
48：间隙壁                  50：间隙壁
54：源极/汲极               60：接触窗插塞
62：复晶硅               66：接触窗蚀刻阻绝层
74：源极/汲极            73：复晶硅
80：电容                 13：硅化金属区域
d1：在图8a中复晶硅和接触窗插塞之间的距离
d2：在图8b中复晶硅和源极/汲极之间的距离
具体实施方式
本发明一较佳实施例使用SiCO和SiCN为基本组成材质的材料例如CDO和NDC来制造MOS元件。在较佳实施例中讨论制造过程的详细内容及MOS元件的测试结果。
请参阅图1到图7，所示为本发明的较佳实施例。图1所示为形成一闸极。在所示的较佳实施例中，基材2为硅基材。在其他较佳实施例中例如硅锗(SiGe)、体积半导体(bulk semiconductor)、应变半导体(strainedsemiconductor)、混成半导体(compound semiconductor)、多层半导体(milti-layer semiconductor)或硅绝缘体(silicon-on-insulatior，SOI)、应变硅绝缘体(SSOI)、应变硅锗绝缘体(S-SiGeOI)、硅锗绝缘体(SiGeOI)、锗绝缘体(GeOI)及其他类似的材料均可当作基材2。由习知工艺可知，部分基材例如通道区(channel areas)将会被轻微地掺杂n型或p型的掺质(dopant)。
闸介电层4沉积在基材2表面上，其材质较佳为氧化物(oxide)，形成闸介电层的方法为习知此工艺者所熟悉例如：热氧化法等方法。在另一较佳实施例中，因为氮化硅膜能有效地阻挡污染物扩散，所以较佳形成氮化硅膜方法为硅的热氮化法，也可藉由氮氢组成的电浆阳极氮化法或二氧化硅(SiO2)的热氮化法形成氮化硅膜。在另一较佳实施例中，闸介电层也可为氮氧介电层、含氧介电层、含氮介电层或结合上述的组合所形成的介电层。
请参阅图1，显示一闸电极6形成在闸介电层4上方，闸电极6较佳材料为复晶硅(polysilicon)，也可由其他材质形成例如金属或包含金属、半导体材料、金属氧化物以及硅化金属(silicides)的化合物。形成闸电极6的较佳方法为化学气相沉积法。复晶硅能作为罩幕以使闸极和源极/汲极重叠减到最小。此将提高元件性能。接着复晶硅被掺杂以降低元件的片电阻。又一较佳实施例中，形成闸电极6的材料可为非晶硅(amorphous silicon)、有传导性质的金属元素、有传导性质的金属元素的合金、有传导性质的硅化金属或氮化金属、或上述的任意组和。闸电极6和闸介电层4被图案化后形成闸极。
请参阅图2所示为有间隙壁的闸极。沿着闸介电层4和闸电极6的两侧形成一对间隙壁8。间隙壁8于接下来的自行对准金属硅化物(self-aligned silicide，通常简称为salicide)制程中作为自行对准罩幕。形成间隙壁的材料可为氧化物、氮化硅、氧氮化物或及上述的组合物。形成间隙壁8的方法为习知此工艺者所熟悉，例如以毯覆式沉积法(blanketdeposition)覆盖一介电层在包含基材2和闸电极6的整个区域上方，接着以非等方性蚀刻移除平行于表面的介电层并留下间隙壁8。
在一较佳实施例中，间隙壁基本组成材质为SiCO，例如碳掺杂氧化物(CDO)、含碳的氧化硅(SiOC)或氧掺杂碳化物(ODC；Oxide Doped Carbide)等。在另一较佳实施例中，间隙壁基本组成材质为SiCN，例如氮掺杂碳化硅物(NDC)。在后续形成CES层的介绍中会详细讨论形成含SiCO和SiCN材料层的细节。含SiCO和SiCN材料层的k值较佳为小于约5.0。因为典型的集成电路尺寸一直在减小，所以接触插塞(即分别连接到源极/汲极之具导电性的接触)和复晶硅的距离也在减少，以至于在闸复晶硅和源极/汲极间的外缘电容变得更明显。k值的减小可以帮助外缘电容减小，因此较佳为选用具有低k值介电质的材质。在一较佳实施例中，当间隙壁由含SiN的材料层(其k值为7.5)改变为含SiCO和SiCN的材料层(其k值为4.0)，外缘电容也会减小约4％到5％。
含SiCO和SiCN材料层并非只局限用在间隙壁。如果在元件的闸极构造中有一介电材料的阶梯外形位于一复晶硅层和另一层复晶硅层之间或是在复晶硅层和接触插塞之间。形成阶梯外形的理想材料为含SiCO和SiCN的材质。阶梯外形为在硅基材上垄起的特性。如果邻近元件之间隙壁之间隔小于300埃、阶梯外形的高宽比(aspect ratio)(即阶梯高度和宽度的比率)约大于2或阶梯高度约大于300埃均可使用含SiCO和SiCN的材料。在典型的例子中，阶梯外形的高度约高于1000埃。当CES层沉积在未形成间隙壁的多晶硅闸极上时，CES层沉积于复晶硅闸极的两侧成了阶梯外形，且含SiCN和SiCN的材质为形成CES层理想材料。
请参阅图3所示为形成一源极和汲极。磊晶沉积一半导体材料10，其是用来定义源极/汲极区域。最佳形成半导体材料10的方法为选择性磊晶成长(selective epitaxy)。形成SiO2层覆盖在基材2上方(图中未示出)，接着形成孔洞穿过SiO2层以曝露源极/汲极区域，再经由磊晶成长形成半导体材10。形成半导体材料10的较佳方法为分子束磊晶(molecular beamepitaxy，MEB)，其他沉积技术包括：化学气相沉积(chemical vapordeposition，CVD)、极高真空化学气相沉积(ultra high vacuum chemicalvapor deposition，UHVCVD)、原子层化学气相沉积(atomic layer chemicalvapor deposition，ALCVD)或金属有机化学气相沉积(metal organicchemical vapor deposition，MOCVD)。在已曝露的单晶基材区域磊晶长成半导体材料10，接着在SiO2层上形成复晶硅(poly-crystal)，然后蚀刻移除复晶硅和SiO2，只留下半导体材料10。在另一较佳实施例中，形成源极9和汲极11的材料为磊晶于基材2凹处所形成，源极9和汲极11实质上是在基材2内所形成(与在基材2上形成源极9和汲极11是不同的)。在另一较佳实施例中，形成源极9和汲极11可经由掺杂于基材2中所选定的区域中进行。
接着对闸电极6、源极9和汲极11区域进行离子植入(ion-implantation)。由半导体材料10所形成理想的源极9和汲极11区可掺杂高浓度的p型及n型掺质。多晶硅的电阻率可藉由掺杂而降低，接着执行回火(annealing)步骤以恢复植入之前的晶格结构，回火过程必须小心控制。在一较佳实施例中，掺质垂直扩散而超过了植入损坏的区域。在另一较佳实施例中，快速热制程(rapid thermal process，RTP)可减少掺质重新分布范围。值得重视的是，横向分布可能引起掺质扩散到间隙壁下方的区域，但不会扩散到闸介电层下方的区域。
再请参阅图3所示一经由自我对准金属硅化物过程所形成的硅化金属区域13。在闸电极、源极/汲极区上方涂布一层过渡金属材料例如钴、钛、镍或其他类似金属。在一较佳实施例中，使用金属镍当材质，接着进行热制程，使金属和位于下方的硅反应形成硅化金属。利用习知技术透过蚀刻剂(etchant)选择性地移除未反应的金属，此蚀刻剂不会攻击到硅化金属、二氧化硅和硅基材。
可随意选择执行一预处理法，在腔体中进行氢预处理法为较佳方式，处理条件的一例为：氢气流速约为9500sccm，腔体内压力维持在约为2.3torr，温度约为400℃以及处理时间约为10秒。
氨预处理法为另一选择方式，下列处理条件为：腔体中充满氨气和氮气的混合气体，氨气流速约为9500sccm以及氮气流速约为2800sccm，腔体内压力维持约为4.8torr，温度约为400℃以及处理时间约为10秒。
请参阅图4所示为形成一粘着层(glue layer)14。为了改善CES层的附着能力(adhesion)及预防CES层的剥离(peeling)，含SiC材质的薄粘着层14可选择性地形成在整个元件上，包含的区域有源极9和汲极11、间隙壁8和复晶硅6。形成粘着层14的方法有电浆增强式化学气相沉积(plasmaenhanced chemical vapor deposition，PECVD)、原子层沉积(atomic layerdeposition，ALD)，以及低压化学气相沉积(low pressure CVD，LPCVD)，其中以PECVD为较佳方法。沉积粘着层14条件一例为：前驱物为四甲基硅烷Si(CH3)4(4MS或tetramethylsilane)，4MS的流速约为1350sccm，腔体内压力维持在约为1.6torr，温度约为400℃以及处理时间约为20秒。粘着层14形成较佳厚度约为20到50埃之间，更佳厚度约为20埃。
请参阅图5所示为一以毯覆式(blanket)沉积CES层16于粘着层14上方。CES层16较佳形成方式为PECVD，或其他方法例如ALD或LPCVD亦可。在形成CES层16的一较佳实施例中，CES层16的材质为碳掺杂氧化物例如CDO、SiOC和ODC(Oxide Deped Carbide)。CES层16的沉积较佳厚度约为100埃到1000埃之间，更佳厚度约为300埃。形成CES层16的气体可为任何包含碳之前驱物，较佳的组成气体为4MS或三甲基硅甲烷(CH3)3SiH(3MS或trimethylsilane)以及二氧化碳(CO2)。在沉积CDO薄膜的一较佳实施例中，整个气腔体充满4MS和CO2组成的前驱气体，前驱气体的流速约为1060sccm到3860sccm，腔体内压力维持在约1.5torr，沉积温度约为400℃。在上述条件之下，厚度为300埃到500埃的CDO薄膜需花约10秒到50秒间来沉积它。
在形成CES层16的另一较佳实施例中，形成CES层16的材质为氮掺杂氧化物例如NDC和SiCN。CES层16的较佳厚度约为100埃到1000埃，更佳厚度约为300埃。形成CES层16的气体可为任何包含碳之前驱物，较佳的组成气体为4MS或三甲基硅甲烷(CH3)3SiH(3MS或trimethylsilane)、氨气(NH3)和氮气(N2)。在沉积NDC薄膜的一较佳实施例中，整个气腔体充满4MS、NH3和N2所组成的前驱气体，前驱气体的流速约为1120sccm到1700sccm，腔体内压力维持在约3.9torr，沉积温度约为400℃。在上述条件之下，厚度为300埃到500埃的NDC薄膜需花约10秒到50秒间来沉积它。
SiCO和SiCN材料的k值比SiN材料为低(一般SiN的k值为7.5到8)，同时实际的k值会随着不同制程而产生变化。k值可利用制程条件的改变而调整，例如沉积压力的改变，所形成的SiCO或SiCN薄膜的k值范围约在3.0到5.0之间。
增加CES层16会导致元件内应力产生。一般所知元件内的应力会提高载子的迁移率，因而提高元件的效能。由习知工艺所知，同平面拉伸应力(in-plane tensile stress)会改善NMOS元件的效能，但是会降低PMOS元件效能。因此为了利用应力的好处，需要CES层16的应力为可调整的在一较佳实施例中，应力可能会经由改变沉积条件而有所调整，例如改变沉积温度。应力可能调整范围约在-3Gpa到3Gpa，此处的正值表示拉伸应力(tensile stress)，负值表示压缩应力(compressive stress)。
接下来图6所示为一层间介电层18(ILD)沉积在CES层16的表面上，其中ILD层18亦称为前金属介电层(pre-metal dielectric，PMD)或金属层间介电层(inter-metal dielectric，IMD)。在一较佳实施例中，ILD层18为含SiCO或SiCN的材料层，其k值约小于7.0，而较佳的k值约小于4.0。由习知此工艺所知，ILD层18位于晶体管及后来将形成于ILD层18上方的金属线之间当做绝缘材料。寄生电容存在于源极/汲极、复晶硅及形成于ILD层18上方的金属线之间，且寄生电容会降低元件的效能。由于降低ILD层18的k值使得寄生电容变得较小，因此改善了元件的效能。因为所使用介电质材料的k值大小和电容大小成正比，因此ILD层18的较小k值导致寄生电容明显地减小。在另一较佳实施例中，ILD层18也可使用SiO2材质沉积，沉积ILD层18的技术包括CVD、PECVD、LPCVD或其他相关方法。
请参阅图6所示为形成一抗微影材料20且图案化于ILD层18上，以便形成接触窗插塞24于源极/汲极区及闸极上(请见图7)。由于ILD层18和CES层16为可进行选择性蚀刻(selective etching)不同材料，因此分两步骤进行蚀刻。第一步骤为蚀刻ILD层18后停止在CES层16，第二步骤为蚀穿CES层16以曝露出位于下方的材料层。因为CES层16厚度比ILD层18薄，所以蚀刻过程中可更精确地控制以预防过蚀刻(over etch)。虽然CES层16和ILD层18均为含SiCO和SiCN的材料层，但两者必须有所不同以便可进行选择性蚀刻。在一较佳实施例中，因为ILD层18为含SiCO的材质层而CES层16为含SiCN的材料层，所以在蚀刻ILD层18时使用C4F6、O2、CO以及Ar的混合气体进行蚀刻并停止在CES层16，接着CES层16可利用CH2F2加O2的混合气体进行蚀刻。
请参阅图图7所示为形成一接触窗插塞24在接触窗孔洞上。接触窗插塞24可由金属钨、铝、铜或其他习知的替代金属作为材料。接触窗插塞24亦可为复合结构，包括阻障层/粘着层的结构，例如钛/氮化钛(titaniumnitride)或钛/氮化钽(tantalum nitride)，或其他类似的复合层亦可。
将本发明的较佳实施例和一些习知技术方面做比较，例如寄生电容、沉积速率、接触电阻和片电阻等。每一方面比较的结果将于下述讨论。习知工艺的元件大都用类似结构物且在相似的条件下作为较佳实施例，除非在其他方面指定说明。
表一列示使用SiN、ODC和NDC三种介电材料形成薄膜的参数及结果，其中SiN为习知技术所使用的材料，ODC及NDC为本发明的最佳实施例使用的材料。SiN薄膜形成于充满硅化氢(SiH4)、氨气和氮气的气腔体中，沉积温度约为480℃，腔体内压力保持约3torr。
表一
  材质   SiN   ODC   NDC
  沉积时间(秒)   176   54   31
  厚度(埃)   1207   1171   1104
  沉积速率(埃/分)   411   1301   2137
  k值   7.5～8   4～5   4～5
  沉积温度(℃)   480   400   400
在本发明的较佳实施例中，CES层16沉积速率较快而且可在较低温度下进行沉积。ODC及NDC的材质沉积速度约是SiN的材质的4到5倍。ODC及NDC的材质其沉积温度为400℃，低于SiN的材质其沉积温度480℃。ODC及NDC的材质其k值范围约为4～5，小于SiN材质的k值约7.5～8。
在本发明的较佳实施例中，元件的外缘电容降低，此外缘电容为复晶硅6和源极/汲极10之间的寄生电容。图8a和图8b所示为用以解释边缘电容结果，每一图所示含有间隙壁的两相邻MOS元件。在图8a中，标示48和50为间隙壁，同时接触窗插塞60连接于和源极/汲极54。距离d1表示复晶硅42和接触窗插塞60之间的距离。在复晶硅42和接触插塞60间存有边缘电容30。图8b类似于图8a，除了于图8b中移除接触插塞60的部分。距离d2表示一元件的复晶硅62和另一元件的复晶硅73之间的距离。在复晶硅62和复晶硅73间存有边缘电容80。在复晶硅62和源极/汲极74之间也存有外缘电容32，此外缘为复晶硅62和源极/汲极74之间的寄生电容。
图9是图示一电容的量测结果，显示边缘电容为在复晶硅和源极/汲极间之间隔距离的函数图形。在图8a中，复晶硅42和接触窗插塞60间的隔距离表示为d1、图8b中复晶硅62和复晶硅73间隔距离表示为d2。图9中的曲线1和曲线2表示所示于图8a中的结合电容30和32的边缘电容和间隔距离的函数关系。其中曲线1表示含SiN材料(k值为7.5)所形成的CES层46，曲线2表示含CDO及NDC材料(k值为4.0)所形成的CES层46。图9中的曲线3和曲线4表示所示于图8b中的结合电容80和32的边缘电容和间隔距离的函数关系。其中曲线3表示含SiN材料(k值为7.5)所形成的CES层66，曲线4表示含CDO及NDC材料(k值为4.0)所形成的CES层66。可观察到CES层46对于电容30有贡献，因此CES层46的k值降低有助于缩小电容30。因为曲线2所表示的CES层46其k值低于曲线1所表示的CES层46的k值，所以曲线2位置低于曲线1。曲线1和曲线2之间的电容差异约为4％到5％。因为曲线4所表示的CES层66其k值低于曲线3所表示CES层66的k值，所以曲线4位置亦低于曲线3。当间隔距离和增加时，电容30和电容80效应会降低以至于CES层所造成的影响也会低。依某个观点而言，当间隔距离明显地增加时，电容30和电容80的效应会减小而且电容32会变成造成边缘电容的主要部分，最后曲线1、2、3和4将会合并成一曲线。
在现有习知的工艺中，因为CES层16影响接触表面特性、接触外型和其他过蚀刻的行为，所以CES层16影响位于其下的层6及层10(如图5或图6中所示)和接触插塞24之间的接触电阻。接触插塞24和源极/汲极9、11之间的接触电阻和习知的工艺做比较，相关结果显示于图10和图11。图10是图示累积或然率为n+掺杂源极/汲极10和接触插塞24之间接触电阻的函数图形。测试结果以794，475个串连的接触窗为基础。需注意到含ODC材料、含NDC材料及含SiN材料形成的CES层16，分别表示为曲线81、曲线82及曲线83，其中曲线81或曲线82所代表的CES层16的接触电阻比曲线83所代表的CES层16的接触电阻约低10％。
请参阅图11，是图示在累积或然率为p+掺杂源极/汲极9、11和接触插塞24之间接触电阻的函数图形。测试结果也以794，475个串连的接触窗为基础。需注意到含NDC材料、含ODC材料及含SiN材料形成的CES层16，分别表示为曲线91、曲线92及曲线93，其中以曲线91或曲线92代表的CES层16的接触电阻小于曲线93所代表的CES层16的接触电阻。
接触电阻也存在于掺杂n+的多晶硅和金属接触窗之间。从这执行的测试以794，475个串连的接触窗的测试平均值为基础，发现含NDC和ODC的材料电阻比含SiN材料的接触电阻要好一些，所以位于金属和掺杂n+/p+多晶硅之间的接触电阻至少可和现有习知的工艺相匹敌。
由测试中也显示出当CES层16的材料由SiN改变成含ODC及HDC时，位于材料下方的片电阻并不会被影响。n+掺杂源极/汲极、p+掺杂源极/汲极、n+掺杂多晶硅和p+掺杂多晶硅的电阻值已被量测出来，显示不管覆盖在CES层的材料为何，上述的片电阻均不会改变。
其他特性方面例如起始电压和MOS晶体管的遗漏电流的测试结果显示在不同的CES材料层例如ODC、NDC和SiN并没有相当差异。
除了上述提到的优点外，本发明的较佳实施例完全符合现今元件的制造过程，同时可由以知的方法及现存的设备加以制造，以致于没有额外的成本开支。
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制，虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发明，任何熟悉本专业的技术人员，在不脱离本发明技术方案范围内，当可利用上述揭示的方法及技术内容作出些许的更动或修饰为等同变化的等效实施例，但是凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

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1、一集成电路元件，其特征在于其包含：
一基材有一表面；
一闸介电层位于该基材表面上；
一闸电极位于在该闸介电层上；
一对间隙壁位于沿着该闸电极及该闸介电层的两侧；
一对源极/汲极区域位于该闸电极的相反两侧；
一接触窗蚀刻阻绝层位于该源极/汲极区及该间隙壁上，其中该接触窗蚀刻阻绝层的材料是选自由氧碳化硅(SiCO)和氮碳化硅(SiCN)所组成的族群；
一金属层间介电质层位于该接触窗蚀刻阻绝层上方；以及
一传导插塞位于该金属层间介电质层上方。
2、根据权利要求1所述的集成电路元件，其特征在于其中所述的元件更包括一粘着层位于该接触窗蚀刻阻绝层上方。
3、根据权利要求2所述的集成电路元件，其特征在于其中所述的粘着层材料为碳化硅。
4、根据权利要求2所述的集成电路元件，其特征在于其中所述的粘着层厚度约为20埃到50埃。
5、根据权利要求1所述的集成电路元件，其特征在于其中所述的接触窗蚀刻阻绝层的k值约小于7.0。
6、根据权利要求1所述的集成电路元件，其特征在于其中所述的接触窗蚀刻阻绝层的厚度约100埃到1000埃。
7、根据权利要求1所述的集成电路元件，其特征在于其中所述的接触窗蚀刻阻绝层内应力约-3Gpa到3Gpa。
8、一种集成电路元件的形成方法，其特征在于其至少包括：
形成一闸介电层在一基材表面上；
形成一闸电极在该闸介电层上；
形成一对间隙壁于沿着该闸电极及该闸介电层的两侧；
形成一对源极/汲极区域于邻近的该些间隙壁；
形成一接触窗蚀刻阻绝层于该源极/汲极区域上方，其中该接触窗蚀刻阻绝层的材料是选自由氧碳化硅(SiCO)和氮碳化硅(SiCN)所组成的族群；
形成一金属层间介电层于该接触窗蚀刻阻绝层上方；以及
形成一导体于该金属层间介电质层内。
9、根据权利要求8所述的集成电路元件的形成方法，其特征在于其中形成所述的接触窗蚀刻阻绝层的方法为一化学气相沉积法。
10、根据权利要求9所述的集成电路元件的形成方法，其特征在于其中所述的接触窗蚀刻阻绝层的一前驱物为含碳的材料。
11、根据权利要求10所述的集成电路元件的形成方法，其特征在于其中所述的前驱物包含四甲基硅甲烷和三甲基硅甲烷。
12、根据权利要求9所述的集成电路元件的形成方法，其特征在于其中所述的化学气相沉积法沉积温度约为300℃到800℃。
13、根据权利要求8所述的集成电路元件的形成方法，其特征在于其更包含一氢电浆预处理步骤执行于形成该接触窗蚀刻阻绝层之前。
14、根据权利要求8所述的集成电路元件的形成方法，其特征在于其更包含一氨电浆预处理步骤执行于形成该接触窗蚀刻阻绝层之前。
15、根据权利要求8所述的集成电路元件的形成方法，其特征在于其更包含形成一含SiC的粘着层于形成该接触窗蚀刻阻绝层之前。
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CN105428307A (zh) * 2014-09-04 2016-03-23 台湾积体电路制造股份有限公司 用于rc延迟改进的半导体器件蚀刻
CN105428307B (zh) * 2014-09-04 2019-05-21 台湾积体电路制造股份有限公司 用于rc延迟改进的半导体器件蚀刻
CN109119339A (zh) * 2018-08-26 2019-01-01 合肥安德科铭半导体科技有限公司 一种低介电常数的SiCO间隔层材料及其制备方法和应用

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