CN105428307B - 用于rc延迟改进的半导体器件蚀刻 - Google Patents
用于rc延迟改进的半导体器件蚀刻 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 105
- 238000005530 etching Methods 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 91
- 229910052751 metal Inorganic materials 0.000 claims abstract description 73
- 239000002184 metal Substances 0.000 claims abstract description 73
- 150000004767 nitrides Chemical class 0.000 claims abstract description 72
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 238000009792 diffusion process Methods 0.000 claims abstract description 42
- 230000004888 barrier function Effects 0.000 claims abstract description 38
- 239000000463 material Substances 0.000 claims abstract description 31
- 239000004020 conductor Substances 0.000 claims description 63
- 239000010949 copper Substances 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010931 gold Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- 150000001875 compounds Chemical class 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 229910017464 nitrogen compound Inorganic materials 0.000 claims 1
- 150000002830 nitrogen compounds Chemical class 0.000 claims 1
- -1 contact zone.Then Substances 0.000 abstract 1
- 238000000151 deposition Methods 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 238000005240 physical vapour deposition Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
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- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Abstract
在用于制造半导体器件的蚀刻方法中,首先,提供包括接触区的半导体衬底。然后,在半导体衬底上形成金属氮化物层以防止过蚀刻。此后,在金属氮化物层上形成介电层。然后,实施蚀刻工艺以形成穿通金属氮化物层和介电层的开口以暴露接触区。蚀刻方法还可以包括在金属氮化物层和半导体衬底之间形成扩散阻挡层以防止接触区的材料的扩散。本发明涉及用于RC延迟改进的半导体器件蚀刻。
Description
技术领域
本发明涉及用于RC延迟改进的半导体器件蚀刻。
背景技术
在一般情况下,诸如电阻器、晶体管和二极管的各种半导体器件形成在半导体衬底内或上。由导体层和介电层形成这些半导体器件。应用蚀刻工艺以暴露导体层的接触区以将一个半导体器件电连接至另一个半导体器件。传统的蚀刻工艺通常需要具有较大(significant)厚度的蚀刻停止层以防止过蚀刻。然而,蚀刻停止层导致高电阻电容时间延迟(RC延迟)。
发明内容
为了解决现有技术中存在的问题,根据本发明的一个方面,提供了一种蚀刻方法,包括:提供包括接触区的半导体衬底;在所述半导体衬底上形成金属氮化物层;在所述金属氮化物层上形成介电层;以及实施蚀刻工艺以形成穿通所述介电层和所述金属氮化物层的开口以暴露所述接触区。
在上述蚀刻方法中,还包括:在所述半导体衬底和所述金属氮化物层之间形成扩散阻挡层,其中,所述开口形成为穿过所述扩散阻挡层。
在上述蚀刻方法中,形成所述接触区的材料是铜并且形成所述扩散阻挡层的材料是SiCN。
在上述蚀刻方法中,所述扩散阻挡层的厚度在从30埃至60埃的范围内。
在上述蚀刻方法中,所述金属氮化物层的金属是Ⅲ族金属。
在上述蚀刻方法中,所述金属氮化物层由GaN或AlN形成。
在上述蚀刻方法中,所述蚀刻工艺是干蚀刻工艺。
在上述蚀刻方法中,所述金属氮化物层的厚度在从5埃至15埃的范围内。
根据本发明的另一方面,还提供了一种半导体器件,包括:半导体衬底;第一介电层,形成在所述半导体衬底上,其中,所述第一介电层具有第一开口;第二介电层,形成在所述第一介电层上,其中,所述第二介电层具有第二开口;蚀刻停止层,形成在所述第一介电层和所述第二介电层之间,其中,所述蚀刻停止层具有将所述第一开口连接至所述第二开口的第三开口,并且包括金属氮化物层;以及导体,形成在所述第一开口、所述第二开口和所述第三开口中。
在上述半导体器件中,所述蚀刻停止层还包括形成在所述金属氮化物层和所述第一介电层之间的扩散阻挡层。
在上述半导体器件中,形成所述导体的材料是铜并且形成所述扩散阻挡层的材料是SiCN。
在上述半导体器件中,所述扩散阻挡层的厚度在从30埃至60埃的范围内。
在上述半导体器件中,形成所述金属氮化物层的材料是Ⅲ族金属氮化物。
在上述半导体器件中,所述金属氮化物层由GaN或AlN形成。
在上述半导体器件中,所述金属氮化物层的厚度在从5埃至15埃的范围内。
在上述半导体器件中,所述第一介电层和所述第二介电层由低k材料形成。
根据本发明的又一方面,还提供了一种用于制造半导体器件的方法,所述方法包括:提供半导体衬底;在所述半导体衬底上形成第一介电层和第一导体,其中,所述第一介电层具有第一开口,并且所述第一导体位于所述第一开口中;在所述第一介电层和所述第一导体上形成金属氮化物层;在所述金属氮化物层上形成第二介电层;实施蚀刻工艺以形成穿通扩散阻挡层、所述金属氮化物层和所述第二介电层的第二开口以暴露所述第一导体;以及在所述第二开口中形成第二导体以使得所述第一导体能够连接至所述第二导体。
在上述方法中,还包括在所述金属氮化物层和所述第一介电层之间形成扩散阻挡层。
在上述方法中,形成所述金属氮化物层的材料是Ⅲ族金属氮化物。
在上述方法中,所述蚀刻工艺是干蚀刻工艺。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1是根据各个实施例的半导体器件的示意性截面图。
图2A至图2G是根据各个实施例的示出形成半导体器件的方法的中间阶段的示意性截面图。
图3是根据各个实施例的用于制造半导体器件的方法的流程图。
图4是根据各个实施例的用于制造半导体器件的方法的流程图。
图5A至图5E是根据各个实施例的示出形成半导体器件的方法的中间阶段的示意性截面图。
图6是根据各个实施例的用于制造半导体器件的方法的流程图。
具体实施方式
在下文中详细论述了本实施例的制造和使用。然而,应当理解,本发明提供了可以体现在各种具体环境中的许多可应用的发明概念。论述的具体实施例仅仅是用于制造和使用所公开的主题的说明性具体方式,并且不限制不同实施例的范围。本发明可以在各个实例中重复参考标号和/或字符。这种重复是用于简化和清楚的目的,并且其本身并不指示所论述的各个实施例和/或配置之间的关系。
应当理解,虽然本文中可以使用术语“第一”、“第二”等以描述各个元件,这些元件不应受到这些术语的限制。使用这些属于以将一个元件与另一元件区别开。例如,在不背离实施例的范围的情况下,可以将第一元件称为第二元件,并且类似地,可以将第二元件称为第一元件。如本文中所使用的,该术语“和/或”包括一个或多个相关的列举的术语的任意或所有组合。
如本文中使用的,术语“包括”、“包含”、“具有”、“含有”、“涉及”等应当理解为开放式的,即,意为包括但不限于。
贯穿本说明书参考的“一个实施例”或“实施例”意味着本公开的至少一个实施例包括结合所述实施例而描述的特定部件、结构或特征。因此在本说明书的各个位置出现的短语“在一个实施中”或“在实施例中”不一定指同一个实施例。而且,在一个或多个实施例中可以以任何合适的方式组合特定部件、结构或特征。
本发明的实施例涉及提供一种用于制造半导体器件的蚀刻方法。在该蚀刻方法中,蚀刻停止层用来防止过蚀刻。该蚀刻停止层包括金属氮化物层,并且蚀刻停止层可以形成为具有相对较小的厚度,从而降低半导体器件的电阻电容时间延迟(RC延迟)。与厚度为250埃的传统的蚀刻停止层相比,包括金属氮化物层的蚀刻停止层可以形成为具有较小的厚度,诸如 60埃。结果,使用包括金属氮化物层的蚀刻停止层的半导体器件具有相对较小的电阻电容时间延迟。在一个实施例中,蚀刻停止层具有多层结构。该蚀刻停止层包括金属氮化物层和扩散阻挡层。扩散阻挡层用于防止设置在蚀刻停止层下方的导体材料的扩散。
图1是根据各个实施例的半导体器件100的示意性截面图。半导体器件100包括半导体衬底110、第一介电层120、第二介电层130、蚀刻停止层140和导体M。第一介电层120和第二介电层130形成在半导体衬底110 上。蚀刻停止层140形成在第一介电层120和第二介电层130之间。蚀刻停止层140具有多层结构。导体M用作穿过第一介电层120、第二介电层130和蚀刻停止层140的导线。
半导体衬底110被限定为任何结构,其包括半导体材料,包括但不限于块状硅、半导体晶圆、绝缘体上硅(SOI)衬底或硅锗衬底。也可以使用包括Ⅲ族、Ⅳ族和V族元素的其他半导体材料。
第一介电层120和第二介电层130包括介电材料,诸如氧化硅、氮化硅、氮氧化硅、低k介电材料、其他合适的介电材料或它们的组合。在一些实施例中,低k介电材料包括氟化石英玻璃(FSG)、碳掺杂的氧化硅、 BLACK DIAMOND.RTM(加利福尼亚州圣克拉拉的应用材料)、干凝胶、气凝胶、氟化非晶碳、聚对二甲苯、BCB(双苯并环丁烯)、SILK(米奇米德兰陶氏化学)、聚酰亚胺、其他合适的材料或它们的组合。在一些实施例中,第一介电层120和第二介电层130包括具有多种介电材料的多层结构。
导体M是用于传输信号并且包括导电材料的导线,导电材料诸如铝 (Al)、铜(Cu)、银(Ag)、金(Au)、镍(Ni)、钨(W)或它们的合金。
蚀刻停止层140包括扩散阻挡层142和金属氮化物层144。扩散阻挡层142用于防止在制造半导体器件100时的导体M的材料的扩散。金属氮化物层144用于防止当实施用于制造半导体器件100的蚀刻工艺时的过蚀刻。金属氮化物层144由诸如GaN或AlN的III族金属氮化物材料形成。根据导体M的材料选择形成扩散阻挡层142的材料。在一些实施例中,由诸如SiCN、SiCO或SiCON的硅碳基材料形成扩散阻挡层142。
蚀刻停止层140可以形成为具有相对较小的厚度,从而降低半导体器件100的电阻电容时间延迟。在一个实施例中,该扩散阻挡层142的厚度在从30埃至60埃的范围内,并且金属氮化物层144的厚度在从5埃至15 埃的范围内。在一些实施例中,扩散阻挡层142的厚度为50埃,并且金属氮化物层144的厚度是10埃。
参考图2A至图2G,图2A至图2G是根据各个实施例的示出形成半导体器件的方法的中间阶段的示意性截面图。如图2A所示,提供半导体衬底 210。如图2B所示,在半导体衬底210上形成第一介电层220和第一导体 M1。第一介电层220具有第一开口,并且第一导体M1位于第一开口中。在这个实施例中,第一介电层220由低k材料形成,并且第一导体M1由铜形成。
如图2C所示,在第一介电层220和第一导体M1上形成扩散阻挡层 232以防止第一导体M1的材料的扩散。在这个实施例中,扩散阻挡层232 由SiCN形成,并且其厚度为50埃。如图2D所示,在扩散阻挡层232上形成金属氮化物层234以防止过蚀刻。在这个实施例中,金属氮化物层234 由GaN或AlN形成。
如图2E所示,在金属氮化物层234上形成第二介电层240。在这个实施例中,该第二介电层240是由低k材料形成的。如图2F所示,实施蚀刻工艺以形成穿过扩散阻挡层232、金属氮化物层234和第二介电层240的第二开口H以暴露出第一导体M1。在这个实施例中,蚀刻工艺是干蚀刻工艺。如2G中所示,在第二开口中形成第二导体M2以与第一导体M1接触。在这个实施例中,第二导体M2由铜形成。
参考图3和图2A至图2G ,图3为根据各个实施例的用于制造半导体器件的方法300的流程图。方法300开始于操作310,如图2A所示,提供半导体衬底210。在操作320中,如图2B所示,在半导体衬底210上形成第一介电层220和第一导体M1。在操作320中,通过使用沉积工艺形成第一介电层220和第一导体M1,沉积工艺包括但不限于化学汽相沉积(CVD) 工艺或物理汽相沉积(PVD)工艺。
在操作330中,如图2C所示,在第一介电层220和第一导体M1上形成扩散阻挡层232以防止第一导体M1的材料的扩散。在操作330中,通过使用诸如CVD工艺、等离子体增强化学汽相沉积(PECVD)工艺、或原子层化学汽相沉积(ALCVD)工艺的沉积工艺形成扩散阻挡层232。在操作340中,如图2D所示,在扩散阻挡层232上形成金属氮化物层234 以防止过蚀刻。在操作340中,通过使用诸如CVD工艺、PECVD工艺或 ALCVD工艺的沉积工艺形成金属氮化物层234。
在操作350中,如图2E所示,在金属氮化物层234上形成第二介电层 240。在操作350中,通过使用诸如CVD工艺或PVD工艺的沉积工艺形成第二介电层240。在操作360中,如图2F所示,实施蚀刻工艺以形成穿过扩散阻挡层232、金属氮化物层234和第二介电层240的第二开口以暴露第一导体M1。在操作360中,通过使用干蚀刻工艺形成第二开口。在操作360中,通过使用干蚀刻工艺形成第二开口。在操作370中,如图2G所示,在第二开口中形成第二导体M2以与第一导体M1接触。在该实施例中,通过使用诸如CVD工艺或PVD工艺的沉积工艺形成第二导体M2。
与形成传统的蚀刻停止层的传统的材料相比,在本发明的实施例中由金属氮化物形成的蚀刻停止层可以形成为具有相对较小的厚度,从而降低了半导体器件的RC延迟。
值得注意的是,当第一导体M1的材料的扩散系数可以接受时,在本实施例中使用的扩散阻挡层可以节省。
图4是根据各个实施例的半导体器件400的示意性截面图。半导体器件400包括半导体衬底410、介电层420、蚀刻停止层430和导体440。在一些实施例中,半导体衬底410具有形成在其中的半导体元件,并且半导体元件的接触区412暴露在半导体衬底410的表面上。在一个实施例中,半导体元件是金属氧化物半导体场效应晶体管(MOSFET),并且MOSFET 的源极/漏极暴露于接触区412。
在半导体衬底410上形成介电层420,并且在介电层420和半导体衬底410之间形成蚀刻停止层430。在这个实施例中,蚀刻停止层430包括金属氮化物层430以防止过蚀刻。导体440用作穿过介电层420和蚀刻停止层430的导线以与半导体衬底410的接触区412接触。
在这个实施例中,蚀刻停止层430不包括扩散阻挡层,并且因此蚀刻停止层430的厚度可以进一步降低。与半导体器件100相比,由于蚀刻停止层430具有相对较小的厚度,因此半导体器件400具有相对较小的电阻电容时间(RC)延迟。在一个实施例中,蚀刻停止层430的厚度在从5埃至15埃的范围内。
参考图5A至图5E,图5A至图5E是根据各个实施例的示出形成半导体器件的方法的中间阶段的示意性截面图。如图5A所示,提供半导体衬底 510。半导体衬底510具有形成在其中的半导体元件,并且半导体元件的接触区512暴露在半导体衬底510的表面上。在一个实施例中,半导体元件是MOSFET,并且MOSFET的源极/漏极暴露于接触区512。在一个实施例中,接触区512的材料的扩散系数是可以接受的。
诸如图5B所示,在半导体衬底510上形成金属氮化物层520以防止过蚀刻。在这个实施例中,金属氮化物层520由GaN或AlN形成。如图5C 所示,在金属氮化物层520上形成介电层530。在这个实施例中,介电层 530由低k材料形成。如图5D所示,实施蚀刻工艺以形成穿过金属氮化物层520和介电层530的开口OP以暴露接触区512。在这个实施例中,蚀刻工艺是干蚀刻工艺。如图5E所示,在开口OP中形成导体540以与半导体衬底510的接触区512接触。在这个实施例中,导体540是由铜形成的。
参考图6和图5A至图5E,图6是根据各个实施例的用于制造半导体器件的方法600的流程图。方法600开始于操作610,其中,如图5A所示,提供半导体衬底510。在操作620中,如图5B所示,在半导体衬底510上形成金属氮化物层520以防止过蚀刻。在操作620中,通过使用诸如CVD 工艺、PECVD工艺、或ALCVD工艺的沉积工艺形成金属氮化物层520。在一个实施例中,金属氮化物层520的厚度在从5埃至15埃的范围内。
在操作630中,如图5C所示,在金属氮化物层520上形成介电层530。在操作630中,通过使用诸如CVD工艺或PVD工艺的沉积工艺形成介电层530。在操作640中,如图5D所示,实施蚀刻工艺以形成穿过金属氮化物层520和介电层530的开口OP以暴露接触区512。在操作640中,通过使用干蚀刻工艺形成开口。在操作650中,如图5E所示,在开口OP中形成导体540以与半导体衬底510的接触区512接触。在这个实施例中,通过使用诸如CVD工艺或PVD工艺的沉积工艺形成导体540。
根据一些实施例,本发明公开了一种蚀刻方法。在蚀刻方法中,首先,提供包括接触区的半导体衬底。然后,在半导体衬底上形成金属氮化物层。此后,在金属氮化物层上形成介电层。然后,实施蚀刻工艺以形成穿通金属氮化物层和介电层的开口以暴露接触区。
根据特定实施例,本发明公开了包括半导体衬底、第一介电层、第二介电层、蚀刻停止层和导体的半导体器件。第一介电层形成在半导体衬底上,其中第一介电层具有第一开口。第二介电层形成在第一介电层上,其中第二介电层具有第二开口。蚀刻停止层形成在第一介电层和第二介电层之间,其中蚀刻停止层具有将第一开口连接至第二开口的第三开口,并且包括金属氮化物层。导体形成在第一开口、第二开口和第三开口中。
根据特定实施例,本发明公开了一种用于制造半导体器件的方法。在该方法中,首先,提供半导体衬底。然后,在半导体衬底上形成第一介电层和第一导体,其中第一介电层具有第一开口,并且第一导体位于第一开口中。此后,在第一介电层和第一导体上形成金属氮化物层。然后,在金属氮化物层上形成第二介电层。之后,实施蚀刻工艺以形成穿通扩散阻挡层、金属氮化物层和第二介电层的第二开口以暴露出第一导体。然后,在第二开口中形成第二导体以使得第一导体能够连接至第二导体。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (14)
1.一种蚀刻方法,包括:
提供包括接触区的半导体衬底;
在所述半导体衬底上形成金属氮化物层,所述金属氮化物层由GaN形成,其中,所述金属氮化物层的厚度在从5埃至15埃的范围内;
在所述金属氮化物层上形成介电层;以及
实施蚀刻工艺以形成穿通所述介电层和所述金属氮化物层的开口以暴露所述接触区。
2.根据权利要求1所述的蚀刻方法,还包括:在所述半导体衬底和所述金属氮化物层之间形成扩散阻挡层,其中,所述开口形成为穿过所述扩散阻挡层。
3.根据权利要求2所述的蚀刻方法,其中,形成所述接触区的材料是铜并且形成所述扩散阻挡层的材料是SiCN。
4.根据权利要求2所述的蚀刻方法,其中,所述扩散阻挡层的厚度在从30埃至60埃的范围内。
5.根据权利要求1所述的蚀刻方法,其中,所述蚀刻工艺是干蚀刻工艺。
6.一种半导体器件,包括:
半导体衬底;
第一介电层,形成在所述半导体衬底上,其中,所述第一介电层具有第一开口;
第二介电层,形成在所述第一介电层上,其中,所述第二介电层具有第二开口;
蚀刻停止层,形成在所述第一介电层和所述第二介电层之间,其中,所述蚀刻停止层具有将所述第一开口连接至所述第二开口的第三开口,并且包括金属氮化物层,所述金属氮化物层由GaN形成;以及
导体,形成在所述第一开口、所述第二开口和所述第三开口中,其中,形成在所述第一开口中的导体与所述半导体衬底直接接触。
7.根据权利要求6所述的半导体器件,其中,所述蚀刻停止层还包括形成在所述金属氮化物层和所述第一介电层之间的扩散阻挡层。
8.根据权利要求7所述的半导体器件,其中,形成所述导体的材料是铜并且形成所述扩散阻挡层的材料是SiCN。
9.根据权利要求7所述的半导体器件,其中,所述扩散阻挡层的厚度在从30埃至60埃的范围内。
10.根据权利要求6所述的半导体器件,其中,所述金属氮化物层的厚度在从5埃至15埃的范围内。
11.根据权利要求6所述的半导体器件,其中,所述第一介电层和所述第二介电层由低k材料形成。
12.一种用于制造半导体器件的方法,所述方法包括:
提供半导体衬底;
在所述半导体衬底上形成第一介电层和第一导体,其中,所述第一介电层具有第一开口,并且所述第一导体位于所述第一开口中,所述第一导体与所述半导体衬底直接接触;
在所述第一介电层和所述第一导体上形成金属氮化物层,所述金属氮化物层由GaN形成;
在所述金属氮化物层上形成第二介电层;
实施蚀刻工艺以形成穿通扩散阻挡层、所述金属氮化物层和所述第二介电层的第二开口以暴露所述第一导体;以及
在所述第二开口中形成第二导体以使得所述第一导体能够连接至所述第二导体。
13.根据权利要求12所述的方法,还包括在所述金属氮化物层和所述第一介电层之间形成扩散阻挡层。
14.根据权利要求12所述的方法,其中,所述蚀刻工艺是干蚀刻工艺。
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US10276505B2 (en) | 2017-03-08 | 2019-04-30 | Samsung Electronics Co., Ltd. | Integrated circuit device and method of manufacturing the same |
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