CN1716180A - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
- Publication number
- CN1716180A CN1716180A CNA2005100555646A CN200510055564A CN1716180A CN 1716180 A CN1716180 A CN 1716180A CN A2005100555646 A CNA2005100555646 A CN A2005100555646A CN 200510055564 A CN200510055564 A CN 200510055564A CN 1716180 A CN1716180 A CN 1716180A
- Authority
- CN
- China
- Prior art keywords
- storer
- circuit
- configuration information
- reshuffled
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000003860 storage Methods 0.000 claims abstract description 19
- 238000009826 distribution Methods 0.000 claims abstract description 9
- 210000000056 organ Anatomy 0.000 claims description 9
- 230000006870 function Effects 0.000 description 11
- 238000000034 method Methods 0.000 description 8
- 241001269238 Data Species 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000005039 memory span Effects 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1694—Configuration of memory controller to different memory types
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Logic Circuits (AREA)
- Microcomputers (AREA)
- Memory System (AREA)
- Multi Processors (AREA)
Abstract
Description
Claims (14)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP194103/2004 | 2004-06-30 | ||
JP2004194103A JP4451733B2 (ja) | 2004-06-30 | 2004-06-30 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1716180A true CN1716180A (zh) | 2006-01-04 |
CN100397334C CN100397334C (zh) | 2008-06-25 |
Family
ID=34940396
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2005100555646A Expired - Fee Related CN100397334C (zh) | 2004-06-30 | 2005-03-16 | 半导体器件 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7908453B2 (zh) |
EP (2) | EP1612682B1 (zh) |
JP (1) | JP4451733B2 (zh) |
CN (1) | CN100397334C (zh) |
DE (1) | DE602005009081D1 (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105719390A (zh) * | 2014-12-22 | 2016-06-29 | 富士通先端科技株式会社 | 介质处理装置 |
WO2016177083A1 (zh) * | 2015-11-03 | 2016-11-10 | 中兴通讯股份有限公司 | 一种数据存储方法、存储装置和计算机存储介质 |
CN112540953A (zh) * | 2020-12-18 | 2021-03-23 | 广东高云半导体科技股份有限公司 | 基于fpga和mcu实现的片上系统 |
CN114003547A (zh) * | 2017-03-14 | 2022-02-01 | 珠海市芯动力科技有限公司 | 可重构并行处理 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008085864A (ja) * | 2006-09-28 | 2008-04-10 | Fujitsu Ltd | 半導体装置 |
JP4962305B2 (ja) * | 2007-12-26 | 2012-06-27 | 富士通セミコンダクター株式会社 | リコンフィギュラブル回路 |
EP2221822A1 (fr) | 2009-02-23 | 2010-08-25 | Gemalto SA | Procédé de sélection d'une taille de mémoire disponible d'un circuit comprenant au moins un processeur et une mémoire, programme et carte à puces correspondants |
JP5375441B2 (ja) * | 2009-08-27 | 2013-12-25 | 株式会社リコー | 半導体集積回路、記憶制御方法、記憶制御プログラム及び記録媒体 |
JP5776306B2 (ja) * | 2011-04-25 | 2015-09-09 | 富士ゼロックス株式会社 | 画像データ処理装置及びプログラム |
KR101442708B1 (ko) * | 2012-11-28 | 2014-09-22 | 주식회사 휴비츠 | 3차원 oct 데이터를 처리하기 위한 광 간섭 단층 촬영장치 |
US9158704B2 (en) * | 2013-01-24 | 2015-10-13 | Wisconsin Alumni Research Foundation | Virtual memory management system with reduced latency |
JP2022040721A (ja) * | 2020-08-31 | 2022-03-11 | 富士フイルムビジネスイノベーション株式会社 | 情報処理装置、及びプログラム |
Family Cites Families (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4747070A (en) * | 1984-01-09 | 1988-05-24 | Wang Laboratories, Inc. | Reconfigurable memory system |
JPH0194469A (ja) | 1987-10-06 | 1989-04-13 | Nec Corp | 並列処理方式 |
JPH05108586A (ja) | 1991-10-18 | 1993-04-30 | Hitachi Ltd | 並列演算機構及び並列演算方法 |
US5572692A (en) * | 1991-12-24 | 1996-11-05 | Intel Corporation | Memory configuration decoding system having automatic row base address generation mechanism for variable memory devices with row access interleaving |
EP0602276A1 (de) * | 1992-12-18 | 1994-06-22 | Siemens Nixdorf Informationssysteme Aktiengesellschaft | Programmierbare Adre dekoder |
US5915265A (en) * | 1995-12-22 | 1999-06-22 | Intel Corporation | Method and apparatus for dynamically allocating and resizing the dedicated memory in a shared memory buffer architecture system |
US5784699A (en) | 1996-05-24 | 1998-07-21 | Oracle Corporation | Dynamic memory allocation in a computer using a bit map index |
US5933023A (en) | 1996-09-03 | 1999-08-03 | Xilinx, Inc. | FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines |
US5708597A (en) * | 1996-11-20 | 1998-01-13 | Xilinx, Inc. | Structure and method for implementing a memory system having a plurality of memory blocks |
US6185654B1 (en) * | 1998-07-17 | 2001-02-06 | Compaq Computer Corporation | Phantom resource memory address mapping system |
US6137307A (en) * | 1998-08-04 | 2000-10-24 | Xilinx, Inc. | Structure and method for loading wide frames of data from a narrow input bus |
US6279096B1 (en) * | 1998-10-01 | 2001-08-21 | Intelect Communications, Inc. | Digital signal processing memory logic unit using PLA to modify address and data bus output values |
US6678269B1 (en) * | 1998-10-05 | 2004-01-13 | Alcatel | Network switching device with disparate database formats |
JP4240610B2 (ja) * | 1998-11-27 | 2009-03-18 | 株式会社日立製作所 | 計算機システム |
DE60029270T2 (de) * | 1999-04-16 | 2007-07-05 | Infineon Technologies North America Corp., San Jose | Dynamische Rekonfiguration des Cache-Speichers eines Mikrokontrollers |
TW504608B (en) * | 1999-08-30 | 2002-10-01 | Ip Flex Inc | Program product and data processing device |
US6502161B1 (en) * | 2000-01-05 | 2002-12-31 | Rambus Inc. | Memory system including a point-to-point linked memory subsystem |
US6553552B1 (en) * | 2000-01-27 | 2003-04-22 | National Semiconductor Corporation | Method of designing an integrated circuit memory architecture |
JP2001344990A (ja) * | 2000-05-29 | 2001-12-14 | Mitsubishi Electric Corp | 半導体記憶装置 |
US7096324B1 (en) * | 2000-06-12 | 2006-08-22 | Altera Corporation | Embedded processor with dual-port SRAM for programmable logic |
JP2002099464A (ja) * | 2000-06-12 | 2002-04-05 | Altera Corp | チップ搭載システムのための再構成可能なメモリ・マップ |
US6473845B1 (en) * | 2000-09-28 | 2002-10-29 | Hewlett-Packard Company | System and method for dynamically updating memory address mappings |
US6691193B1 (en) | 2000-10-18 | 2004-02-10 | Sony Corporation | Efficient bus utilization in a multiprocessor system by dynamically mapping memory addresses |
US6662285B1 (en) | 2001-01-09 | 2003-12-09 | Xilinx, Inc. | User configurable memory system having local and global memory blocks |
US7610447B2 (en) * | 2001-02-28 | 2009-10-27 | Rambus Inc. | Upgradable memory system with reconfigurable interconnect |
US6889304B2 (en) * | 2001-02-28 | 2005-05-03 | Rambus Inc. | Memory device supporting a dynamically configurable core organization |
US7325123B2 (en) * | 2001-03-22 | 2008-01-29 | Qst Holdings, Llc | Hierarchical interconnect for configuring separate interconnects for each group of fixed and diverse computational elements |
JP2002329396A (ja) * | 2001-04-26 | 2002-11-15 | Fujitsu Ltd | バンク構成を変更可能なフラッシュメモリ |
KR100912437B1 (ko) * | 2001-07-12 | 2009-08-14 | 아이피플렉스 가부시키가이샤 | 집적회로장치 |
US6938127B2 (en) * | 2001-09-25 | 2005-08-30 | Intel Corporation | Reconfiguring memory to reduce boot time |
US20030163769A1 (en) * | 2002-02-27 | 2003-08-28 | Sun Microsystems, Inc. | Memory module including an error detection mechanism for address and control signals |
JP3934493B2 (ja) * | 2002-06-28 | 2007-06-20 | 富士通株式会社 | 集積回路及びシステム開発方法 |
JP2004127245A (ja) | 2002-08-07 | 2004-04-22 | Matsushita Electric Ind Co Ltd | 半導体集積回路装置 |
US7782853B2 (en) * | 2002-12-06 | 2010-08-24 | Stmicroelectronics, Inc. | Apparatus and method of using fully configurable memory, multi-stage pipeline logic and an embedded processor to implement multi-bit trie algorithmic network search engine |
-
2004
- 2004-06-30 JP JP2004194103A patent/JP4451733B2/ja not_active Expired - Fee Related
-
2005
- 2005-01-26 DE DE602005009081T patent/DE602005009081D1/de active Active
- 2005-01-26 EP EP05250402A patent/EP1612682B1/en not_active Expired - Fee Related
- 2005-01-26 EP EP07119502A patent/EP1906312B1/en not_active Expired - Fee Related
- 2005-03-16 CN CNB2005100555646A patent/CN100397334C/zh not_active Expired - Fee Related
- 2005-06-28 US US11/167,310 patent/US7908453B2/en active Active
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105719390A (zh) * | 2014-12-22 | 2016-06-29 | 富士通先端科技株式会社 | 介质处理装置 |
WO2016177083A1 (zh) * | 2015-11-03 | 2016-11-10 | 中兴通讯股份有限公司 | 一种数据存储方法、存储装置和计算机存储介质 |
CN114003547A (zh) * | 2017-03-14 | 2022-02-01 | 珠海市芯动力科技有限公司 | 可重构并行处理 |
CN114003547B (zh) * | 2017-03-14 | 2023-12-19 | 珠海市芯动力科技有限公司 | 可重构并行处理 |
CN112540953A (zh) * | 2020-12-18 | 2021-03-23 | 广东高云半导体科技股份有限公司 | 基于fpga和mcu实现的片上系统 |
Also Published As
Publication number | Publication date |
---|---|
JP4451733B2 (ja) | 2010-04-14 |
CN100397334C (zh) | 2008-06-25 |
US20060004979A1 (en) | 2006-01-05 |
US7908453B2 (en) | 2011-03-15 |
DE602005009081D1 (de) | 2008-10-02 |
JP2006018452A (ja) | 2006-01-19 |
EP1906312B1 (en) | 2012-07-25 |
EP1612682B1 (en) | 2008-08-20 |
EP1612682A1 (en) | 2006-01-04 |
EP1906312A1 (en) | 2008-04-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1716180A (zh) | 半导体器件 | |
JP2018073402A (ja) | Dram基盤プロセシングユニット | |
EP0424618A2 (en) | Input/output system | |
JP6791522B2 (ja) | インデータパス計算動作のための装置及び方法 | |
EP3056985A1 (en) | Register file system and method for pipelined processing | |
US7386689B2 (en) | Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner | |
CN111656339B (zh) | 存储器装置及其控制方法 | |
CN1716210A (zh) | 半导体器件 | |
TWI713047B (zh) | Dram式處理單元的電路和微架構 | |
US9798543B2 (en) | Fast mapping table register file allocation algorithm for SIMT processors | |
EP3910488A1 (en) | Systems, methods, and devices for near data processing | |
CN1201233C (zh) | 带有可编程存储体选择的具有不同数据缓冲区容量的多层存储体 | |
CN101243416A (zh) | 在具有至少两个处理单元和用于数据和/或指令的至少一个第一存储器或存储器区域的计算机系统中存储数据和/或指令的设备和方法 | |
CN1758208A (zh) | 对挂接在片外单总线上的多种存储器进行访问的方法 | |
CN1416139A (zh) | 具有备份存储器块的非易失性半导体存储器 | |
JP2012008747A (ja) | 集積装置、メモリ割り当て方法、および、プログラム | |
CN1768331A (zh) | 半导体存储器装置和控制器及其读写控制方法 | |
CN112433760B (zh) | 数据排序方法和数据排序电路 | |
JPWO2010122607A1 (ja) | 記憶制御装置及びその制御方法 | |
GB2370139A (en) | Parallel loaded shift register in parallel processor element | |
CN112486904A (zh) | 可重构处理单元阵列的寄存器堆设计方法及装置 | |
US20060069873A1 (en) | Instruction cache using single-ported memories | |
US20190095360A1 (en) | Sorting Memory Address Requests for Parallel Memory Access | |
US7000089B2 (en) | Address assignment to transaction for serialization | |
CN101243404A (zh) | 用于在具有至少两个处理单元和用于数据和/或指令的至少一个第一存储器或存储器区域的计算机系统中存储数据和/或指令的设备和方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: FUJITSU MICROELECTRONICS CO., LTD. Free format text: FORMER OWNER: FUJITSU LIMITED Effective date: 20081024 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20081024 Address after: Tokyo, Japan, Japan Patentee after: Fujitsu Microelectronics Ltd. Address before: Kanagawa Patentee before: Fujitsu Ltd. |
|
C56 | Change in the name or address of the patentee |
Owner name: FUJITSU SEMICONDUCTORS CO., LTD Free format text: FORMER NAME: FUJITSU MICROELECTRON CO., LTD. |
|
CP03 | Change of name, title or address |
Address after: Kanagawa Patentee after: Fujitsu Semiconductor Co., Ltd. Address before: Tokyo, Japan, Japan Patentee before: Fujitsu Microelectronics Ltd. |
|
ASS | Succession or assignment of patent right |
Owner name: SPANSION LLC N. D. GES D. STAATES Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR CO., LTD. Effective date: 20140102 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20140102 Address after: American California Patentee after: Spansion LLC N. D. Ges D. Staates Address before: Kanagawa Patentee before: Fujitsu Semiconductor Co., Ltd. |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20160314 Address after: American California Patentee after: Cypress Semiconductor Corp. Address before: American California Patentee before: Spansion LLC N. D. Ges D. Staates |
|
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080625 Termination date: 20170316 |
|
CF01 | Termination of patent right due to non-payment of annual fee |