WO2016177083A1 - 一种数据存储方法、存储装置和计算机存储介质 - Google Patents

一种数据存储方法、存储装置和计算机存储介质 Download PDF

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WO2016177083A1
WO2016177083A1 PCT/CN2016/075819 CN2016075819W WO2016177083A1 WO 2016177083 A1 WO2016177083 A1 WO 2016177083A1 CN 2016075819 W CN2016075819 W CN 2016075819W WO 2016177083 A1 WO2016177083 A1 WO 2016177083A1
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data
ram
memory
storage
space
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French (fr)
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文显琼
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中兴通讯股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0638—Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing

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  • the present invention relates to the field of data reading and writing, and in particular, to a data storage method, a storage device, and a computer storage medium.
  • RAM Random Access Memory
  • n M a positive integer, for example, 32M, 64M, 16M, etc.; but the RAM storage space required for design is not exactly 2 n M. Assume that the RAM storage space required for design is 67M. At this time, the use of 64M RAM storage space can not meet the design needs; using 128MB of RAM storage space, there will be 61 depth of RAM space can not be used, resulting in a waste of storage space.
  • the embodiments of the present invention are expected to provide a data storage method, a storage device, and a computer storage medium, which can utilize the storage space to the maximum extent and reduce the waste of the storage space.
  • a data storage method comprising:
  • the first data is stored in a memory and/or a random access memory RAM in accordance with the addressing space.
  • the memory and/or random access according to the addressing space includes:
  • the first 2 n M data in the first data is written into the first RAM, and the remaining (X-2 n )M data is written into the storage space as (X-2 n )M memory, the y ⁇ 2 n ;
  • the first data is written into the second RAM having a storage space of 2 n+1 M.
  • the y is equal to
  • the method further includes:
  • control signal being configured to select an address of the second data to be read from among the respective addresses of the RAM and/or the memory;
  • an embodiment of the present invention further provides a storage device, where the device includes:
  • An obtaining unit configured to acquire an addressing space, where the addressing space is a space required to store the first data
  • a storage unit configured to store the first data in a memory and/or a random access memory RAM according to the addressing space.
  • the storage unit is configured to:
  • the first 2 n M data in the first data is written into the first RAM, and the remaining (X-2 n )M data is written into the storage space as (X-2 n )M memory, the y ⁇ 2 n ;
  • the first data is written into the second RAM having a storage space of 2 n+1 M.
  • the y is equal to
  • the device further includes:
  • a receiving unit configured to receive a control signal, the control signal configured to select an address of the second data to be read from the RAM and/or each address of the memory;
  • the reading unit is configured to read the second data from the address of the second data according to the control signal.
  • an embodiment of the present invention further provides a storage device, where the device includes: a RAM, a memory, and an address bus connecting the RAM and the memory;
  • the first data is stored in the memory and the RAM according to an addressing space, and the addressing space is a space required to store the first data.
  • a chip select bit of the RAM when the first data is written into the RAM, a chip select bit of the RAM is an active state; a slice select bit of the memory is an invalid state; when the first data is not written When the data into the RAM is written into the memory, the chip select bit of the memory is in an active state; the chip select bit of the RAM is in an invalid state;
  • the chip select bit of the RAM is the highest bit of the address bus connected to the RAM; the chip select bit of the memory is the highest bit of the address bus connected to the memory.
  • the memory is at least one register.
  • the device further includes:
  • a multi-selector configured to read the stored second data based on the control signal.
  • the embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the data storage method according to the embodiment of the present invention.
  • Embodiments of the present invention provide a data storage method, a storage device, and a computer storage medium.
  • the method includes obtaining an addressing space that is a space required to store first data, and storing the first data in a memory and/or a random access memory RAM according to the addressing space.
  • the combination of the RAM and the memory is selected according to the storage space of the storage device. Therefore, the storage space is not limited to the number of times of 2, but is closest to the storage space required by the design, thereby maximizing The use of storage space reduces the waste of storage space.
  • FIG. 1 is a flowchart of a data storage method according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a storage device according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of still another storage device according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of still another storage device according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of another storage device according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a storage device with a storage space of 67M according to an embodiment of the present invention.
  • An embodiment of the present invention provides a data storage method, as shown in FIG. 1, applied to a storage device, where the storage device includes a first RAM, a memory, and a second RAM, and the method includes:
  • Step 101 Acquire an addressing space, where the addressing space is a space required to store the first data.
  • Step 102 Store the first data in the memory and/or the RAM according to the addressing space.
  • the first data is written into the first RAM with a storage space of 2 n M, and the n is a positive integer; if 2 n ⁇ X ⁇ 2 n +y, then the first The first 2 n M data in one data is written into the first RAM, and the remaining (X-2 n )M data is written into the memory of the storage space (X-2 n )M, the y ⁇ 2 n ; if 2 n +y ⁇ X ⁇ 2 n+1 , the first data is written to the second RAM having a storage space of 2 n+1 M.
  • the storage device of this embodiment can be divided into two cases. In the first case, it is assumed that the storage device has only the RAM, only the first RAM, the second RAM, and the memory. If X ⁇ 2 n , the first data is written to the first memory. In the second case, the storage device has a RAM of each storage space, and the first data is written into the most suitable RAM according to the addressing address. If X ⁇ 2 n , the first data is allocated to the method according to the embodiment. A smaller order of RAM and memory.
  • y is equal to
  • the writing process may include: inputting a chip select signal to the memory, the chip select signal causing the chip select bit of the memory to be in an active state, writing data to the memory; and inputting the chip select signal to the first RAM or the second RAM, The chip select signal causes the chip select bit of the corresponding RAM to be in an active state, and writes the data to the corresponding RAM.
  • the chip select bit is in the active state, the chip select bit is at the high level; the chip select bit is in the invalid state, the chip select bit is at the low level, wherein the chip select bit is the highest bit of the address bus.
  • the combination of the RAM and the memory is selected according to the storage space of the storage device. Therefore, the storage space is not limited to the number of times of 2, but is closest to the storage space required for the design, thereby maximizing the use of the storage space and reducing the storage. The waste of space.
  • the memory is at least one register.
  • the memory of (X-2 n )M includes:
  • the memory can be more than just registers, but can be other memories, such as RAM.
  • the unified write port of the plurality of registers is an address comparison unit, and based on the address space, it is determined which register is written. Since the total storage space of the current register set is mM, the m is a positive integer, so the bit width of the address comparison unit is zbit, and z satisfies 2 z-1 ⁇ m ⁇ 2 z .
  • the method further includes:
  • the control signal being configured to select an address of the second data to be read from among respective addresses of the RAM and/or the memory; and reading the second data from the address of the second data according to the control signal .
  • the RAM is a first RAM or a second RAM.
  • the embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the data storage method according to the embodiment of the invention.
  • the embodiment of the present invention provides a storage device 20. As shown in FIG. 2, the device 20 includes:
  • the obtaining unit 201 is configured to acquire an addressing space, which is a space required for storing the first data.
  • the storage unit 202 is configured to store the first data in a memory and/or a RAM according to the addressing space.
  • the combination of the RAM and the memory is selected according to the storage space of the storage device. Therefore, the storage space is not limited to the number of times of 2, but is closest to the storage space required for the design, thereby maximizing the use of the storage space and reducing the storage. The waste of space.
  • the storage unit 202 is configured to:
  • the first data is written to the second RAM having a storage space of 2 n+1 M.
  • X needs to be less than 2 n+1 .
  • the y is equal to
  • the device 20 further includes:
  • the receiving unit 203 is configured to receive a control signal, where the control signal is configured to select an address of the second data to be read from the RAM and/or each address of the memory;
  • the reading unit 204 is configured to read the second data from the address of the second data according to the control signal.
  • the acquiring unit 201 and the reading unit 204 in the storage device may be used by a central processing unit (CPU) and a digital signal processor (DSP, in the device). Digital Signal Processor) or a Field-Programmable Gate Array (FPGA); a memory unit in the storage device may be implemented by a memory in the device in an actual application; a receiving unit in the storage device 203, which can be implemented in a practical application by a transmission interface in the device.
  • CPU central processing unit
  • DSP digital signal processor
  • FPGA Field-Programmable Gate Array
  • the embodiment of the present invention further provides a storage device 20, as shown in FIG. 4, the device 20 includes: a RAM 301, a memory 302, and an address bus 303 connecting the RAM 301 and the memory 302;
  • the first data is stored in the memory 302 and the RAM 301 according to an addressing space, and the addressing space is a space required to store the first data.
  • the storage space of the storage device is composed of the storage space of the RAM and the memory, and many kinds of combinations are possible. Therefore, the storage space is not limited to the number of times of 2, but is the storage space closest to the design. Maximize the use of storage space and reduce the waste of storage space.
  • the chip select bit of the RAM 301 when the first data is written into the RAM 301, the chip select bit of the RAM 301 is in an active state; the chip select bit of the memory 302 is in an invalid state; when the first data is not written into the RAM 301 When the data is written into the memory 302, the chip select bit of the memory 302 is in an active state; the chip select bit of the RAM 301 is in an invalid state;
  • the chip select bit of the RAM 301 is the highest bit of the address bus connected to the RAM 301; the chip select bit of the memory 302 is the highest bit of the address bus connected to the memory 302.
  • the memory 302 is at least one register 3021.
  • the device 20 further includes:
  • the multi-selector 304 is configured to read the stored second data according to a control signal.
  • the storage space X is very close to 2 n+1 , the space saved is not very large, and the second RAM with the storage space of 2 n+1 M can be used directly, without using the RAM of the embodiment.
  • the way to add memory Preferably, when using the RAM plus memory method, That is, X should satisfy
  • a storage space 67M is required, which is slightly larger than 64M and smaller than (64+64/3) M. Therefore, the scheme of using the RAM 301 plus the register 3021 provided in this embodiment is very suitable.
  • the storage device having a storage space of 67M is composed of a 64M RAM 302 and three 1M registers 3021.
  • the 64M RAM 301 and the 3 sets of registers 3021 use a common address bus.
  • the chip select bit of the RAM 301 is in an active state
  • the chip select bit of the register 3021 is in an invalid state
  • the RAM 301 is written; when the address space is outside 64, the RAM is selected.
  • the bit is in an inactive state
  • the chip select bit of the register 3021 is in an active state.
  • the register 3021 is written.
  • the write port is a The address comparison unit, since the storage space of the current three registers 3021 is 3M, the bit width of the address comparison unit can access all the current registers 3021 by only 2 bits.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • the embodiment of the present invention selects a combination mode of the RAM and the memory according to the storage space of the storage device. Therefore, the storage space is not limited to the number of times of 2, but is closest to the storage space required by the design, thereby maximally utilizing the storage space. Reduce the waste of storage space.

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Abstract

一种数据存储方法、存储装置和计算机存储介质。所述方法包括：获取寻址空间，所述寻址空间是需要存储第一数据需要的空间（101）；根据所述寻址空间，在存储器和/或随机存取存储器RAM中存储所述第一数据（102）。

Description

一种数据存储方法、存储装置和计算机存储介质 技术领域
本发明涉及数据读写领域，尤其涉及一种数据存储方法、存储装置和计算机存储介质。
背景技术
在现场可编程门阵列(Field Programmable Gate Array，FPGA)或特定用途集成电路(Application Specific Integrated Circuit，ASIC)设计中，经常会使用随机存取存储器(Random-Access Memory，RAM)。目前使用的RAM存储空间都是2nM，n是正整数，例如，32M、64M、16M等；但设计时需要的RAM存储空间并非都恰好是2nM。假设设计时需要的RAM存储空间是67M。此时，使用存储空间为64M的RAM不能满足设计需要；使用存储空间为128M的RAM，将会有61深度的RAM空间完全不能被利用，从而造成了存储空间的浪费。
发明内容
本发明实施例期望提供一种数据存储方法、存储装置和计算机存储介质，能够最大限度的利用存储空间，减少存储空间的浪费。
本发明实施例的技术方案是这样实现的：
第一方面，提供一种数据存储方法，所述方法包括：
获取寻址空间，所述寻址空间是需要存储第一数据需要的空间；
根据所述寻址空间，在存储器和/或随机存取存储器RAM中存储所述第一数据。
作为一种实施方式，所述根据所述寻址空间，在存储器和/或随机存取 存储器RAM中存储所述第一数据包括：
若所述寻址空间X＝2n，则将所述第一数据写入存储空间为2nM的第一RAM，所述n是正整数；
若所述2n<X≤2n+y，则将所述第一数据中前2nM数据写入所述第一RAM，将剩余的(X-2n)M数据写入存储空间为(X-2n)M的存储器，所述y<2n；
若所述2n+y<X<2n+1，则将所述第一数据写入存储空间为2n+1M的第二RAM。
作为一种实施方式，所述y等于
Figure PCTCN2016075819-appb-000001
作为一种实施方式，所述方法还包括：
接收控制信号，所述控制信号配置为从所述RAM和/或所述存储器的各个地址中，选择需要读取的第二数据的地址；
根据所述控制信号，将所述第二数据的地址中读出所述第二数据。
第二方面，本发明实施例还提供了一种存储装置，所述装置包括：
获取单元，配置为获取寻址空间，所述寻址空间是需要存储第一数据需要的空间；
存储单元，配置为根据所述寻址空间，在存储器和/或随机存取存储器RAM中存储所述第一数据。
作为一种实施方式，所述存储单元配置为：
若所述寻址空间X＝2n，则将所述第一数据写入存储空间为2nM的第一RAM，所述n是正整数；
若所述2n<X≤2n+y，则将所述第一数据中前2nM数据写入所述第一RAM，将剩余的(X-2n)M数据写入存储空间为(X-2n)M的存储器，所述y<2n；
若所述2n+y<X<2n+1，则将所述第一数据写入存储空间为2n+1M的第二RAM。
作为一种实施方式，所述y等于
Figure PCTCN2016075819-appb-000002
作为一种实施方式，所述装置还包括：
接收单元，配置为接收控制信号，所述控制信号配置为从所述RAM和/或所述存储器的各个地址中，选择需要读取的第二数据的地址；
读出单元，配置为根据所述控制信号，将所述第二数据的地址中读出所述第二数据。
第三方面，本发明实施例还提供了一种存储装置，所述装置包括：RAM、存储器和连接所述RAM和所述存储器的地址总线；
其中，第一数据根据寻址空间，存入所述存储器和所述RAM，所述寻址空间是需要存储所述第一数据需要的空间。
作为一种实施方式，当所述第一数据写入所述RAM时，所述RAM的片选位是有效状态；所述存储器的片选位是无效状态；当所述第一数据中未写入所述RAM的数据写入所述存储器时，所述存储器的片选位是有效状态；所述RAM的片选位是无效状态；
其中，所述RAM的片选位是与所述RAM连接的地址总线的最高位；所述存储器的片选位是与所述存储器连接的地址总线的最高位。
作为一种实施方式，所述存储器是至少一个寄存器。
作为一种实施方式，所述装置还包括：
多选器，配置为根据控制信号，将所述已存储的第二数据读出。
第四方面，本发明实施例还提供了一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行本发明实施例所述的数据存储方法。
本发明实施例提供了一种数据存储方法、存储装置和计算机存储介质， 所述方法包括：获取寻址空间，所述寻址空间是需要存储第一数据需要的空间；根据所述寻址空间，在存储器和/或随机存取存储器RAM中存储所述第一数据。采用本发明实施例的技术方案，根据存储装置的存储空间选择RAM和存储器的组合方式，因此，该存储空间不仅仅限于2的几次方，而是最为接近设计需要的存储空间，从而最大限度的利用存储空间，减少存储空间的浪费。
附图说明
图1为本发明实施例提供的一种数据存储方法的流程图；
图2为本发明实施例提供的一种存储装置的结构示意图；
图3为本发明实施例提供的再一种存储装置的结构示意图；
图4为本发明实施例提供的又一种存储装置的结构示意图；
图5为本发明实施例提供的另一种存储装置的结构示意图；
图6为本发明实施例提供的存储空间为67M的存储装置的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
实施例一
本发明实施例提供一种数据存储方法，如图1所示，应用于存储装置，所述存储装置包括第一RAM、存储器和第二RAM，所述方法包括：
步骤101、获取寻址空间，所述寻址空间是需要存储第一数据需要的空间。
步骤102、根据寻址空间，在存储器和/或RAM中存储第一数据。
具体的，若寻址空间X＝2n，则将第一数据写入存储空间为2nM的第一RAM，所述n是正整数；若2n<X≤2n+y，则将第一数据中前2nM数据写 入第一RAM，将剩余的(X-2n)M数据写入存储空间为(X-2n)M的存储器，所述y<2n；若2n+y<X<2n+1，则将第一数据写入存储空间为2n+1M的第二RAM。
值得说明的是，本实施例的存储装置可以分为两种情况。第一种情况，假设存储装置只有RAM只有第一RAM、第二RAM和存储器，若X<2n，则将第一数据写入第一存储器。第二种情况，存储装置具有各个存储空间的RAM，根据寻址地址将第一数据写入最合适的RAM中，若X<2n，在按照本实施例的方法，将第一数据分配到更小数量级的RAM和存储器中。
作为其中一种实施方式，y等于
Figure PCTCN2016075819-appb-000003
这里，写入过程可以包括：向存储器输入片选信号，所述片选信号使存储器的片选位处于有效状态，将数据写入存储器；向第一RAM或第二RAM输入片选信号，所述片选信号使对应RAM的片选位处于有效状态，将数据写入对应的RAM。
其中，片选位处于有效状态是指片选位处于高电平；片选位处于无效状态是指片选位处于低电平，其中，片选位是地址总线的最高位。
这样，根据存储装置的存储空间选择RAM和存储器的组合方式，因此，该存储空间不仅仅限于2的几次方，而是最为接近设计需要的存储空间，从而最大限度的利用存储空间，减少存储空间的浪费。
作为一种实施方式，所述存储器是至少一个寄存器。
对应的，若2n<X≤2n+y，则将所述第一数据中前2nM数据写入所述第一RAM，将剩余的(X-2n)M数据写入容量为(X-2n)M的存储器包括：
当寄存器的片选位处于有效状态，存储器的片选位处于无效状态时，对寄存器进行写操作；当寄存器的片选位处于无效状态，存储器的片选位处于有效状态时，对第一RAM进行写操作。值得说明的是，本实施例中， 存储器可以不仅仅是寄存器，还可以是其他存储器，例如RAM。
对于存储器是多个寄存器时，多个寄存器的统一写口是一个地址比较单元，根据寻址空间，确定出写入哪个寄存器。由于当前寄存器组的总存储空间是mM，该m是正整数，所以，地址比较单元的位宽是zbit，z满足2z-1<m<2z。
进一步的，所述方法还包括：
接收控制信号，所述控制信号配置为从RAM和/或存储器的各个地址中，选择需要读取的第二数据的地址；根据所述控制信号，将第二数据的地址中读出第二数据。这里，该RAM为第一RAM或第二RAM。
本发明实施例还提供了一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行本发明实施例所述的数据存储方法。
实施例二
本发明实施例提供一种存储装置20，如图2所示，所述装置20包括：
获取单元201，配置为获取寻址空间，所述寻址空间是需要存储第一数据需要的空间。
存储单元202，配置为根据所述寻址空间，在存储器和/或RAM中存储所述第一数据。
这样，根据存储装置的存储空间选择RAM和存储器的组合方式，因此，该存储空间不仅仅限于2的几次方，而是最为接近设计需要的存储空间，从而最大限度的利用存储空间，减少存储空间的浪费。
具体的，所述存储单元202配置为：
若所述寻址空间X＝2n，则将所述第一数据写入存储空间为2nM的第一RAM，所述n是正整数；
若2n<X<2n+y，则将所述第一数据中前2nM数据写入所述第一RAM， 将剩余的(X-2n)M数据写入所述存储器，所述y<2n；
若2n+y<X<2n+1，则将第一数据写入存储空间为2n+1M的第二RAM。这里，X需要小于2n+1。
作为其中一种实施方式，所述y等于
Figure PCTCN2016075819-appb-000004
作为一种实施方式，如图3所示，所述装置20还包括：
接收单元203，配置为接收控制信号，所述控制信号配置为从所述RAM和/或所述存储器的各个地址中，选择需要读取的第二数据的地址；
读出单元204，配置为根据所述控制信号，将所述第二数据的地址中读出所述第二数据。
在本实施例中，所述存储装置中的获取单元201和读出单元204，在实际应用中均可由所述装置中的中央处理器(CPU，Central Processing Unit)、数字信号处理器(DSP，Digital Signal Processor)或可编程门阵列(FPGA，Field－Programmable Gate Array)实现；所述存储装置中的存储单元，在实际应用中可由所述装置中的存储器实现；所述存储装置中的接收单元203，在实际应用中可由所述装置中的传输接口实现。
实施例三
本发明实施例还提供一种存储装置20，如图4所示，所述装置20包括：RAM 301、存储器302和连接所述RAM301和所述存储器302的地址总线303；
其中，第一数据根据寻址空间，存入所述存储器302和所述RAM301，所述寻址空间是需要存储所述第一数据需要的空间。
这样，存储装置的存储空间由RAM和存储器的存储空间共同组成，可以出现许多种组合的可能，因此，该存储空间不仅仅限于2的几次方，而是最为接近设计需要的存储空间，从而最大限度的利用存储空间，减少存储空间的浪费。
进一步的，当第一数据写入所述RAM301时，所述RAM301的片选位是有效状态；所述存储器302的片选位是无效状态；当所述第一数据中未写入所述RAM301的数据写入所述存储器302时，所述存储器302的片选位是有效状态；所述RAM301的片选位是无效状态；
其中，所述RAM301的片选位是与所述RAM301连接的地址总线的最高位；所述存储器302的片选位是与所述存储器302连接的地址总线的最高位。
作为一种实施方式，所述存储器302是至少一个寄存器3021。
作为一种实施方式，如图5所示，所述装置20还包括：
多选器304，配置为根据控制信号，将所述已存储的第二数据读出。
值得说明的是，若存储空间X很接近2n+1，则节省的空间也不是很大，直接使用存储空间为2n+1M的第二RAM即可，无需使用本实施例这种RAM加存储器的方式。优选的，使用RAM加存储器的方式时，
Figure PCTCN2016075819-appb-000005
即X应该满足
Figure PCTCN2016075819-appb-000006
例如，如图6所示，需要存储空间67M，该存储空间略大于64M，小于(64+64/3)M，因此，使用本实施例提供的RAM301加寄存器3021的方案就非常合适。
具体的，存储空间为67M的存储装置由64M的RAM302和3个1M的寄存器3021组成。
在写操作时，64M的RAM301和3组寄存器3021使用公用的地址总线。当寻址空间在64以内时，RAM301的片选位处于有效状态，寄存器3021的片选位处于无效状态，此时，对RAM301进行写操作；当寻址空间在64以外时，RAM的片选位处于无效状态，寄存器3021的片选位处于有效状态，此时，对寄存器3021进行写操作。对于3个寄存器3021，写口是一个 地址比较单元，由于当前3个寄存器3021的存储空间为3M，所以地址比较单元的位宽只要2bit即可访问当前所有寄存器3021组。
在读操作时，要求数据出来后不要做复杂逻辑。这个设计上，只是一个MUX(多选器)，而且MUX的控制的使能位比数据rd_data提前给出，所以MUX的通道是提前建立好的。与现有的RAM相比就是多了一个MUX的器件延时。读出数据后按常规设计用寄存器3021打一拍即可。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机 实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
本发明实施例根据存储装置的存储空间选择RAM和存储器的组合方式，因此，该存储空间不仅仅限于2的几次方，而是最为接近设计需要的存储空间，从而最大限度的利用存储空间，减少存储空间的浪费。

Claims (13)

  1. 一种数据存储方法，所述方法包括：
    获取寻址空间，所述寻址空间是需要存储第一数据需要的空间；
    根据所述寻址空间，在存储器和/或随机存取存储器RAM中存储所述第一数据。
  2. 根据权利要求1所述的方法，其中，所述根据所述寻址空间，在存储器和/或随机存取存储器RAM中存储所述第一数据包括：
    若所述寻址空间X＝2n，则将所述第一数据写入存储空间为2nM的第一RAM，所述n是正整数；
    若所述2n<X≤2n+y，则将所述第一数据中前2nM数据写入所述第一RAM，将剩余的(X-2n)M数据写入存储空间为(X-2n)M的存储器，所述y<2n；
    若所述2n+y<X<2n+1，则将所述第一数据写入存储空间为2n+1M的第二RAM。
  3. 根据权利要求2所述的方法，其中，所述y等于
    Figure PCTCN2016075819-appb-100001
  4. 根据权利要求1至3任一项所述的方法，其中，所述方法还包括：
    接收控制信号，所述控制信号配置为从所述RAM和/或所述存储器的各个地址中，选择需要读取的第二数据的地址；
    根据所述控制信号，将所述第二数据的地址中读出所述第二数据。
  5. 一种存储装置，所述装置包括：
    获取单元，配置为获取寻址空间，所述寻址空间是需要存储第一数据需要的空间；
    存储单元，配置为根据所述寻址空间，在存储器和/或随机存取存储器RAM中存储所述第一数据。
  6. 根据权利要求5所述的装置，其中，所述存储单元配置为：
    若所述寻址空间X＝2n，则将所述第一数据写入存储空间为2nM的第一RAM，所述n是正整数；
    若所述2n<X≤2n+y，则将所述第一数据中前2nM数据写入所述第一RAM，将剩余的(X-2n)M数据写入存储空间为(X-2n)M的存储器，所述y<2n；
    若所述2n+y<X<2n+1，则将所述第一数据写入存储空间为2n+1M的第二RAM。
  7. 根据权利要求6所述的装置，其中，所述y等于
    Figure PCTCN2016075819-appb-100002
  8. 根据权利要求5至7任一项所述的装置，其中，所述装置还包括：
    接收单元，配置为接收控制信号，所述控制信号配置为从所述RAM和/或所述存储器的各个地址中，选择需要读取的第二数据的地址；
    读出单元，配置为根据所述控制信号，将所述第二数据的地址中读出所述第二数据。
  9. 一种存储装置，所述装置包括：RAM、存储器和连接所述RAM和所述存储器的地址总线；
    其中，第一数据根据寻址空间，存入所述存储器和所述RAM，所述寻址空间是需要存储所述第一数据需要的空间。
  10. 根据权利要求9所述的装置，其中，当所述第一数据写入所述RAM时，所述RAM的片选位是有效状态；所述存储器的片选位是无效状态；当所述第一数据中未写入所述RAM的数据写入所述存储器时，所述存储器的片选位是有效状态；所述RAM的片选位是无效状态；
    其中，所述RAM的片选位是与所述RAM连接的地址总线的最高位；所述存储器的片选位是与所述存储器连接的地址总线的最高位。
  11. 根据权利要求9或10所述的装置，其中，所述存储器是至少一个 寄存器。
  12. 根据权利要求11所述的装置，其中，所述装置还包括：
    多选器，配置为根据控制信号，将所述已存储的第二数据读出。
  13. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行权利要求1至4任一项所述的数据存储方法。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017157110A1 (zh) * 2016-03-18 2017-09-21 深圳市中兴微电子技术有限公司 高速访问双倍速率同步动态随机存储器的控制方法及装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1477519A (zh) * 2002-08-20 2004-02-25 深圳市中兴通讯股份有限公司上海第二 一种处理器的地址空间优化方法
CN1716180A (zh) * 2004-06-30 2006-01-04 富士通株式会社 半导体器件
CN101944385A (zh) * 2010-06-24 2011-01-12 新邮通信设备有限公司 一种存储器
CN102684976A (zh) * 2011-03-10 2012-09-19 中兴通讯股份有限公司 一种基于ddr sdram进行数据读写的方法、装置及系统
CN104572573A (zh) * 2014-12-26 2015-04-29 深圳市国微电子有限公司 数据存储方法、存储模块和可编程逻辑器件

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5696917A (en) * 1994-06-03 1997-12-09 Intel Corporation Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory
US6279093B1 (en) * 1998-11-24 2001-08-21 Dell Usa, L.P. Computer system and method for preparing a computer-readable medium
JP3918434B2 (ja) * 2001-01-05 2007-05-23 セイコーエプソン株式会社 情報処理装置
CA2522862A1 (en) * 2003-05-23 2005-03-24 Washington University Intelligent data storage and processing using fpga devices
US20060294312A1 (en) * 2004-05-27 2006-12-28 Silverbrook Research Pty Ltd Generation sequences
US7363454B2 (en) * 2004-12-10 2008-04-22 International Business Machines Corporation Storage pool space allocation across multiple locations
US8452929B2 (en) * 2005-04-21 2013-05-28 Violin Memory Inc. Method and system for storage of data in non-volatile media
CN100466602C (zh) * 2005-04-28 2009-03-04 华为技术有限公司 动态共享存储器存储空间的实现方法
JP2009199199A (ja) * 2008-02-20 2009-09-03 Hitachi Ltd ストレージシステム及びそのデータライト方法
CN101661438B (zh) * 2008-08-29 2013-08-28 鸿富锦精密工业（深圳）有限公司 电子装置及中央处理器寻址空间扩展方法
CN101950273B (zh) * 2010-09-26 2012-05-23 中国人民解放军海军工程大学 一种dsp数据区动态管理方法
US8886990B2 (en) * 2011-01-27 2014-11-11 Apple Inc. Block management schemes in hybrid SLC/MLC memory
CN103377135B (zh) * 2012-04-25 2016-04-13 上海东软载波微电子有限公司 寻址方法、装置及系统
US9489148B2 (en) * 2013-03-13 2016-11-08 Seagate Technology Llc Selecting between non-volatile memory units having different minimum addressable data unit sizes

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1477519A (zh) * 2002-08-20 2004-02-25 深圳市中兴通讯股份有限公司上海第二 一种处理器的地址空间优化方法
CN1716180A (zh) * 2004-06-30 2006-01-04 富士通株式会社 半导体器件
CN101944385A (zh) * 2010-06-24 2011-01-12 新邮通信设备有限公司 一种存储器
CN102684976A (zh) * 2011-03-10 2012-09-19 中兴通讯股份有限公司 一种基于ddr sdram进行数据读写的方法、装置及系统
CN104572573A (zh) * 2014-12-26 2015-04-29 深圳市国微电子有限公司 数据存储方法、存储模块和可编程逻辑器件

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017157110A1 (zh) * 2016-03-18 2017-09-21 深圳市中兴微电子技术有限公司 高速访问双倍速率同步动态随机存储器的控制方法及装置

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