WO2017157110A1 - 高速访问双倍速率同步动态随机存储器的控制方法及装置 - Google Patents

高速访问双倍速率同步动态随机存储器的控制方法及装置 Download PDF

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WO2017157110A1
WO2017157110A1 PCT/CN2017/072862 CN2017072862W WO2017157110A1 WO 2017157110 A1 WO2017157110 A1 WO 2017157110A1 CN 2017072862 W CN2017072862 W CN 2017072862W WO 2017157110 A1 WO2017157110 A1 WO 2017157110A1
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read
write
channel
data
ddr
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PCT/CN2017/072862
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English (en)
French (fr)
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岳雷霆
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深圳市中兴微电子技术有限公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization

Definitions

  • the present invention relates to access technologies, and in particular, to a method and apparatus for controlling high speed access double rate synchronous dynamic random access memory (DDR).
  • DDR synchronous dynamic random access memory
  • Ethernet data traffic in network systems is getting larger and larger, and more service functions are required.
  • a buffer space of sufficient size is needed to cache data.
  • the data packets are taken out of the cache and sent out.
  • SDRAM Synchronous Dynamic Random Access Memory
  • the access to the DDR in the current network communication device is mainly performed by converting the access address into the row and column mapping, first selecting the corresponding page by the page selection operation, and then selecting the corresponding address through the address line.
  • the segment reads and writes data. If the read and write addresses of the DDR are not continuous, frequent page selection operations will be performed during the access, which greatly reduces the access efficiency of the DDR; at the same time, the imbalance of the read and write will also reduce the access efficiency of the DDR.
  • the traditional solution is to divide the DDR into fixed cache blocks. Although this method can improve the access efficiency of DDR, there are some drawbacks: for example, the division of fixed cache blocks, if the cache block is too large, it may waste DDR. The memory space; if the cache block is too small, it will not increase the rate, etc., which will reduce the access efficiency of DDR.
  • the embodiments of the present invention are intended to provide a method and apparatus for controlling high-speed access to DDR, and at least solve the problems existing in the prior art.
  • Embodiments of the present invention provide a method for controlling a high speed access double rate synchronous dynamic random access memory, the method comprising:
  • read/write operations for multiple channels are scheduled according to a weighted round-robin scheduling policy, and the read/write bandwidth is balanced.
  • the method further includes:
  • the read/write operation requests for each channel are sequentially cached according to the burst buffer scheduling policy, and the cache order is recorded;
  • the DDR is divided into variable cache blocks according to a dynamic configuration policy, including:
  • Each of the regions is configured by a configurable cache block, and each cache block corresponds to a cache pointer BP;
  • an area close to the buffer size is selected according to the packet length of the data packet, and is stored in the cache block corresponding to the BP.
  • the DDR is divided into variable cache blocks according to a dynamic configuration policy, and include:
  • the BP of each area is configured as a linked list, and when the data packet is written into the DDR, the BP of the header of the area list is applied, and when the data packet reads the DDR, the BP is written to the tail of the linked list;
  • the read and write operations are performed based on the variable cache block
  • the read/write operations for multiple channels are scheduled according to the weighted round-robin scheduling policy, and the read/write bandwidth is balanced, including:
  • Each read/write channel is assigned a weight, and each time a read/write operation is detected, the weight is subtracted from the packet length of the read or written data packet;
  • the weight can be adjusted and the weight is increased according to the setting timing of the timer.
  • the read/write operation when the read/write operation is performed based on the variable cache block, the read/write operations for multiple channels are scheduled according to the weighted round-robin scheduling policy, and the read/write bandwidth is balanced, and the method further includes:
  • the channel length of the read or written data packet is selected to be close to the last read/write operation to ensure DDR address is continuous;
  • the read/write operation when the read/write operation is performed based on the variable cache block, the read/write operations for multiple channels are scheduled according to the weighted round-robin scheduling policy, and the read/write bandwidth is balanced, and the method further includes:
  • the read/write operation requests for each channel are sequentially cached, and the cache order is recorded, including:
  • Two FIFO queues are respectively configured for the read direction channel and the write direction channel.
  • the first FIFO is used for buffering read and write commands
  • the second FIFO is used for buffering read and write data.
  • the read and write commands and the channel flags are sequentially buffered according to the scheduling result of the read/write operations for the multiple channels, and the read and write command order and the channel mark order are stored in the first FIFO as the cache order.
  • Read and write commands are passed to the DDR in the order of the read and write commands.
  • the performing the read/write operation on the variable cache block in the DDR according to the cache order includes:
  • the write data of each channel is buffered into the second FIFO, and the other write data is scheduled by the cached channel, and then the write data is written according to the channel mark order.
  • the data is written to the corresponding second FIFO according to the channel mark, and the corresponding channel can read the data from the second FIFO.
  • a high-speed access double-rate synchronous dynamic random access memory control device includes:
  • a cache control module configured to divide the double rate synchronous dynamic random access memory DDR into a variable cache block according to a dynamic configuration policy
  • the scheduling module configured to perform read and write operations based on the variable cache block, schedule read/write operations for multiple channels according to a weighted round-robin scheduling policy, and balance read/write bandwidth.
  • the device further includes: a channel control module, configured to:
  • the read/write operation requests for each channel are sequentially cached according to the burst buffer scheduling policy, and the cache order is recorded;
  • the cache control module is further configured to:
  • Each of the regions is configured by a configurable cache block, and each cache block corresponds to a cache pointer BP;
  • an area close to the buffer size is selected according to the packet length of the data packet, and is stored in the cache block corresponding to the BP.
  • the cache control module is further configured to:
  • the BP of each area is configured as a linked list, and when the data packet is written into the DDR, the BP of the header of the area list is applied, and when the data packet reads the DDR, the BP is written to the tail of the linked list;
  • the scheduling module is further configured to:
  • Each read/write channel is assigned a weight, and each time a read/write operation is detected, the weight is subtracted from the packet length of the read or written data packet;
  • the weight can be adjusted and the weight is increased according to the setting timing of the timer.
  • the scheduling module is further configured to:
  • the packet whose read or write packet length is similar to the last read/write operation is selected to ensure that the DDR address is continuous;
  • the scheduling module is further configured to:
  • the channel control module is further configured to:
  • Two FIFO queues are respectively configured for the read direction channel and the write direction channel.
  • the first FIFO is used for buffering read and write commands
  • the second FIFO is used for buffering read and write data.
  • the read and write commands and the channel flags are sequentially buffered according to the scheduling result of the read/write operations for the multiple channels, and the read and write command order and the channel mark order are stored in the first FIFO as the cache order.
  • Read and write commands are passed to the DDR in the order of the read and write commands.
  • the channel control module is further configured to:
  • the write data of each channel is buffered into the second FIFO, and the other write data is scheduled by the cached channel, and then the write data is written according to the channel mark order.
  • the data is written to the corresponding second FIFO according to the channel mark, and the corresponding channel can read the data from the second FIFO.
  • the cache control module, the scheduling module, and the channel control module may use a central processing unit (CPU) and a digital signal processor (DSP) when performing processing. Digital Singnal Processor) or Field-Programmable Gate Array (FPGA) implementation.
  • CPU central processing unit
  • DSP digital signal processor
  • Digital Singnal Processor or Field-Programmable Gate Array (FPGA) implementation.
  • the method for controlling high-speed access DDR includes: dividing a double rate synchronous dynamic random access memory (DDR) into a variable cache block according to a dynamic configuration policy; and performing read and write operations based on the variable cache block, The read/write operations for multiple channels are scheduled according to a weighted round-robin scheduling policy, and the read/write bandwidth is balanced. With the embodiment of the invention, the access efficiency and the read/write rate of the DDR are improved.
  • DDR double rate synchronous dynamic random access memory
  • FIG. 1 is a schematic flowchart of an implementation process according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic structural diagram of a device according to Embodiment 2 of the present invention.
  • FIG. 3 is a workflow diagram corresponding to a cache control module according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of initializing a DDR space to which an embodiment of the present invention is applied;
  • FIG. 5 is a schematic diagram of BP initialization according to an embodiment of the present invention.
  • FIG. 6 is a structural diagram of a channel control module to which an embodiment of the present invention is applied;
  • FIG. 7 is a flowchart of a scheduling module application to which an embodiment of the present invention is applied.
  • FIG. 9 is a flow chart of a data readout DDR to which an embodiment of the present invention is applied.
  • a method for controlling high-speed access DDR according to an embodiment of the present invention includes:
  • Step 101 Divide the DDR into a variable cache block according to a dynamic configuration policy.
  • Step 102 Perform read/write operations for multiple channels according to the weighted cyclic scheduling policy when performing read and write operations based on the variable cache block, and balance read/write bandwidth.
  • Step 103 After obtaining a read/write operation request for multiple channel bursts, the read/write operation requests for each channel are sequentially cached according to the burst buffer scheduling policy, and the cache order is recorded.
  • Step 104 Perform a current read/write operation on the variable cache block in the DDR according to the cache order, and support each of the read and write operations during data read and write. The scheduling of other read/write operation requests for the channel.
  • the dividing the DDR into a variable cache block according to the dynamic configuration policy includes: dividing the address space of the DDR into a plurality of areas, and configuring a start address and an end address of each area as Each of the regions may be configured by a configurable cache block, each cache block corresponding to a cache pointer BP; for a data packet written to the DDR, the cache size is selected according to the packet length of the data packet The close area is stored in the cache block corresponding to BP.
  • the dividing the DDR into a variable cache block according to the dynamic configuration policy further includes: configuring BP of each area as a linked list, and writing the data packet to the DDR BP is applied to the header of the area linked list.
  • the BP is written to the end of the linked list; the packet size of the DDR data is selected to be written once or read according to the BP size, and the data packet exceeding the first threshold is selected. Long, configured to write or read longer data that meets the second threshold, and to ensure that the address written or read once is continuous.
  • the read/write operations for multiple channels are scheduled according to the weighted round-robin scheduling policy, and the read/write bandwidth is read. Balancing includes: assigning a weight to each read/write channel, and subtracting the weight of the read or written data packet for each read/write operation detected; the weight may be Adjust and increase the weight according to the timer setting.
  • the read/write operations for multiple channels are scheduled according to the weighted round-robin scheduling policy, and the read/write bandwidth is read. Balancing, also includes: if a read/write operation for multiple channels is detected, and If the length of the application data is not greater than the current weight of the channel, the channel whose read or write packet has a packet length close to the last read/write operation is selected to ensure that the DDR address is continuous.
  • Performing balancing further includes: configuring a first total weight for the write direction channel; configuring a second total weight for the read direction channel; continuously scheduling the data of the write direction channel to a weight of 0, or detecting all writes according to the first total weight After the data writing of the direction channel is completed, the data of the read direction channel is continuously scheduled to a weight of 0, or until the data reading of all the read channels is detected according to the second total weight, the scheduling is terminated.
  • the read/write operation request for each channel is sequentially cached according to the burst buffer scheduling policy, and the cache order is recorded, including: configuring two advanced parameters for the read direction channel and the write direction channel respectively.
  • First out queue FIFO in the two FIFOs, the first FIFO is used to buffer read and write commands, the second FIFO is used to buffer read and write data, and the read and write commands are sequentially executed according to the scheduling result of scheduling read/write operations for multiple channels.
  • the channel tag is cached, the read and write command order and the channel tag order are stored in the first FIFO as the cache order, and the read and write commands are transmitted to the DDR according to the read and write command order.
  • the performing the read/write operation on the variable cache block in the DDR according to the cache order includes: if it is detected for a write direction channel
  • the write operation caches the write data of each channel into the second FIFO, and schedules other write data through the buffered channel, and then writes the write data to the DDR according to the channel mark order; if it is detected for reading After the read operation of the direction channel, after the data is read, the data is written into the corresponding second FIFO according to the channel mark, and the corresponding channel can read the data from the second FIFO.
  • a high-speed access double-rate synchronous dynamic random access memory control device includes:
  • a cache control module configured to divide the double rate synchronous dynamic random access memory DDR into a variable cache block according to a dynamic configuration policy
  • the scheduling module configured to perform read and write operations based on the variable cache block, schedule read/write operations for multiple channels according to a weighted round-robin scheduling policy, and balance read/write bandwidth.
  • the device further includes: a channel control module, configured to:
  • the read/write operation requests for each channel are sequentially cached according to the burst buffer scheduling policy, and the cache order is recorded;
  • the cache control module is further configured to:
  • Each of the regions is configured by a configurable cache block, and each cache block corresponds to a cache pointer BP;
  • an area close to the buffer size is selected according to the packet length of the data packet, and is stored in the cache block corresponding to the BP.
  • the cache control module is further configured to:
  • the BP of each area is configured as a linked list, and when the data packet is written into the DDR, the BP of the header of the area list is applied, and when the data packet reads the DDR, the BP is written to the tail of the linked list;
  • the scheduling module is further configured to:
  • Each read/write channel is assigned a weight, and each time a read/write operation is detected, the weight is subtracted from the packet length of the read or written data packet;
  • the weight can be adjusted and the weight is increased according to the setting timing of the timer.
  • the scheduling module is further configured to:
  • the channel length of the read or written data packet is selected to be close to the last read/write operation to ensure DDR address is continuous;
  • the scheduling module is further configured to:
  • the channel control module is further configured to:
  • Two FIFO queues are respectively configured for the read direction channel and the write direction channel.
  • the first FIFO is used for buffering read and write commands
  • the second FIFO is used for buffering read and write data.
  • the read and write commands and the channel flags are sequentially buffered according to the scheduling result of the read/write operations for the multiple channels, and the read and write command order and the channel mark order are stored in the first FIFO as the cache order.
  • Read and write commands are passed to the DDR in the order of the read and write commands.
  • the channel control module is further configured to:
  • the write data of each channel is buffered into the second FIFO, and the other completed write data is scheduled through the cached completed channel, and then according to The channel marking order writes write data to the DDR;
  • the data is written to the corresponding second FIFO according to the channel mark, and the corresponding channel can read the data from the second FIFO.
  • the access to the DDR in the current network communication device is mainly performed by converting the access address into the row and column mapping, first selecting the corresponding page by the page selection operation, and then selecting the corresponding page through the address line.
  • the address segment reads and writes data. If the read and write addresses of the DDR are not continuous, frequent page selection operations will be performed during the access, which greatly reduces the access efficiency of the DDR; at the same time, the imbalance of the read and write will also reduce the access efficiency of the DDR.
  • the traditional solution is to divide the DDR into fixed cache blocks (such as 64 bytes) and read and write them in units of cache blocks. This method can make the DDR read and write addresses continuous, thus improving the access efficiency of DDR.
  • the scheme of adopting such a fixed cache block still has the following drawbacks:
  • the cache block is too large, the memory space of the DDR may be wasted. If the cache block is too small, the rate may not be increased.
  • the traditional access method is to perform the next read and write operation when a read/write operation is completed. Since the DDR has a delay in the read/write direction, the traditional access method wastes part of the time on the delay wait. , reducing the access efficiency of DDR.
  • the high-speed access DDR control method of the embodiment of the present invention can improve the DDR access efficiency and the read/write rate through the mechanism of DDR space dynamic cache block division and management, multi-channel read/write equalization control, and continuous read and write operations, including The following:
  • the dynamic cache block partitioning and management mechanism the DDR address space is divided into several regions, each region is composed of multiple buffers, and the cache size of each region can be configured through Different cache pointers (BP, Buffer Point) manage the address space.
  • BP Buffer Point
  • the dynamic cache block division and management mechanism is implemented, including: 1.1) dividing the address space of the DDR into several areas, the start address and the end address of each area can be configured; 1.2) each area is configurable by a size Composition, each cache corresponds to a BP; 1.3) For a data packet, select the area whose buffer size is close to the packet length according to the packet length, and store it in the corresponding BP cache; 1.4) BP of each area is a linked list, data When writing a DDR packet, apply for BP in the header of the area list. When the packet reads DDR, write BP to the end of the linked list. 1.5) Select the size of the DDR data to be written or read once according to the BP size. The packet length is as long as possible to write or read relatively long data, and to ensure that the address written or read once is continuous, reducing the DDR page selection operation.
  • the multi-channel read-write equalization control mechanism in the DDR controller, the weighted round-robin scheduling algorithm (WRR, Weighted Round Robin) is used to schedule multiple channels, and the read-write bandwidth is balanced to reduce read-write switching.
  • WRR Weighted Round Robin
  • the multi-channel read/write equalization control mechanism is implemented, including: 2.1) assigning a weight to each read/write channel, and each time a read/write operation occurs, the weight is subtracted from the packet length, and the weight timing is increased; 2.2) on the basis of 2.1 If multiple channels have access to the DDR request and the weights are all satisfactory, try to ensure that the channel with the packet length is close to the last read and write, to ensure that the DDR address is continuous and reduce the page selection operation; 2.3) set one for the read direction and the write direction.
  • Total weight on the basis of 2.1, continuously schedule the write direction channel data to a weight of 0 or all write channel data is completed, and then continuously read the read direction data to a weight of 0 or all read channel data is completed, reduce read and write switching and achieve read Write balance.
  • the mechanism for implementing continuous read and write operations includes: 3.1) Each of the read and write directions has two FIFOs (First Input First Output), one of which is a FIFO buffer read/write command (data length), and a FIFO buffer read. Write data; 3.2) DDR controller caches the read and write commands and channel markers in turn according to the scheduling result, and passes the read and write commands to DDR in order; 3.3) If it is a write access, the DDR controller writes the data of each channel as well.
  • FIFOs First Input First Output
  • DDR controller caches the read and write commands and channel markers in turn according to the scheduling result, and passes the read and write commands to DDR in order; 3.3) If it is a write access, the DDR controller writes the data of each channel as well.
  • the channel can dispatch other data, then the DDR controller writes the data to the DDR according to the channel marking order; 3.4) If it is a read access, the DDR controller reads the data and follows the channel. The tag writes the data to the corresponding FIFO, and the corresponding channel can read the data from the FIFO.
  • FIG. 2 is a schematic structural diagram of a device to which an embodiment of the present invention is applied.
  • the device is applied to a DDR control circuit of an independent chip (such as the DDR controller in FIG. 2), and the first embodiment and the implementation thereof are implemented.
  • Each implementation in the manner is implemented in the independent chip, and the DDR controller performs a read/write operation (read operation or write operation) to the DDR.
  • DDR31 is used to store data.
  • the DDR controller includes a cache control module 21, a scheduling module 22, and a plurality of channel control modules 23 (such as channel control modules 1-4 in FIG. 2, each channel control module controls a channel in a read/write direction). In practice, these channel control modules are not limited.
  • the cache control module is configured to implement a dynamic cache block division and management mechanism. Specifically, the DDR address space is divided into several areas, each area is composed of multiple buffers, and the cache size of each area can be configured. The address space is managed by different buffer pointers (BP, Buffer Point).
  • BP buffer pointers
  • the dynamic cache block division and management mechanism is implemented, including: 1.1) dividing the address space of the DDR into several areas, the start address and the end address of each area can be configured; 1.2) each area is configurable by a size Composition, each cache corresponds to a BP; 1.3) For a data packet, select the area whose buffer size is close to the packet length according to the packet length, and store it in the corresponding BP cache; 1.4) BP of each area is a linked list, data When writing a DDR packet, apply for BP in the header of the area list. When the packet reads DDR, write BP to the end of the linked list. 1.5) Select the size of the DDR data to be written or read once according to the BP size. The packet length is as long as possible to write or read relatively long data, and to ensure that the address written or read once is continuous, reducing the DDR page selection operation.
  • the scheduling module is configured to implement a multi-channel read/write equalization control mechanism. Specifically, in the DDR controller, multiple channels are scheduled by a weighted round robining algorithm (WRR, Weighted Round Robin), and the read/write bandwidth is balanced. , reduce read and write switching.
  • WRR weighted round robining algorithm
  • the multi-channel read/write equalization control mechanism is implemented, including: 2.1) assigning a weight to each read/write channel, and each time a read/write operation occurs, the weight is subtracted from the packet length, and the weight timing is increased; 2.2) on the basis of 2.1 If multiple channels have access to the DDR request and the weights are all satisfactory, try to ensure that the channel with the packet length is close to the last read and write, to ensure that the DDR address is continuous and reduce the page selection operation; 2.3) set one for the read direction and the write direction.
  • Total weight on the basis of 2.1, continuously schedule the write direction channel data to a weight of 0 or all write channel data is completed, and then continuously read the read direction data to a weight of 0 or all read channel data is completed, reduce read and write switching and achieve read Write balance.
  • the channel control module is configured to implement a continuous read and write operation mechanism.
  • the Burst Outstanding scheduling mechanism is supported.
  • the requests of each channel may be sequentially cached.
  • the DDR is read and written according to the cache order.
  • each channel can perform other scheduling without waiting for the read and write returns.
  • the mechanism for implementing continuous read and write operations includes: 3.1)
  • the read and write directions each have two FIFOs (First Input First Output), one of which is a FIFO buffer read/write command (data length), and one FIFO buffer read.
  • DDR controller caches the read and write commands and channel markers in turn according to the scheduling result, and passes the read and write commands to DDR in order; 3.3) If it is a write access, the DDR controller writes the data of each channel as well. Cache into the data FIFO, after the buffer is completed, the channel can dispatch other data, then the DDR controller writes the data to the DDR according to the channel marking order; 3.4) If it is a read access, the DDR controller reads the data and follows the channel. The tag writes the data to the corresponding FIFO, and the corresponding channel can read the data from the FIFO.
  • FIG. 3 shows the workflow of the cache control module. The specific steps are as follows:
  • Step 201 Initialize the DDR address space first.
  • the initialization divides the DDR space into N regions, wherein the cached particles of the first region are configured as M bytes, and the second region is configured to be 2 Mbytes...
  • the buffer particles of the last region are configured as N*M bytes, such as Figure 4, after completion, proceeds to step 202;
  • Step 202 Initialize a BP pool in each area.
  • the BP pool is a 1-K pointer list, stored in a ram of depth K, and each address has an indication flag. 1 indicates that the BP has been used, 0 indicates that it has not been used, and proceeds to step 203 after completion;
  • Step 203 accept the request sent by the scheduling module, if it is a write request, proceeds to step 204, otherwise proceeds to step 205;
  • Step 204 Take the current idle BP from the BP pool of the corresponding area, send it to the scheduling module, set the current BP indication to 1, and point the idle BP pointer to the next idle BP, and write the data to the DDR. Step 203;
  • Step 205 Read the data in the DDR from the corresponding BP address, return to the scheduling module, and set the current BP indication to 0. After completing, proceed to step 203.
  • Figure 6 is a block diagram of the channel control module.
  • the corresponding controller of the channel buffers the read/write command and the read/write data, and the read/write command is stored in the first FIFO (specifically, Figure 6 In the command FIFO), the read/write data is stored in the second FIFO (specifically the data FIFO in Figure 6).
  • the scheduling module is responsible for scheduling each channel request, and all channels perform WRR scheduling through the scheduling module, and the scheduling structure is passed to the cache control module.
  • Step 301 The scheduling module initializes a weight for each channel, and the weight value can be configured, and a total weight is configured for each read and write, and the weight of each channel is refreshed every fixed time;
  • Step 302 enter the write scheduling period, query the access request of each write channel, if there is no request, proceed to step 306, otherwise proceed to step 303;
  • Step 303 Compare all the channel application packet lengths that meet the requirements with the BP size of the last write DDR. If the packet length of one channel matches the previous BP size, select the channel, if there are multiple, then Polling one of them, ensuring that the BP written this time is adjacent to the last write, and the address space is continuous; if not, polling one of all input channels, and proceeding to step 304;
  • Step 304 according to the polling result, apply for the BP of the corresponding area to the cache control module, send the write request to the cache control module, and take the data from the corresponding channel control module and send it to the cache control module, and proceed to step 305;
  • Step 305 the weight of the corresponding channel and the total weight of the write channel minus the scheduling packet length, if the total weight of the write channel has been 0, then proceeds to step 306, otherwise proceeds to step 302;
  • Step 306 enter the read scheduling period, query the access request of each read channel, if there is no request, proceed to step 302, otherwise proceeds to step 307;
  • Step 307 comparing all the channel application BPs that meet the requirements with the last read BP, preferentially selecting the channel adjacent to the BP and BP last time, if not, polling one of the channels, and proceeding to step 308;
  • Step 308 according to the polling result, the read request is sent to the cache control device, and accept the read content of the DDR is sent to the channel control device, proceeds to step 309;
  • step 309 the weight of the corresponding channel and the total weight of the read channel are subtracted from the scheduling packet length. If the total weight of the read channel is already 0, the process proceeds to step 302, otherwise, the process proceeds to step 306.
  • FIG. 8 is a workflow diagram of writing data access DDR according to the present invention, including:
  • Step 401 the write channel sends a write request to the channel control module, the channel control module checks whether the internal command and the data FIFO are not full, then, proceeds to step 402;
  • Step 402 the channel control module writes the command and data into the command FIFO and the data FIFO respectively, and the corresponding write channel can perform subsequent data scheduling, without waiting for the write result, and then returns to step 401;
  • Step 403 the channel control module checks whether the command FIFO is empty, non-empty, the write request is sent to the scheduling module, proceeds to step 404;
  • Step 404 the scheduling module according to the previously described scheduling algorithm, polling the channel data, apply for BP to the cache control module, proceeds to step 405;
  • Step 405 the cache control module assigns the data BP to the scheduling module, points the idle BP to the next value, and writes the data to the DDR, and returns the success indication to the scheduling module, and proceeds to step 406;
  • Step 406 The cache control module returns BP to the corresponding channel control module, and the channel control module notifies the write channel to complete the write, and notifies the write channel to BP, ends the current operation, and returns to step 403.
  • FIG. 9 is a workflow diagram of reading data access DDR according to the present invention, including:
  • Step 501 the read channel sends the read request and the read BP to the channel control module, the channel control module checks whether the internal command and the data FIFO are not full, and then proceeds to step 502;
  • Step 502 the channel control module writes the command and BP into the command FIFO, and the corresponding read channel can perform subsequent data scheduling, without waiting for the read result, and then returns to step 501;
  • Step 503 the channel control module checks whether the command FIFO is empty, non-empty, then send the read request and BP to the scheduling module, proceeds to step 504;
  • Step 504 the scheduling module according to the previously described scheduling algorithm, polling the channel data, initiate a read request to the cache control, proceeds to step 505;
  • Step 505 the cache control module sets the BP to idle BP, and reads data from the DDR, returns to the scheduling module to read data, proceeds to step 506;
  • Step 506 The cache control module returns the data to the corresponding channel control module, the channel control module writes the data to the data FIFO, and notifies the read channel that the read is completed, and the read channel can read the data from the FIFO, and ends the operation, and returns to step C. .
  • the particle size of each region can be configured; at the same time, the data packets of each read/write channel are balanced according to the WRR algorithm; the burst continuous access in the read/write direction is supported, and the traditional DDR access method can achieve read and write address connection
  • the traditional DDR access method can achieve read and write address connection
  • the integrated modules described in the embodiments of the present invention may also be stored in a computer readable storage medium if they are implemented in the form of software functional modules and sold or used as separate products. Based on such understanding, the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions.
  • a computer device (which may be a personal computer, server, or network device, etc.) is caused to perform all or part of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .
  • embodiments of the invention are not limited to any specific combination of hardware and software.
  • the embodiment of the present invention further provides a computer storage medium, wherein a computer program is stored, and the computer program is used to execute a high-speed access DDR control method according to an embodiment of the present invention.
  • the double rate synchronous dynamic random access memory is divided into variable cache blocks according to a dynamic configuration policy; when the read and write operations are performed based on the variable cache block, the weighted round-robin scheduling policy is targeted to Read/write operations for multiple channels are scheduled and the read/write bandwidth is balanced.
  • the access efficiency and the read/write rate of the DDR are improved.

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Abstract

一种高速访问双倍速率同步动态随机存储器的控制方法及装置，所述方法包括：将双倍速率同步动态随机存储器（DDR）按照动态配置策略划分为可变的缓存块（101）；基于所述可变的缓存块进行读写操作时，根据加权循环调度策略对针对多个通道的读/写操作进行调度，并对读/写带宽进行平衡（102）。

Description

高速访问双倍速率同步动态随机存储器的控制方法及装置 技术领域
本发明涉及访问技术，尤其涉及一种高速访问双倍速率同步动态随机存储器(DDR，Double Data Rate SDRAM)的控制方法及装置。
背景技术
随着高速通信系统的迅猛发展，网络系统中的以太网数据流量越来越大，所需服务功能也越来越多，对传输的以太网包，需要一块足够大小的缓存空间，将数据缓存起来，在完成以太网数据的分析、交换、路由以及用户定义的服务功能后，再将数据报文从缓存中取出并发送出去。
由于当前的网络通信设备速率很高，所需的缓存空间也非常大，对缓存空间的访问速率也有不小的要求，在这种情况下，传统的同步动态随机存储器(SDRAM，Synchronous Dynamic Random Access Memory)已经不能满足需求，而DDR具有更高的工作频率，更快的速度，更大的缓存空间，已经成为通信网络中最为重要的缓存器件。
现有技术中，在当前网络通信设备中对DDR的访问，主要是通过将访问地址转化成行列映射，首先经过选页操作选到相应的页面(page)，再通过地址线选到相应的地址段对数据进行读写。如果DDR的读写地址不连续，则访问时会进行频繁的选页操作，大大降低了DDR的访问效率；同时读写的不均衡也会降低DDR的访问效率。传统的解决方法主要是将DDR划分为固定的缓存块，虽然，这种方法可以提高DDR的访问效率，但是也存在一些弊端：比如固定缓存块的划分，如果缓存块过大，可能会浪费DDR的内存空间；如果缓存块过小，则起不到提高速率的作用等等，这些，都会降低DDR的访问效率。
发明内容
有鉴于此，本发明实施例希望提供一种高速访问DDR的控制方法及装置，至少解决了现有技术存在的问题。
本发明实施例的技术方案是这样实现的：
本发明实施例一种高速访问双倍速率同步动态随机存储器的控制方法，所述方法包括：
将双倍速率同步动态随机存储器DDR按照动态配置策略划分为可变的缓存块；
基于所述可变的缓存块进行读写操作时，根据加权循环调度策略对针对多个通道的读/写操作进行调度，并对读/写带宽进行平衡。
上述方案中，所述方法还包括：
获取针对多个通道突发的读/写操作请求后，根据突发缓冲调度策略将对各个通道的读/写操作请求依次缓存下来，并记录缓存次序；
根据所述缓存次序，对所述DDR中的所述可变的缓存块进行本次读/写操作，在进行本次读/写操作对应的数据读写期间，支持针对所述各个通道其他读/写操作请求的调度。
上述方案中，所述将DDR按照动态配置策略划分为可变的缓存块，包括：
将DDR的地址空间划分为数个区域，配置每个区域的起始地址和结束地址为均可配置；
配置所述每个区域由大小可配置的缓存块组成，每个缓存块均对应一个缓存指针BP；
对于写入DDR的数据包，根据所述数据包的包长选择缓存大小与其接近的区域，将其存入对应BP的缓存块里面。
上述方案中，所述将DDR按照动态配置策略划分为可变的缓存块，还 包括：
配置每个区域的BP为一个链表，将所述数据包写入所述DDR时，申请区域链表首部的BP，数据包读出DDR时，将BP写入链表的尾部；
根据BP大小选择执行一次写入或读出DDR数据的数据包大小，对于超过第一阈值的数据包包长，配置为一次写入或读出符合第二阈值的较长数据，并且保证一次写入或读出的地址是连续的。
上述方案中，所述基于所述可变的缓存块进行读写操作时，根据加权循环调度策略对针对多个通道的读/写操作进行调度，并对读/写带宽进行平衡，包括：
为每一个读/写通道分配一个权重，每检测到发生了一次读/写操作，则将所述权重减去读出或写入的数据包的包长；
所述权重可调整，并按照定时器的设置定时增加所述权重。
上述方案中，所述基于所述可变的缓存块进行读写操作时，根据加权循环调度策略对针对多个通道的读/写操作进行调度，并对读/写带宽进行平衡，还包括：
如果检测到针对多个通道的读/写操作，且申请数据长度均不大于通道当前权重，则选择读出或写入的数据包的包长与上次读/写操作相近的通道，以保证DDR地址连续；
上述方案中，所述基于所述可变的缓存块进行读写操作时，根据加权循环调度策略对针对多个通道的读/写操作进行调度，并对读/写带宽进行平衡，还包括：
为写方向通道配置第一总权重；
为读方向通道配置第二总权重；
连续调度写方向通道的数据到权重为0、或者根据所述第一总权重检测到所有写方向通道的数据写入完成之后，连续调度读方向通道的数据到权 重为0、或者直至根据所述第二总权重检测到所有读通道的数据读出完成，结束调度。
上述方案中，根据突发缓冲调度策略将对各个通道的读/写操作请求依次缓存下来，并记录缓存次序，包括：
为读方向通道和写方向通道分别配置两个先进先出队列FIFO，两个FIFO中，第一FIFO用于缓存读写命令，第二FIFO用于缓存读写数据；
根据针对多个通道的读/写操作进行调度的调度结果依次将读写命令和通道标记缓存下来，将读写命令次序和通道标记次序作为所述缓存次序并存入所述第一FIFO中，按照所述读写命令次序将读写命令传递给所述DDR。
上述方案中，所述根据所述缓存次序，对所述DDR中的所述可变的缓存块进行本次读/写操作，包括：
如果检测到是针对写方向通道的写入操作，则将各个通道的写数据缓存到第二FIFO里面，通过缓存完成的通道去调度其他的写数据，之后按照所述通道标记次序将写数据写入DDR；
如果检测到是针对读方向通道的读出操作，则将数据读出后，按照所述通道标记将数据写入对应的第二FIFO，对应通道可以将数据从第二FIFO读出。
本发明实施例的一种高速访问双倍速率同步动态随机存储器的控制装置，所述装置包括：
缓存控制模块，配置为将双倍速率同步动态随机存储器DDR按照动态配置策略划分为可变的缓存块；
调度模块，配置为基于所述可变的缓存块进行读写操作时，根据加权循环调度策略对针对多个通道的读/写操作进行调度，并对读/写带宽进行平衡。
上述方案中，所述装置还包括：通道控制模块，配置为：
获取针对多个通道突发的读/写操作请求后，根据突发缓冲调度策略将对各个通道的读/写操作请求依次缓存下来，并记录缓存次序；
根据所述缓存次序，对所述DDR中的所述可变的缓存块进行本次读/写操作，在进行本次读/写操作对应的数据读写期间，支持针对所述各个通道其他读/写操作请求的调度。
上述方案中，所述缓存控制模块，还配置为：
将DDR的地址空间划分为数个区域，配置每个区域的起始地址和结束地址为均可配置；
配置所述每个区域由大小可配置的缓存块组成，每个缓存块均对应一个缓存指针BP；
对于写入DDR的数据包，根据所述数据包的包长选择缓存大小与其接近的区域，将其存入对应BP的缓存块里面。
上述方案中，所述缓存控制模块，还配置为：
配置每个区域的BP为一个链表，将所述数据包写入所述DDR时，申请区域链表首部的BP，数据包读出DDR时，将BP写入链表的尾部；
根据BP大小选择执行一次写入或读出DDR数据的数据包大小，对于超过第一阈值的数据包包长，配置为一次写入或读出符合第二阈值的较长数据，并且保证一次写入或读出的地址是连续的。
上述方案中，所述调度模块，还配置为：
为每一个读/写通道分配一个权重，每检测到发生了一次读/写操作，则将所述权重减去读出或写入的数据包的包长；
所述权重可调整，并按照定时器的设置定时增加所述权重。
上述方案中，所述调度模块，还配置为：
如果检测到针对多个通道的读/写操作，且申请数据长度均不大于通道 当前权重，则选择读出或写入的数据包的包长与上次读/写操作相近的通道，以保证DDR地址连续；
上述方案中，所述调度模块，还配置为：
为写方向通道配置第一总权重；
为读方向通道配置第二总权重；
连续调度写方向通道的数据到权重为0、或者根据所述第一总权重检测到所有写方向通道的数据写入完成之后，连续调度读方向通道的数据到权重为0、或者直至根据所述第二总权重检测到所有读通道的数据读出完成，结束调度。
上述方案中，所述通道控制模块，还配置为：
为读方向通道和写方向通道分别配置两个先进先出队列FIFO，两个FIFO中，第一FIFO用于缓存读写命令，第二FIFO用于缓存读写数据；
根据针对多个通道的读/写操作进行调度的调度结果依次将读写命令和通道标记缓存下来，将读写命令次序和通道标记次序作为所述缓存次序并存入所述第一FIFO中，按照所述读写命令次序将读写命令传递给所述DDR。
上述方案中，所述通道控制模块，还配置为：
如果检测到是针对写方向通道的写入操作，则将各个通道的写数据缓存到第二FIFO里面，通过缓存完成的通道去调度其他的写数据，之后按照所述通道标记次序将写数据写入DDR；
如果检测到是针对读方向通道的读出操作，则将数据读出后，按照所述通道标记将数据写入对应的第二FIFO，对应通道可以将数据从第二FIFO读出。
所述缓存控制模块、所述调度模块、所述通道控制模块在执行处理时，可以采用中央处理器(CPU，Central Processing Unit)、数字信号处理器(DSP， Digital Singnal Processor)或可编程逻辑阵列(FPGA，Field－Programmable Gate Array)实现。
本发明实施例的高速访问DDR的控制方法包括：将双倍速率同步动态随机存储器(DDR)按照动态配置策略划分为可变的缓存块；基于所述可变的缓存块进行读写操作时，根据加权循环调度策略对针对多个通道的读/写操作进行调度，并对读/写带宽进行平衡。采用本发明实施例，提高了DDR的访问效率和读写速率。
附图说明
图1为本发明实施例一的实现流程示意图；
图2为本发明实施例二的装置组成结构示意图；
图3为应用本发明实施例的缓存控制模块对应的工作流程图；
图4为应用本发明实施例的DDR空间初始化示意图；
图5为应用本发明实施例的BP初始化示意图；
图6为应用本发明实施例的通道控制模块结构图；
图7为应用本发明实施例的调度模块工作流程图；
图8为应用本发明实施例的数据写入DDR流程图；
图9为应用本发明实施例的数据读出DDR流程图。
具体实施方式
下面结合附图对技术方案的实施作进一步的详细描述。
本发明实施例的一种高速访问DDR的控制方法，如图1所示，所述方法包括：
步骤101、将DDR按照动态配置策略划分为可变的缓存块。
步骤102、基于所述可变的缓存块进行读写操作时，根据加权循环调度策略对针对多个通道的读/写操作进行调度，并对读/写带宽进行平衡。
步骤103、获取针对多个通道突发的读/写操作请求后，根据突发缓冲调度策略将对各个通道的读/写操作请求依次缓存下来，并记录缓存次序。
步骤104、根据所述缓存次序，对所述DDR中的所述可变的缓存块进行本次读/写操作，在进行本次读/写操作对应的数据读写期间，支持针对所述各个通道其他读/写操作请求的调度。
在本发明实施例一实施方式中，所述将DDR按照动态配置策略划分为可变的缓存块，包括：将DDR的地址空间划分为数个区域，配置每个区域的起始地址和结束地址为均可配置；配置所述每个区域由大小可配置的缓存块组成，每个缓存块均对应一个缓存指针BP；对于写入DDR的数据包，根据所述数据包的包长选择缓存大小与其接近的区域，将其存入对应BP的缓存块里面。
在本发明实施例一实施方式中，所述将DDR按照动态配置策略划分为可变的缓存块，还包括：配置每个区域的BP为一个链表，将所述数据包写入所述DDR时，申请区域链表首部的BP，数据包读出DDR时，将BP写入链表的尾部；根据BP大小选择执行一次写入或读出DDR数据的数据包大小，对于超过第一阈值的数据包包长，配置为一次写入或读出符合第二阈值的较长数据，并且保证一次写入或读出的地址是连续的。
在本发明实施例一实施方式中，所述基于所述可变的缓存块进行读写操作时，根据加权循环调度策略对针对多个通道的读/写操作进行调度，并对读/写带宽进行平衡，包括：为每一个读/写通道分配一个权重，每检测到发生了一次读/写操作，则将所述权重减去读出或写入的数据包的包长；所述权重可调整，并按照定时器的设置定时增加所述权重。
在本发明实施例一实施方式中，所述基于所述可变的缓存块进行读写操作时，根据加权循环调度策略对针对多个通道的读/写操作进行调度，并对读/写带宽进行平衡，还包括：如果检测到针对多个通道的读/写操作，且 申请数据长度均不大于通道当前权重，则选择读出或写入的数据包的包长与上次读/写操作相近的通道，以保证DDR地址连续。
在本发明实施例一实施方式中，所述基于所述可变的缓存块进行读写操作时，根据加权循环调度策略对针对多个通道的读/写操作进行调度，并对读/写带宽进行平衡，还包括：为写方向通道配置第一总权重；为读方向通道配置第二总权重；连续调度写方向通道的数据到权重为0、或者根据所述第一总权重检测到所有写方向通道的数据写入完成之后，连续调度读方向通道的数据到权重为0、或者直至根据所述第二总权重检测到所有读通道的数据读出完成，结束调度。
在本发明实施例一实施方式中，根据突发缓冲调度策略将对各个通道的读/写操作请求依次缓存下来，并记录缓存次序，包括：为读方向通道和写方向通道分别配置两个先进先出队列FIFO，两个FIFO中，第一FIFO用于缓存读写命令，第二FIFO用于缓存读写数据；根据针对多个通道的读/写操作进行调度的调度结果依次将读写命令和通道标记缓存下来，将读写命令次序和通道标记次序作为所述缓存次序并存入所述第一FIFO中，按照所述读写命令次序将读写命令传递给所述DDR。
在本发明实施例一实施方式中，所述根据所述缓存次序，对所述DDR中的所述可变的缓存块进行本次读/写操作，包括：如果检测到是针对写方向通道的写入操作，则将各个通道的写数据缓存到第二FIFO里面，通过缓存完成的通道去调度其他的写数据，之后按照所述通道标记次序将写数据写入DDR；如果检测到是针对读方向通道的读出操作，则将数据读出后，按照所述通道标记将数据写入对应的第二FIFO，对应通道可以将数据从第二FIFO读出。
本发明实施例的一种高速访问双倍速率同步动态随机存储器的控制装置，所述装置包括：
缓存控制模块，配置为将双倍速率同步动态随机存储器DDR按照动态配置策略划分为可变的缓存块；
调度模块，配置为基于所述可变的缓存块进行读写操作时，根据加权循环调度策略对针对多个通道的读/写操作进行调度，并对读/写带宽进行平衡。
在本发明实施例一实施方式中，所述装置还包括：通道控制模块，配置为：
获取针对多个通道突发的读/写操作请求后，根据突发缓冲调度策略将对各个通道的读/写操作请求依次缓存下来，并记录缓存次序；
根据所述缓存次序，对所述DDR中的所述可变的缓存块进行本次读/写操作，在进行本次读/写操作对应的数据读写期间，支持针对所述各个通道其他读/写操作请求的调度。
在本发明实施例一实施方式中，所述缓存控制模块，还配置为：
将DDR的地址空间划分为数个区域，配置每个区域的起始地址和结束地址为均可配置；
配置所述每个区域由大小可配置的缓存块组成，每个缓存块均对应一个缓存指针BP；
对于写入DDR的数据包，根据所述数据包的包长选择缓存大小与其接近的区域，将其存入对应BP的缓存块里面。
在本发明实施例一实施方式中，所述缓存控制模块，还配置为：
配置每个区域的BP为一个链表，将所述数据包写入所述DDR时，申请区域链表首部的BP，数据包读出DDR时，将BP写入链表的尾部；
根据BP大小选择执行一次写入或读出DDR数据的数据包大小，对于超过第一阈值的数据包包长，配置为一次写入或读出符合第二阈值的较长数据，并且保证一次写入或读出的地址是连续的。
在本发明实施例一实施方式中，所述调度模块，还配置为：
为每一个读/写通道分配一个权重，每检测到发生了一次读/写操作，则将所述权重减去读出或写入的数据包的包长；
所述权重可调整，并按照定时器的设置定时增加所述权重。
在本发明实施例一实施方式中，所述调度模块，还配置为：
如果检测到针对多个通道的读/写操作，且申请数据长度均不大于通道当前权重，则选择读出或写入的数据包的包长与上次读/写操作相近的通道，以保证DDR地址连续；
在本发明实施例一实施方式中，所述调度模块，还配置为：
为写方向通道配置第一总权重；
为读方向通道配置第二总权重；
连续调度写方向通道的数据到权重为0、或者根据所述第一总权重检测到所有写方向通道的数据写入完成之后，连续调度读方向通道的数据到权重为0、或者直至根据所述第二总权重检测到所有读通道的数据读出完成，结束调度。
在本发明实施例一实施方式中，所述通道控制模块，还配置为：
为读方向通道和写方向通道分别配置两个先进先出队列FIFO，两个FIFO中，第一FIFO用于缓存读写命令，第二FIFO用于缓存读写数据；
根据针对多个通道的读/写操作进行调度的调度结果依次将读写命令和通道标记缓存下来，将读写命令次序和通道标记次序作为所述缓存次序并存入所述第一FIFO中，按照所述读写命令次序将读写命令传递给所述DDR。
在本发明实施例一实施方式中，所述通道控制模块，还配置为：
如果检测到是针对写方向通道的写入操作，则将各个通道的写数据缓存到第二FIFO里面，通过缓存完成的通道去调度其他的写数据，之后按照 所述通道标记次序将写数据写入DDR；
如果检测到是针对读方向通道的读出操作，则将数据读出后，按照所述通道标记将数据写入对应的第二FIFO，对应通道可以将数据从第二FIFO读出。
以一个现实应用场景为例对本发明实施例阐述如下：
在现有技术中，在当前网络通信设备中对DDR的访问，主要是通过将访问地址转化成行列映射，首先经过选页操作选到相应的页面(page)，再通过地址线选到相应的地址段对数据进行读写。如果DDR的读写地址不连续，则访问时会进行频繁的选页操作，大大降低了DDR的访问效率；同时读写的不均衡也会降低DDR的访问效率。传统的解决方法主要是将DDR划分为固定的缓存块(比如64字节)，以缓存块为单位对其进行读写，这种方法能够使DDR的读写地址连续，从而提高DDR的访问效率，但是，如举例说明，采用这种固定缓存块的方案仍然存在如下弊端：
比如固定缓存块的划分，如果缓存块过大，可能会浪费DDR的内存空间，如果缓存块过小，则起不到提高速率的作用。
另外，采用传统的控制方法很难实现读写均衡，同时有较多的读写切换，降低了访问效率，在多通道同时访问DDR时，也很难实现均衡调度。
而且，采用传统的访问方式是在一个读写操作完成时，才进行下一个读写操作，由于DDR在读写方向均存在时延，使得传统的访问方式会将部分时间浪费在时延等待上，降低了DDR的访问效率。
对于上述问题，本发明实施例高速访问DDR的控制方法，通过DDR空间动态缓存块划分及管理、多通道读写均衡控制、连续读写操作的机制可以提高DDR访问效率和读/写速率，包括以下内容：
一，动态缓存块划分及管理机制：将DDR地址空间划分为数个区域，每个区域由多个缓存(buffer)组成，每个区域的缓存大小均可配置，通过 不同的缓存指针(BP，Buffer Point)对地址空间进行管理。
这里，实现动态缓存块划分及管理机制，包括：1.1)将DDR的地址空间划分为数个区域，每个区域的起始地址和结束地址均可配置；1.2)每个区域由大小可配置的缓存组成，每个缓存均对应一个BP；1.3)对于一个数据包，根据包长选择缓存大小与其接近的区域，将其存入对应BP的缓存里面；1.4)每个区域的BP为一个链表，数据包写入DDR时，申请该区域链表首部的BP，数据包读出DDR时，将BP写入链表的尾部；1.5)根据BP大小选择一次写入或读出DDR数据的大小，对于较大的包长，尽量一次写入或读出比较长的数据，并且保证一次写入或读出的地址是连续，减少DDR的选页操作。
二，多通道读写均衡控制机制：在DDR控制器中，通过加权循环调度算法(WRR，Weighted Round Robin)对多个通道进行调度，同时对读写带宽进行平衡，减少读写切换。
这里，实现多通道读写均衡控制机制，包括：2.1)为每一个读写通道分配一个权重，每发生一次读/写操作，将权重减去包长，权重定时增加；2.2)在2.1基础上，如果多个通道有访问DDR请求，且权重均满足要求，尽量保证选择包长与上次读写相近的通道，保证DDR地址连续，减少选页操作；2.3)读方向和写方向各设一个总权重，在2.1的基础上，连续调度写方向通道数据到权重为0或者所有写通道数据完成，然后连续调度读方向数据到权重为0或者所有读通道数据完成，减少读写切换并实现读写均衡。
三，连续读写操作的机制：支持突发缓冲(Burst Outstanding)调度机制，对于多个通道突发的读写请求，可以将各个通道的请求依次缓存下来，按照缓存次序对DDR进行读写，在数据读写期间各个通道可以进行其他调度，不必等待本次读写返回结果。
这里，实现连续读写操作的机制，包括：3.1)读写方向各有2个先进先出队列(FIFO，First Input First Output)，其中一个FIFO缓存读写命令(数据长度)，一个FIFO缓存读写数据；3.2)DDR控制器按照调度结果依次将读写命令和通道标记缓存下来，并按照次序将读写命令传递给DDR；3.3)如果是写访问，DDR控制器将各个通道的写数据也缓存到数据FIFO里面，缓存完成之后该通道可以去调度别的数据，之后DDR控制器按照通道标记次序将数据写入DDR；3.4)如果是读访问，DDR控制器将数据读出后，按照通道标记将数据写入对应的FIFO，对应通道可以将数据从FIFO读出。
具体的，如图2所示为应用本发明实施例的一个装置结构组成示意图，该装置应用于独立芯片的DDR控制电路(如图2中的DDR控制器)，将上述实施例一及其实施方式中的各个实现过程在该独立芯片中具体实现，由DDR控制器实现对DDR的读/写操作(读入操作或写出操作)。DDR31用于存储数据。其中，所述DDR控制器包括缓存控制模块21、调度模块22和多个通道控制模块23(如图2中的通道控制模块1-4，每个通道控制模块控制一个读/写方向的通道)，实际应用中不限于这些通道控制模块。
所述缓存控制模块配置为实现动态缓存块划分及管理机制，具体的，将DDR地址空间划分为数个区域，每个区域由多个缓存(buffer)组成，每个区域的缓存大小均可配置，通过不同的缓存指针(BP，Buffer Point)对地址空间进行管理。其中，实现动态缓存块划分及管理机制，包括：1.1)将DDR的地址空间划分为数个区域，每个区域的起始地址和结束地址均可配置；1.2)每个区域由大小可配置的缓存组成，每个缓存均对应一个BP；1.3)对于一个数据包，根据包长选择缓存大小与其接近的区域，将其存入对应BP的缓存里面；1.4)每个区域的BP为一个链表，数据包写入DDR时，申请该区域链表首部的BP，数据包读出DDR时，将BP写入链表的尾部；1.5)根据BP大小选择一次写入或读出DDR数据的大小，对于较大的 包长，尽量一次写入或读出比较长的数据，并且保证一次写入或读出的地址是连续，减少DDR的选页操作。
所述调度模块配置为实现多通道读写均衡控制机制，具体的，在DDR控制器中，通过加权循环调度算法(WRR，Weighted Round Robin)对多个通道进行调度，同时对读写带宽进行平衡，减少读写切换。其中，实现多通道读写均衡控制机制，包括：2.1)为每一个读写通道分配一个权重，每发生一次读/写操作，将权重减去包长，权重定时增加；2.2)在2.1基础上，如果多个通道有访问DDR请求，且权重均满足要求，尽量保证选择包长与上次读写相近的通道，保证DDR地址连续，减少选页操作；2.3)读方向和写方向各设一个总权重，在2.1的基础上，连续调度写方向通道数据到权重为0或者所有写通道数据完成，然后连续调度读方向数据到权重为0或者所有读通道数据完成，减少读写切换并实现读写均衡。
所述通道控制模块配置为实现连续读写操作的机制，具体的，支持突发缓冲(Burst Outstanding)调度机制，对于多个通道突发的读写请求，可以将各个通道的请求依次缓存下来，按照缓存次序对DDR进行读写，在数据读写期间各个通道可以进行其他调度，不必等待本次读写返回结果。其中，实现连续读写操作的机制，包括：3.1)读写方向各有2个先进先出队列(FIFO，First Input First Output)，其中一个FIFO缓存读写命令(数据长度)，一个FIFO缓存读写数据；3.2)DDR控制器按照调度结果依次将读写命令和通道标记缓存下来，并按照次序将读写命令传递给DDR；3.3)如果是写访问，DDR控制器将各个通道的写数据也缓存到数据FIFO里面，缓存完成之后该通道可以去调度别的数据，之后DDR控制器按照通道标记次序将数据写入DDR；3.4)如果是读访问，DDR控制器将数据读出后，按照通道标记将数据写入对应的FIFO，对应通道可以将数据从FIFO读出。
如图3所示为缓存控制模块的工作流程，具体步骤如下：
步骤201、首先进行DDR地址空间的初始化。该初始化将DDR空间划分为N个区域，其中第一个区域的缓存颗粒配置成M字节，第二个区域配成2M字节…最后一个区域的缓存颗粒配置成N*M字节，如图4所示，完成后进入步骤202；
步骤202、每个区域初始化一个BP池，如图5所示，该BP池为1个1-K的指针链表，存储在1块深度为K的ram里，每个地址都有一个指示标识，为1表示该BP已经被使用，为0表示还未被使用，完成后进入步骤203；
步骤203、接受调度模块发过来的请求，如果是写请求，进入步骤204，否则进入步骤205；
步骤204、从对应区域的BP池里取出当前的空闲BP，发送给调度模块，并将当前BP指示置为1，将空闲BP指针指向下一个空闲BP，并将数据写入DDR，完成后进入步骤203；
步骤205、从对应的BP地址读出DDR中的数据，返回给调度模块，并将当前BP指示置为0，完成后进入步骤203。
图6是通道控制模块的结构图，某个通道访问DDR时，该通道对应的控制器将读/写命令和读/写数据缓存下来，读/写命令存入第一FIFO(具体为图6中的命令FIFO)，将读/写数据存入第二FIFO(具体为图6中的数据FIFO)。调度模块负责调度各个通道请求，所有通道通过调度模块进行WRR调度，将调度结构传递给缓存控制模块。
调度模块的工作流程如图7所示，具体步骤如下：
步骤301、调度模块给每个通道初始化一个权重，该权重值可以配置，并给读写各配置一个总权重，每隔固定时间刷新各通道权重；
步骤302、进入写调度周期，查询各个写通道的访问请求，如果没有任何请求则进入步骤306，否则进入步骤303；
步骤303、将符合要求的所有通道申请包长与上次写入DDR的BP大小进行比较，如果有一个通道的包长符合上次的BP大小，则选择这个通道，如果有多个满足，则轮询其中一个，保证本次写入的BP与上次写入的相邻，地址空间连续；如果都不满足，则轮询所有输入通道中的一个，进入步骤304；
步骤304、根据轮询结果，向缓存控制模块申请对应区域的BP，将写请求发给缓存控制模块，并从对应通道控制模块取出数据发送给缓存控制模块，进入步骤305；
步骤305、将对应通道的权重和写通道总权重减去调度包长，如果写通道总权重已经为0，则进入步骤306，否则进入步骤302；
步骤306、进入读调度周期，查询各个读通道的访问请求，如果没有任何请求则进入步骤302，否则进入步骤307；
步骤307、将符合要求的所有通道申请BP与上次读取的BP进行比较，优先选择本次BP与上次BP相邻的通道，如果没有，则轮询其中给一个通道，进入步骤308；
步骤308、根据轮询结果，将读请求发给缓存控制装置，并接受DDR的读出内容发送给通道控制装置，进入步骤309；
步骤309、将对应通道的权重和读通道总权重减去调度包长，如果读通道总权重已经为0则进入步骤302，否则进入步骤306。
图8为本发明写数据访问DDR的工作流程，包括：
步骤401、写通道将写请求发送给该通道控制模块，通道控制模块检查内部命令和数据FIFO是否非满，是，则进入步骤402；
步骤402、通道控制模块将命令和数据分别写入命令FIFO和数据FIFO，此时对应写通道可以进行后续数据调度，无须等待写结果，之后返回步骤401；
步骤403、通道控制模块检查命令FIFO是否为空，非空则将写请求发送给调度模块，进入步骤404；
步骤404、调度模块根据之前描述调度算法，轮询到该通道数据，向缓存控制模块申请BP，进入步骤405；
步骤405、缓存控制模块将数据分配BP给调度模块，将空闲BP指向下一个值，并将数据写入DDR，返回给调度模块写成功指示，进入步骤406；
步骤406、缓存控制模块将BP返回给对应通道控制模块，通道控制模块通知写通道写完成，并告知写通道对应BP，结束本次操作，返回步骤403。
图9为本发明读数据访问DDR的工作流程，包括：
步骤501、读通道将读请求和读BP发送给该通道控制模块，通道控制模块检查内部命令和数据FIFO是否非满，是，则进入步骤502；
步骤502、通道控制模块将命令和BP写入命令FIFO，此时对应读通道可以进行后续数据调度，无须等待读结果，之后返回步骤501；
步骤503、通道控制模块检查命令FIFO是否为空，非空，则将读请求和BP发送给调度模块，进入步骤504；
步骤504、调度模块根据之前描述调度算法，轮询到该通道数据，向缓存控制发起读请求，进入步骤505；
步骤505、缓存控制模块将该BP置为空闲BP，并从DDR中读出数据，返回给调度模块读数据，进入步骤506；
步骤506、缓存控制模块将数据返回给对应通道控制模块，通道控制模块将数据写入数据FIFO，并通知读通道读完成，读通道可以从FIFO中读出数据，结束本次操作，返回步骤C。
采用本发明实施例，通过将DDR地址划分为多个区域，每个区域颗粒大小可以配置；同时根据WRR算法平衡各个读写通道的数据包；支持读写方向的突发连续访问，与传统的DDR访问方法相比，可以实现读写地址连 续均衡，减少DDR的选页和切换操作，同时支持突发缓冲调度，避免了传统方法在读写时的数据等待，提高了DDR访问效率。
本发明实施例所述集成的模块如果以软件功能模块的形式实现并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明实施例的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机、服务器、或者网络设备等)执行本发明各个实施例所述方法的全部或部分。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。这样，本发明实施例不限制于任何特定的硬件和软件结合。
相应的，本发明实施例还提供一种计算机存储介质，其中存储有计算机程序，该计算机程序用于执行本发明实施例的一种高速访问DDR的控制方法。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
采用本发明实施例，将双倍速率同步动态随机存储器(DDR)按照动态配置策略划分为可变的缓存块；基于所述可变的缓存块进行读写操作时，根据加权循环调度策略对针对多个通道的读/写操作进行调度，并对读/写带宽进行平衡。采用本发明实施例，提高了DDR的访问效率和读写速率。

Claims (18)

  1. 一种高速访问双倍速率同步动态随机存储器的控制方法，所述方法包括：
    将双倍速率同步动态随机存储器DDR按照动态配置策略划分为可变的缓存块；
    基于所述可变的缓存块进行读写操作时，根据加权循环调度策略对针对多个通道的读/写操作进行调度，并对读/写带宽进行平衡。
  2. 根据权利要求1所述的方法，其中，所述方法还包括：
    获取针对多个通道突发的读/写操作请求后，根据突发缓冲调度策略将对各个通道的读/写操作请求依次缓存下来，并记录缓存次序；
    根据所述缓存次序，对所述DDR中的所述可变的缓存块进行本次读/写操作，在进行本次读/写操作对应的数据读写期间，支持针对所述各个通道其他读/写操作请求的调度。
  3. 根据权利要求2所述的方法，其中，所述将DDR按照动态配置策略划分为可变的缓存块，包括：
    将DDR的地址空间划分为数个区域，配置每个区域的起始地址和结束地址为均可配置；
    配置所述每个区域由大小可配置的缓存块组成，每个缓存块均对应一个缓存指针BP；
    对于写入DDR的数据包，根据所述数据包的包长选择缓存大小与其接近的区域，将其存入对应BP的缓存块里面。
  4. 根据权利要求3所述的方法，其中，所述将DDR按照动态配置策略划分为可变的缓存块，还包括：
    配置每个区域的BP为一个链表，将所述数据包写入所述DDR时，申请区域链表首部的BP，数据包读出DDR时，将BP写入链表的尾部；
    根据BP大小选择执行一次写入或读出DDR数据的数据包大小，对于超过第一阈值的数据包包长，配置为一次写入或读出符合第二阈值的较长数据，并且保证一次写入或读出的地址是连续的。
  5. 根据权利要求1所述的方法，其中，所述基于所述可变的缓存块进行读写操作时，根据加权循环调度策略对针对多个通道的读/写操作进行调度，并对读/写带宽进行平衡，包括：
    为每一个读/写通道分配一个权重，每检测到发生了一次读/写操作，则将所述权重减去读出或写入的数据包的包长；
    所述权重可调整，并按照定时器的设置定时增加所述权重。
  6. 根据权利要求5所述的方法，其中，所述基于所述可变的缓存块进行读写操作时，根据加权循环调度策略对针对多个通道的读/写操作进行调度，并对读/写带宽进行平衡，还包括：
    如果检测到针对多个通道的读/写操作，且申请数据长度均不大于通道当前权重，则选择读出或写入的数据包的包长与上次读/写操作相近的通道，以保证DDR地址连续；
  7. 根据权利要求5或6所述的方法，其中，所述基于所述可变的缓存块进行读写操作时，根据加权循环调度策略对针对多个通道的读/写操作进行调度，并对读/写带宽进行平衡，还包括：
    为写方向通道配置第一总权重；
    为读方向通道配置第二总权重；
    连续调度写方向通道的数据到权重为0、或者根据所述第一总权重检测到所有写方向通道的数据写入完成之后，连续调度读方向通道的数据到权重为0、或者直至根据所述第二总权重检测到所有读通道的数据读出完成，结束调度。
  8. 根据权利要求2所述的方法，其中，根据突发缓冲调度策略将对各 个通道的读/写操作请求依次缓存下来，并记录缓存次序，包括：
    为读方向通道和写方向通道分别配置两个先进先出队列FIFO，两个FIFO中，第一FIFO用于缓存读写命令，第二FIFO用于缓存读写数据；
    根据针对多个通道的读/写操作进行调度的调度结果依次将读写命令和通道标记缓存下来，将读写命令次序和通道标记次序作为所述缓存次序并存入所述第一FIFO中，按照所述读写命令次序将读写命令传递给所述DDR。
  9. 根据权利要求8所述的方法，其中，所述根据所述缓存次序，对所述DDR中的所述可变的缓存块进行本次读/写操作，包括：
    如果检测到是针对写方向通道的写入操作，则将各个通道的写数据缓存到第二FIFO里面，通过缓存完成的通道去调度其他的写数据，之后按照所述通道标记次序将写数据写入DDR；
    如果检测到是针对读方向通道的读出操作，则将数据读出后，按照所述通道标记将数据写入对应的第二FIFO，对应通道可以将数据从第二FIFO读出。
  10. 一种高速访问双倍速率同步动态随机存储器的控制装置，所述装置包括：
    缓存控制模块，配置为将双倍速率同步动态随机存储器DDR按照动态配置策略划分为可变的缓存块；
    调度模块，配置为基于所述可变的缓存块进行读写操作时，根据加权循环调度策略对针对多个通道的读/写操作进行调度，并对读/写带宽进行平衡。
  11. 根据权利要求10所述的装置，其中，所述装置还包括：通道控制模块，配置为：
    获取针对多个通道突发的读/写操作请求后，根据突发缓冲调度策略将 对各个通道的读/写操作请求依次缓存下来，并记录缓存次序；
    根据所述缓存次序，对所述DDR中的所述可变的缓存块进行本次读/写操作，在进行本次读/写操作对应的数据读写期间，支持针对所述各个通道其他读/写操作请求的调度。
  12. 根据权利要求11所述的装置，其中，所述缓存控制模块，还配置为：
    将DDR的地址空间划分为数个区域，配置每个区域的起始地址和结束地址为均可配置；
    配置所述每个区域由大小可配置的缓存块组成，每个缓存块均对应一个缓存指针BP；
    对于写入DDR的数据包，根据所述数据包的包长选择缓存大小与其接近的区域，将其存入对应BP的缓存块里面。
  13. 根据权利要求12所述的装置，其中，所述缓存控制模块，还配置为：
    配置每个区域的BP为一个链表，将所述数据包写入所述DDR时，申请区域链表首部的BP，数据包读出DDR时，将BP写入链表的尾部；
    根据BP大小选择执行一次写入或读出DDR数据的数据包大小，对于超过第一阈值的数据包包长，配置为一次写入或读出符合第二阈值的较长数据，并且保证一次写入或读出的地址是连续的。
  14. 根据权利要求10所述的装置，其中，所述调度模块，还配置为：
    为每一个读/写通道分配一个权重，每检测到发生了一次读/写操作，则将所述权重减去读出或写入的数据包的包长；
    所述权重可调整，并按照定时器的设置定时增加所述权重。
  15. 根据权利要求14所述的装置，其中，所述调度模块，还配置为：
    如果检测到针对多个通道的读/写操作，且申请数据长度均不大于通道 当前权重，则选择读出或写入的数据包的包长与上次读/写操作相近的通道，以保证DDR地址连续；
  16. 根据权利要求14或15所述的装置，其中，所述调度模块，还配置为：
    为写方向通道配置第一总权重；
    为读方向通道配置第二总权重；
    连续调度写方向通道的数据到权重为0、或者根据所述第一总权重检测到所有写方向通道的数据写入完成之后，连续调度读方向通道的数据到权重为0、或者直至根据所述第二总权重检测到所有读通道的数据读出完成，结束调度。
  17. 根据权利要求11所述的装置，其中，所述通道控制模块，还配置为：
    为读方向通道和写方向通道分别配置两个先进先出队列FIFO，两个FIFO中，第一FIFO用于缓存读写命令，第二FIFO用于缓存读写数据；
    根据针对多个通道的读/写操作进行调度的调度结果依次将读写命令和通道标记缓存下来，将读写命令次序和通道标记次序作为所述缓存次序并存入所述第一FIFO中，按照所述读写命令次序将读写命令传递给所述DDR。
  18. 根据权利要求17所述的装置，其中，所述通道控制模块，还配置为：
    如果检测到是针对写方向通道的写入操作，则将各个通道的写数据缓存到第二FIFO里面，通过缓存完成的通道去调度其他的写数据，之后按照所述通道标记次序将写数据写入DDR；
    如果检测到是针对读方向通道的读出操作，则将数据读出后，按照所述通道标记将数据写入对应的第二FIFO，对应通道可以将数据从第二FIFO 读出。
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CN113360420A (zh) * 2020-03-06 2021-09-07 北京机械设备研究所 一种内存控制方法和装置
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CN111831606B (zh) * 2020-07-17 2023-03-31 电子科技大学 一种基于fpga的数据包精准延时方法及系统
CN111831606A (zh) * 2020-07-17 2020-10-27 电子科技大学 一种基于fpga的数据包精准延时方法及系统
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CN114257263A (zh) * 2021-11-22 2022-03-29 中电科思仪科技股份有限公司 一种基于触发的高机动信道模拟装置及方法
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CN117373501B (zh) * 2023-12-08 2024-04-09 深圳星云智联科技有限公司 统计业务执行速率提升方法及相关装置

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