CN1685261A - 电光组件 - Google Patents

电光组件 Download PDF

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CN1685261A
CN1685261A CNA038225255A CN03822525A CN1685261A CN 1685261 A CN1685261 A CN 1685261A CN A038225255 A CNA038225255 A CN A038225255A CN 03822525 A CN03822525 A CN 03822525A CN 1685261 A CN1685261 A CN 1685261A
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CN100468108C (zh
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S·托勒
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Intel Corp
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    • G—PHYSICS
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    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4204—Packages, e.g. shape, construction, internal or external details the coupling comprising intermediate optical elements, e.g. lenses, holograms
    • G02B6/4214—Packages, e.g. shape, construction, internal or external details the coupling comprising intermediate optical elements, e.g. lenses, holograms the intermediate optical element having redirecting reflective means, e.g. mirrors, prisms for deflecting the radiation from horizontal to down- or upward direction toward a device
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
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    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
    • G02B6/4228—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements
    • G02B6/4232—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements using the surface tension of fluid solder to align the elements, e.g. solder bump techniques
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    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73209—Bump and HDI connectors
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
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    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
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    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Optical Integrated Circuits (AREA)
  • Optical Couplings Of Light Guides (AREA)
  • Semiconductor Lasers (AREA)

Abstract

一种包括微电子封装(20)和光学基底(62)的电子组件，其中该光学基底包括耦合器(70)和波导(72)。电光元件(54)被配置成把来自微电子封装(20)的电信号转换到用于传输到耦合器(70)和波导(72)的光信号，和/或接收光信号并把它转换到用于传输到微电子封装(20)的电信号。

Description

电光组件
技术领域
本发明涉及在一盒子中封装带有一个或多个光学部件的微电子构件的装置及方法及其功能方式。本发明特别涉及使电光元件与波导对准并在微电子封装和基底之间固定电光元件的一种封装技术。
背景技术
较高的频带宽度，改良的性能，较低的成本，以及提高的小型化是计算机工业为要加强在计算机内芯片之间传播的现有目的。我们已经知道，集成的电路部件已经提高的小型化，且这个目的达到后，需要微电子晶片变得更小。人们希望的是与微电子封装类似的小型化，因为它可减少成本和部件的外形尺寸(形状因素)。
至于获得，例如，10Gb/s数量级或更高的较高频宽来说，光学芯片间的传播面临着许多挑战。属于这些挑战之列的是在微处理器和光发射器/探测器芯片之间的高频宽，低等待时间的传播，在光发射器/探测器芯片和波导之间的对准与耦合，以及维持可接受的成本。直至现在，应付所有这些挑战的困难已经表示芯片间的传播一般是用电子学方式获得。
应付面临光学芯片间的传播挑战将提供显著的好处，包括不仅减少来自诸如电磁干涉(EMI)和交叉干扰源的噪声，而且还包括光学芯片间传播提供的较高的频宽。但是，为电光组件提供对可能设置在印刷电路板上波导结构的良好对准，在微处理器和光发射器/探测器芯片之间低的电寄生，以及相当低的制造成本是必须的。
所以，发展用于把带有与集成到印刷电路板(光电PCB)上的耦合器和波导对准的电光元件的微电子封装固定到诸如印刷电路板的基底上来提供合适的电光组件将是有利的。
附图简述
尽管本发明由权利要求书特别指出并明白地提出哪些内容为本发明权利要求的结论。但是，当与附图结合在一起阅读时，从本发明的下面描述中可更为容易地肯定本发明的优点，其中：
图1是根据本发明邻接到保护薄膜的微电子封装核心的侧横截面图；
图2是配置在图1中微电子封装核心的开口之内的微电子晶片的侧横截面图；
图3是在已封装好之后的图2中组件的侧横截面图；
图4是已除去保护薄膜之后的图3中的组件的侧横截面图；
图5是说明在微子晶片上电接触的图4中组件的侧横截面图；
图6是说明覆盖电接触的电介质薄层的图5中组件的侧横截面图；
图7是在多个经过电介质薄层的通路形成之后的图6中组件的侧横截面图；
图8是说明多个导电轨道的形成的图7中组件的侧横截面图；
图9是说明焊料掩膜和通路的图8中组件的侧横截面图；
图10是说明多个焊料球的形成的图9中组件的侧横截面图；
图11是说明电连接到微电子晶片的电光元件的图10中组件的侧横截面图；以及
图12是固定到具有耦合器和波导的电光印刷电路板上的图11中组件的侧横截面图。
具体实施方式
虽然图1-12图示说明了本发明的各种视图，但这些图并不意味着用精确的细节来描绘出微电子和光学的组件。相反，这些图以一种更为清楚的方法来说明微电子和光学的组件来传达本发明的概念。另外，应注意到在整个各种视图中，在各图之间共用的元件保留相同的数字指示。
本发明包括一种封装技术，这个技术以把电光元件与在电光PCB上的耦合器和波导对准的方式把微电子封装固定到电光PCB上。在微电子封装和电光PCB之间配置这电光元件来把来自在微电子封装中微电子晶片的电信号转换成被传输到耦合器和波导的光信号。或者，这电光元件可把来自在电光PCB上的耦合器和波导的光信号转换成被传输到微电子封装的电信号。
图1示出微电子封装核心20，它包括用于制作具有在其中形成通道22的微电子封装的基本上是平面的材料。这通道22从第一、有源表面24到对面的、第二表面26全部地经过微电子封装核心20延伸。正如将会理解的，通道22可以是具有受到唯一限制的任何形状和尺寸，这个形状和尺寸就是要被合适的做成能容纳在其中的、相应的微电子晶片的尺寸和形状将在下面讨论。
图1示出邻接在保护薄膜28上的该微电子封装核心第二表面26。具有有源表面32和后背表面34的微电子晶片30被放置在微电子封装核心20的通道22中，如图2所示。这样来放置微电子晶片30，使得它的有源表面32邻接于可能在其上具有诸如硅有机树脂粘合剂的保护薄膜28上。保护aies28到微电子封装核心20的第一，即有源，表面24和微电子晶片30的有源表面32，如图4所示。或者，保护薄膜28可以是依赖于封装工艺的非粘合薄膜。
尤其是，在放置微电子晶片30和微电子封装核心20之前，在能供封装工艺过程之用的铸模或其它的设备部件中来涂敷粘合型保护薄膜28。保护薄膜28还可以是诸如EPFE(乙烯-五氟乙烯)或聚四氟乙烯(Teflon)的非粘合的薄膜，它通过可供封装工艺过程之用的铸模或其它设备的部件的内表面被固定在微电子晶片有源表面32和微电子封装核心的第一，即有源表面24上。在这两种情况中，保护aies28将从微电子晶片30的有源表面32和微电子封装核心20的第一，即有源表面24被除去，接着就是封装过程。
于是，采用封装材料36填入在微电子封装核心20中未被微电子晶片30占有的通道22中的部分来封装微电子晶片30，如图5所示。微电子晶片30的封装可通过包括但并不限于转移和加压模铸，和撒布的任何已知的工艺。也可能在不用保护薄膜的情况下来完成这种封装过程。封装材料36起着在微电子封装核心20之内固定微电子晶片30的作用，并对随后导电轨道薄层的建立，为与表面区在一起的最后结构提供机械的坚固性。
在封装之后，除去保护薄膜28，如图4所示，以暴露带有在微电子封装核心20和微电子晶片30之间的空间起填料作用的封装材料36的微电子晶片有源表面32。结果是基本上与微电子晶片有源表面32和微电子封装核心的第一，即有源表面24共平面的至少一个表面38。图5示出在微电子封装核心20之内用封装材料36所封装的微电子晶片30。微电子晶片30包括在微电子晶片有源表面32上设置的多个电接触点40。电接触点40被连接到微电子晶片30中的电路系统(未出示)，但是，为了简单和清晰，应理解在图5中仅示出4个电接触点40。
如图6所示，在微电子晶片有源表面32上配置着诸如环氧树脂，聚酰亚胺，二苯环丁二烯，以及诸如此类化合物的电介质薄层42。电介质薄层42和封装材料表面38，而且还覆盖诸电接触点40。电介质薄层42的形成可通过包括，但并不限于，层压，旋转涂膜，滚动涂膜，和喷雾沉积的任何已知的工艺过程。
如图7所示，于是用包括，但并不限于，激光打孔，光刻等在本领域中任何已知的方法，穿过电介质薄层42来形成多个通路44，如果电介质薄层42是光敏的，则可用在光刻工艺过程中制作光酸抗蚀掩膜的相同方法来形成多个通路44，如在本领域中已知的。
在电介质薄层42上形成多个导电轨道46，如图8所示，为了与在微电子晶片30上的接触点40电接触，形成多个导电轨道46的每个中的一部分，使其延伸到多个通路44中的至少一个中(参见图7)。多个导电轨道46可由诸如铜，铝，其合金，如导电的聚合物树脂的任何合适的导电材料形成。
多个导电轨道46可用包括，但并不限于，半添加电镀和光刻技术的任何已知技术来形成。一种示范性的半添加电镀技术可牵涉到在电介质薄层42上沉积诸如溅射沉积或化学镀沉积金属的籽晶薄层。于是可沉积抗蚀层，然后在籽晶层上做图形。然后在做好图形的抗蚀层上被开口区暴露的籽晶层上用电解电镀涂敷一层诸如铜的金属层。于是，可把做好图形的抗蚀层剥离，而在其上没有被电镀金属薄层的籽晶层中的一部分腐蚀掉以完成导电层46的形成。尽管在前面陈述了一种用于形成导电轨道的已知技术，但是形成多个导电轨道46的其它方法，对在本领域中的技术人员是明白的。
可能要求锡需要在这种位置上沉积轨道那样，来获得合适的互连或满足电的或其它性能的规格，可重复用于沉积电介质材料，形成通路，和形成轨道的工艺步骤的序列。一旦形成导电轨道46，可把它们用于带有焊料凸缘，焊料球，细杆，及诸如此类焊料的导电互连的形成用来与诸如光学基底的外部部件的传播。例如，在电介质层42上可沉积焊料后掩膜材料48，于是可在焊料掩膜材料48中形成带有焊料掩膜开口51的导电轨道46，如图9所示，以及多个通路50，以暴露每个导电轨道46中的至少一个区段。可放置多个诸如球栅格阵列(BGA)的导电凸缘52与导电轨道46的暴露区段相接触，并用回流工艺固定在那里，如图10所示。
图11示出与至少一个导电轨道46相接触的诸如纵向空腔表面发射激光器(VCSEL)或光探测器的电光元件54，用于把来自微电子晶片30的电信号转换成光信号，或者反过来转换亦行。如图11所示，电光元件54通过用回流工艺把电光元件54固定到微电子封装58的焊料球56与一对导电轨道46相接触。正如将会理解的，微电子封装58是由微电子封装核心20，微电子晶片30，封装材料36，以及由电介质层42，导电轨道30，封装材料36，以及由电介质层42，导电轨道46和焊料掩膜材料48限定的组合层即诸薄层60，所限定的。
如图12所示，用BGA52，固定到微电子封装58的电光PCB62具有第一表面66和第一表面66对面的第二表面68。图12示出耦合器70和波导72被安装于第一和第二表面中的诸如第一表面66的一个表面之中或之上，或在中间的位置处，且把它放在相对于微电子封装58的有源一侧与微电子晶片有源表面32隔开，但是面向着它。图12还示出微电子封装58的有源侧至少部分地分别由微电子晶片30的有源表面32和对应的微电子封装核心20的有源表面24和38，以及封装材料36所限定，所有这些表面是共面的。图12还进一步示出在微电子封装58有源侧上的组合层即诸薄层60被分别安装在微电子片段有源表面42和微电子封装核心20相应的有源表面24和38，以及封装材料36中的至少一个，且较佳的是所有的之上。示于图12中BGA接合处的位置由焊料掩膜开口51所决定。用于把微电子封装58固定到电光印刷线路板64的BGA球和固定电光元件54的BGA球的焊料掩膜开口，较佳的应是如果做图形工艺是根据光刻的，则由作为相同的做图形的工艺或用相同的掩膜一次曝光来制作。
可通过焊料自对准来获得在电光元件和耦合器之间的对准，例如，可由BGA回流来获得这种自对准。用这方法成功的对准要求耦合器相对于光学基底的BGA焊料掩膜开口的精确位置。
还是参考图12，电光元件54可包括集成透镜76来聚焦并传输到或来自耦合器70和波导72光信号。一般来说，邻近耦合器70和波导72，如在78处那样，可把折射率匹配的材料安装在集成透镜76的表面上，图12还示出，例如在面向微电子封装58的一侧，光学基底62可包括在其上具有耦合器70和波导72的印刷电路板。
有了本发明实施例这样详细的描述，要知道，由所附权利要求书中所规定的本发明，并不限于在上面描述中陈述的特殊细节，因为在不违背其精神实质或范围的情况下，有其许多明显的变化是可能的。

Claims (23)

1.一种电光组件，包括：
微电子封装；
光学基底；
电光元件，把来自所述微电子封装和所述光学基底中的一个的信号转换并传输到所述微电子封装和所述光学基底中的另一个；以及
接合剂，把所述微电子封装固定到所述光学基底。
2.根据权利要求1所述的电光组件，其特征在于，其中所述微电子封装具有微电子晶片，而所述光学基底具有耦合器和波导。
3.根据权利要求2所述的电光组件，其特征在于，其中所述微电子封装包括具有通道的核心，通过封装材料把所述微电子晶片粘附到这通道中。
4.根据权利要求3所述的电光组件，其特征在于，其中所述微电子封装具有由所述微电子晶片的有源表面和所述核心的对应表面所限定的有源侧面。
5.根据权利要求3所述的电光组件，其特征在于，其中所述在微电子封装的所述核心中的所述通道中的所述封装材料与所述微电子晶片的所述有源表面是共面的。
6.根据权利要求4所述的电光组件，在所述微电子封装的所述有源侧上还包括组合层以支承与所述微电子晶片电接触的导电轨道。
7.根据权利要求6所述的电光组件，其特征在于，其中所述组合层包括电介质层，通过这电介质层，所述轨道为在所述微电子封装的所述有源侧上的接触而延伸。
8.根据权利要求6所述的电光组件，包括焊料球以把所述电光元件固定到所述导电轨道和到在所述组合层上焊料掩膜的做好图形的开口。
9.根据权利要求8所述的电光组件，其特征在于，其中所述接合剂包括固定到光学基底的焊料球和到在所述微电子封装的所述组合层上的已做好图形的开口。
10.根据权利要求9所述的电光组件，其特征在于，其中用于所述电光元件和所述结合剂的所述已做好图形的开口是用在用于所述焊料掩膜的单一薄层中的单一的构图工艺来做成图形的。
11.根据权利要求10所述的电光组件，其特征在于，其中所述构图工艺包括用单一的光刻掩膜对用于所述电光元件和接合剂的所述图形开口做图形。
12.根据权利要求2所述的电光组件，其特征在于，其中所述电光元件转换来自所述微电子晶片和所述耦合器与波导中的一个的信号，并把所述信号传输到所述微电子晶片和所述耦合器与波导中的另一个。
13.根据权利要求2所述的电光组件，其特征在于，其中所述电光元件把来自所述微电子晶片的电信号转移到光信号，并把所述光信号传输到所述耦合器与波导中。
14.根据权利要求2所述的电光组件，其特征在于，其中所述电光元件把来自所述耦合器与波导的光信号转换成电信号，并把所述电信号传输到所述微电子晶片。
15.根据权利要求12所述的电光组件，一般于邻近所述耦合器和所述波导处，在所述电光组件的表面上包括折射率匹配的材料。
16.根据权利要求13所述的电光组件，其特征在于，其中所述电光元件包括集成透镜，以把所述光信号聚焦并传输到所述耦合器与所述波导。
17.根据权利要求1所述的电光组件，其特征在于，其中所述电光元件是在所述微电子封装和所述光学基底之间并包括一VCSEL。
18.根据权利要求1所述的电光组件，其特征在于，其中所述电光元件在所述微电子封装和所述光学基底之间并包括光探测器。
19.根据权利要求1所述的电光组件，其特征在于，其中所述光学基底包括在其上具有耦合器和波导的印刷电路板。
20.一种制造电光封装的方法，包括：
把电光元件接合到具有微电子晶片的微电子封装的有源侧；
设置具有耦合器和波导的光学基底面向所述电光元件；以及
把所述微电子封装接合到所述光学基底，使得所述电光元件与所述耦合器对准。
21.根据权利要求20所述方法，其特征在于，其中用焊料球把所述电光元件接合到在所述微电子封装的所述有源侧上的组合层上焊料掩膜的已做好图形的开口。
22.根据权利要求20所述方法，其特征在于，其中用焊料球把所述光学基底接合到在所述微电子封装的所述有源侧上的组合层上焊料掩膜的已做好图形的开口。
23.根据权利要求20所述的方法，其特征在于，在电光元件和耦合器之间的对准采用焊料自对准。
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CN109683261A (zh) * 2019-01-22 2019-04-26 中科天芯科技（北京）有限公司 一种探测器电路板与光波导芯片的集成对准封装结构
CN111934192A (zh) * 2020-09-29 2020-11-13 常州纵慧芯光半导体科技有限公司 一种光发射模组及其封装方法

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AU2003274975A8 (en) 2004-04-19
WO2004029680A3 (en) 2004-08-05
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US20040057649A1 (en) 2004-03-25
TW200408842A (en) 2004-06-01
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