CN100468108C - 电光组件 - Google Patents

电光组件 Download PDF

Info

Publication number
CN100468108C
CN100468108C CNB038225255A CN03822525A CN100468108C CN 100468108 C CN100468108 C CN 100468108C CN B038225255 A CNB038225255 A CN B038225255A CN 03822525 A CN03822525 A CN 03822525A CN 100468108 C CN100468108 C CN 100468108C
Authority
CN
China
Prior art keywords
electro
package according
electrooptic cell
optical
microelectronics packaging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB038225255A
Other languages
English (en)
Other versions
CN1685261A (zh
Inventor
S·托勒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN1685261A publication Critical patent/CN1685261A/zh
Application granted granted Critical
Publication of CN100468108C publication Critical patent/CN100468108C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4204—Packages, e.g. shape, construction, internal or external details the coupling comprising intermediate optical elements, e.g. lenses, holograms
    • G02B6/4214—Packages, e.g. shape, construction, internal or external details the coupling comprising intermediate optical elements, e.g. lenses, holograms the intermediate optical element having redirecting reflective means, e.g. mirrors, prisms for deflecting the radiation from horizontal to down- or upward direction toward a device
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
    • G02B6/4228—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements
    • G02B6/4232—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements using the surface tension of fluid solder to align the elements, e.g. solder bump techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73209—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Optical Integrated Circuits (AREA)
  • Optical Couplings Of Light Guides (AREA)
  • Semiconductor Lasers (AREA)

Abstract

一种包括微电子封装(20)和光学基底(62)的电子组件，其中该光学基底包括耦合器(70)和波导(72)。电光元件(54)被配置成把来自微电子封装(20)的电信号转换到用于传输到耦合器(70)和波导(72)的光信号，和/或接收光信号并把它转换到用于传输到微电子封装(20)的电信号。

Description

电光组件
技术领域
本发明涉及以紧凑但功能性方式封装带有一个或多个光学部件的微电子部件的装置及方法。本发明特别涉及在光电封装和具有波导的基地之间对准和固定电光元件的封装技术。
背景技术
较高的频带宽度，改良的性能，较低的成本，以及提高的小型化是计算机工业为要加强在计算机内芯片之间通信的现有目的。我们已经知道，集成的电路部件已经经历进一步的小型化，当这个目的达到后，需要微电子管芯变得更小。人微电子封装的类似小型化为人们所期望，因为它可减少成本和部件的外形尺寸(成形系数form factor)。
对于获得诸如10Gb/s数量级或更高的较高频宽来说，光学芯片间的通信面临着许多挑战。属于这些挑战之列的是在微处理器和光发射器/探测器芯片之间的高频宽，低等待时间的通信，在光发射器/探测器芯片和波导之间的对准与耦合，以及维持可接受的成本。迄今为止，应付所有这些挑战的困难之处在于芯片间的通信一般是用电子学方式获得。
应付面临光学芯片间的通信挑战将提供显著的好处，包括不仅减少来自诸如电磁干涉(EMI)和交叉干扰源的噪声，而且还包括光学芯片间通信提供的较高的频宽。但是，电光组件提供对可能设置在印刷电路板上波导结构的良好对准，在微处理器和光发射器/探测器芯片之间低的电寄生，以及相当低的制造成本是必须的。
所以，发展用于把带有与集成到印刷电路板(光电PCB)上的耦合器和波导对准的电光元件的微电子封装固定到诸如印刷电路板的基底上来提供合适的电光组件将是有利的。
发明内容
根据本发明的一种电光组件，包括：具有有源侧的微电子封装，所述微电子封装包括微电子管芯和具有通道的核心，通过封装材料把所述微电子管芯粘附到所述通道中；位于所述有源侧上的组合层，所述组合层包括导电轨道；耦合到所述微电子封装的有源侧的光学基底；耦合到所述组合层的电光元件，把来自所述微电子封装和所述光学基底中的一个的信号转换并传输到所述微电子封装和所述光学基底中的另一个；以及接合剂，把所述光学基底接合所述到组合层。
根据本发明的一种制造电光封装的方法，包括：把电光元件(54)接合到具有微电子管芯(30)的微电子封装(58)的有源侧上的组合层(60)上，其中所述组合层的至少一部分在所述微电子管芯的有源表面(24)上；设置具有耦合器(70)和波导(72)的光学基底(62)以面向所述电光元件；以及把所述微电子封装上的所述组合层接合到所述光学基底，使得所述电光元件和所述光学基底被接合到组合层的同一侧，从而使得所述电光元件与所述耦合器对准。
附图说明
尽管说明书以特别指出并明白地提出哪些内容为本发明的权利要求书作为结论。但是，当与附图结合在一起阅读时，从本发明的下面描述中可更为容易地肯定本发明的优点，其中：
图1是根据本发明邻接到保护膜的微电子封装核心的侧横截面图；
图2是配置在图1中微电子封装核心的开口之内的微电子管芯的侧横截面图；
图3是在已封装好微电子管芯之后的图2中组件的侧横截面图；
图4是已除去保护膜之后的图3中的组件的侧横截面图；
图5是说明在微子管芯上电触点的图4中组件的侧横截面图；
图6是说明覆盖电触点的电介质层的图5中组件的侧横截面图；
图7是在多个经过电介质层的通孔形成之后的图6中组件的侧横截面图；
图8是说明多个导电轨道的形成的图7中组件的侧横截面图；
图9是说明焊料掩膜和通孔的图8中组件的侧横截面图；
图10是说明多个焊料球的形成的图9中组件的侧横截面图；
图1是说明电连接到微电子管芯的电光元件的图10中组件的侧横截面图；以及
图12是固定到具有耦合器和波导的电光印刷电路板上的图1中组件的侧横截面图。
具体实施方式
虽然图1-12图示说明了本发明的各种视图，但这些图并不意味着用精确的细节来描绘出微电子和光学的组件。相反，这些图以一种更为清楚的方法来说明微电子和光学的组件来传达本发明的概念。另外，应注意到在整个各种视图中，在各图之间共用的元件保留相同的数字指示。
本发明包括一种封装技术，这个技术以把电光元件与在电光PCB上的耦合器和波导对准的方式把微电子封装固定到电光PCB上。在微电子封装和电光PCB之间配置这电光元件，从而把来自在微电子封装中微电子管芯的电信号转换成被传输到耦合器和波导的光信号。或者，这电光元件可把来自在电光PCB上的耦合器和波导的光信号转换成被传输到微电子封装的电信号。
图1示出微电子封装核心20，它包括用于制作具有在其中形成开口(opening)22的微电子封装的基本上是平面的材料。开口22从第一、有源表面24到对面的、第二表面26，完整地延伸穿过微电子封装核心20。正如将会理解的，开口22可以是具有受到唯一限制的任何形状和尺寸，这个形状和尺寸就是要被合适的做成能容纳在其中的、相应的微电子管芯，如下面讨论。
图1示出邻接在保护膜28上的该微电子封装核心第二表面26。具有有源表面32和后背表面34的微电子管芯30被放置在微电子封装核心20的开口22中，如图2所示。这样来放置微电子管芯30，使得它的有源表面32邻接于可能在其上具有诸如硅有机树脂粘合剂的保护膜28上。保护膜28附接到微电子封装核心20的第一，即有源，表面24和微电子管芯30的有源表面32，如图4所示。或者，保护膜28可以是依赖于封装工艺的非粘合薄膜。
具体地说，在将微电子管芯30和微电子封装核心20放置在能供封装工艺过程之用的铸模或其它的设备部件中之前，涂敷粘合型保护膜28。保护膜28还可以是诸如EPFE(乙烯-五氟乙烯)或聚四氟乙烯(
Figure C03822525D00071
)的非粘合的膜，它被可供封装工艺过程所用的铸模或其它设备的部件的内表面固定在微电子管芯有源表面32和微电子封装核心的第一(即有源)表面24上。在这两种情况中，在封装过程后，保护膜28将从微电子管芯30的有源表面32和微电子封装核心20的第一(即有源)表面24被除去。
然后，采用封装材料36填入在微电子封装核心20中未被微电子管芯30占有的开口22中的部分来封装微电子管芯30，如图5所示。微电子管芯30的封装可通过包括但并不限于转移和加压模铸，和撒布(dispense)的任何已知的工艺来实现。也可能在不用保护膜的情况下来完成这种封装过程。封装材料36起着在微电子封装核心20之内固定微电子管芯30的作用，并对随后导电轨道层的建立的表面区以及最后结构提供机械的坚固性。
在封装之后，除去保护膜28，如图4所示，以暴露微电子管芯有源表面32，而封装材料36在微电子封装核心20和微电子管芯30之间的空间起填料作用。结果是基本上与微电子管芯有源表面32和微电子封装核心的第一，即有源表面24共平面的至少一个表面38。图5示出在微电子封装核心20之内用封装材料36所封装的微电子管芯30。微电子管芯30包括在微电子管芯有源表面32上设置的多个电触点40。电触点40被连接到微电子管芯30中的电路系统(未出示)，但是，为了简单和清晰，应理解在图5中仅示出4个电触点40。
如图6所示，在微电子管芯有源表面32上配置着诸如环氧树脂，聚酰亚胺，二苯并环丁烯，以及诸如此类化合物的电介质层42。电介质层42覆盖诸电触点40以及微电子封装核心第一或有源表面24和封装材料表面38。电介质层42的形成可通过包括，但并不限于，层压，旋转涂膜，滚动涂膜，和喷雾沉积的任何已知的工艺过程。
如图7所示，然后用包括但并不限于激光打孔，光刻等在本领域中任何已知的方法，穿过电介质层42来形成多个通孔44，如果电介质层42是光敏的，则可用在光刻工艺过程中制作光刻胶掩膜的相同方法来形成多个通孔44，如在本领域中已知的。
在电介质层42上形成多个导电轨道46，如图8所示，为了与在微电子管芯30上的触点40电接触，形成多个导电轨道46的每个中的一部分，使其延伸到多个通孔44中的至少一个中(参见图7)。多个导电轨道46可由诸如铜，铝，其合金，如导电的聚合物树脂的任何合适的导电材料形成。
多个导电轨道46可用包括但并不限于半添加电镀和光刻技术的任何已知技术来形成。一种示范性的半添加电镀技术可牵涉到在电介质层42上沉积诸如溅射沉积或无电镀沉积金属的籽晶层。然后可沉积抗蚀层，然后在籽晶层上做图形。然后在做好图形的抗蚀层上被开口区暴露的籽晶层上用电解电镀涂敷一层诸如铜的金属层。于是，可把做好图形的抗蚀层剥离，而在其上没有被电镀金属层的籽晶层中的一部分腐蚀掉以完成导电轨道46的形成。尽管在前面陈述了一种用于形成导电轨道的已知技术，但是形成多个导电轨道46的其它方法，对在本领域中的技术人员是明白的。
用于沉积电介质材料，形成通孔，和形成轨道的工艺步骤的序列可以根据需要而被重复，从而将轨道按照要求沉积在特定位置上以获得合适的互连或满足电气的或其它的性能规格。一旦形成导电轨道46，可把它们用于与焊料凸缘，焊料球，针脚，及诸如此类焊料的导电互连的形成，从而用来与诸如光学基底的外部部件的通信。例如，在电介质层42上可沉积焊料掩膜材料48，于是可在焊料掩膜材料48中形成带有焊料掩膜开口51的导电轨道46，如图9所示，以及多个通孔50，以暴露每个导电轨道46中的至少一个区段。可放置多个诸如球栅格阵列(BGA)的导电凸缘52与导电轨道46的暴露区段相接触，并用回流工艺固定在那里，如图10所示。
图1示出与至少一个导电轨道46相接触的诸如纵向空腔表面发射激光器(VCSEL)或光探测器的电光元件54，用于把来自微电子管芯30的电信号转换成光信号，或者反过来转换亦行。如图1所示，电光元件54通过焊料球56和一对导电轨道46相接触，所述焊料球通过回流工艺把电光元件54固定到微电子封装58。正如将会理解的，微电子封装58是由微电子封装核心20，微电子管芯30，封装材料36，以及由电介质层42，导电轨道46和焊料掩膜材料48限定的一个或多个组合层60所限定的。
如图12所示，用BGA52，固定到微电子封装58的电光PCB62具有第一表面66和第一表面66对面的第二表面68。图12示出耦合器70和波导72被安装于第一和第二表面中的诸如第一表面66的一个表面之中或之上，或在中间的位置处，且把它放在相对于微电子封装58的有源一侧与微电子管芯有源表面32隔开，但是面向着它。图12还示出微电子封装58的有源侧至少部分地分别由微电子管芯30的有源表面32和对应的微电子封装核心20的有源表面24和38，以及封装材料36所限定，所有这些表面是共面的。图12还进一步示出在微电子封装58有源侧上的组合层即诸层60被分别安装在微电子管芯有源表面42和微电子封装核心20相应的有源表面24和38，以及封装材料36中的至少一个，且较佳的是所有的之上。示于图12中BGA接合处的位置由焊料掩膜开口51的位置所决定。如果做图形工艺是基于光刻的，那么用于把微电子封装58固定到电光印刷线路板64的BGA球和固定电光元件54的BGA球的焊料掩膜开口，较佳的应是由作为相同的做图形的工艺或用相同的掩膜一次曝光来制作。
可通过焊料自对准来获得在电光元件和耦合器之间的对准，例如，可由BGA回流来获得这种自对准。用这方法成功的对准要求耦合器相对于光学基底的BGA焊料掩膜开口的精确位置。
还是参考图12，电光元件54可包括集成透镜76来聚焦并传输到或来自耦合器70和波导72光信号。一般来说，邻近耦合器70和波导72，如在78处那样，可把折射率匹配的材料安装在集成透镜76的表面上，图12还示出，例如在面向微电子封装58的一侧，光学基底62可包括在其上具有耦合器70和波导72的印刷电路板。
有了本发明实施例这样详细的描述，要知道，由所附权利要求书中所规定的本发明，并不限于在上面描述中陈述的特殊细节，因为在不违背其精神实质或范围的情况下，有其许多明显的变化是可能的。

Claims (23)

1.一种电光组件，包括：
具有有源侧的微电子封装，所述微电子封装包括微电子管芯和具有通道的核心，通过封装材料把所述微电子管芯粘附到所述通道中；
位于所述有源侧上的组合层，所述组合层包括导电轨道；
耦合到所述微电子封装的有源侧的光学基底；
耦合到所述组合层的电光元件，把来自所述微电子封装和所述光学基底中的一个的信号转换并传输到所述微电子封装和所述光学基底中的另一个；以及
接合剂，把所述光学基底接合到所述组合层。
2.根据权利要求1所述的电光组件，其特征在于，其中所述光学基底具有耦合器和波导，所述耦合器与电光元件对准以耦合在微电子封装和光学基底之间的信号。
3.根据权利要求1所述的电光组件，其特征在于，所述有源侧由所述微电子管芯的有源表面和所述核心的对应表面所限定。
4.根据权利要求3所述的电光组件，其特征在于，其中在微电子封装的核心中的通道中的所述封装材料与微电子管芯的所述有源表面是共面的。
5.根据权利要求3所述的电光组件，其特征在于，所述组合层还包括电介质层和焊料掩膜材料，其中所述电介质层支承与所述微电子管芯电接触的导电轨道。
6.根据权利要求5所述的电光组件，其特征在于，所述导电轨道为在所述微电子封装的所述有源侧上的接触而延伸穿过所述电介质层。
7.根据权利要求5所述的电光组件，包括焊料球以通过所述组合层上焊料掩模的做好图形的开口把所述电光元件固定到所述导电轨道。
8.根据权利要求7所述的电光组件，其特征在于，其中所述接合剂包括焊料球，所述焊料球固定到所述光学基底并固定到在所述微电子封装的所述组合层上的已做好图形的开口。
9.根据权利要求8所述的电光组件，其特征在于，其中用于所述电光元件和所述接合剂的所述已做好图形的开口是采用在用于所述焊料掩膜的单一薄层中的单次构图工艺来做成图形的。
10.根据权利要求9所述的电光组件，其特征在于，其中所述构图工艺包括用单一的光刻掩膜对用于所述电光元件和接合剂的所述图形开口做图形。
11.根据权利要求2所述的电光组件，其特征在于，其中所述电光元件转换来自所述微电子管芯与所述耦合器和波导中的一个的信号，并把转换后的信号传输到所述微电子管芯与所述耦合器和波导中的另一个。
12.根据权利要求2所述的电光组件，其特征在于，其中所述电光元件把来自所述微电子管芯的电信号转移到光信号，并把所述光信号传输到所述耦合器与波导中。
13.根据权利要求2所述的电光组件，其特征在于，其中所述电光元件把来自所述耦合器与波导的光信号转换成电信号，并把所述电信号传输到所述微电子管芯。
14.根据权利要求2所述的电光组件，在邻近所述耦合器处，在所述电光组件的表面上包括折射率匹配的材料。
15.根据权利要求2所述的电光组件，其特征在于，其中所述电光元件包括集成透镜，以把所述光信号聚焦并传输到所述耦合器。
16.根据权利要求1所述的电光组件，其特征在于，其中所述电光元件在所述微电子封装和所述光学基底之间并包括一VCSEL。
17.根据权利要求1所述的电光组件，其特征在于，其中所述电光元件在所述微电子封装和所述光学基底之间并包括光探测器。
18.根据权利要求1所述的电光组件，其特征在于，其中所述光学基底包括在其上具有耦合器和波导的印刷电路板。
19.根据权利要求5所述的电光组件，其特征在于，所述电光元件和所述光学基底都直接耦合到所述组合层上。
20.一种制造电光封装的方法，包括：
把电光元件(54)接合到具有微电子管芯(30)的微电子封装(58)的有源侧上的组合层(60)上，其中所述组合层的至少一部分在所述微电子管芯的有源表面(24)上；
设置具有耦合器(70)和波导(72)的光学基底(62)以面向所述电光元件；以及
把所述微电子封装上的所述组合层接合到所述光学基底，使得所述电光元件和所述光学基底被接合到组合层的同一侧，从而使得所述电光元件与所述耦合器对准。
21.根据权利要求20所述方法，其特征在于，其中用焊料球把所述电光元件接合到在所述微电子封装的所述有源侧上的组合层上焊料掩膜的已做好图形的开口。
22.根据权利要求20所述方法，其特征在于，其中用焊料球把所述光学基底接合到在所述微电子封装的所述有源侧上的组合层上焊料掩膜的已做好图形的开口。
23.根据权利要求20所述的方法，其特征在于，在电光元件和耦合器之间的对准采用焊料自对准。
CNB038225255A 2002-09-24 2003-09-12 电光组件 Expired - Fee Related CN100468108C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/253,834 2002-09-24
US10/253,834 US7039263B2 (en) 2002-09-24 2002-09-24 Electrooptic assembly

Publications (2)

Publication Number Publication Date
CN1685261A CN1685261A (zh) 2005-10-19
CN100468108C true CN100468108C (zh) 2009-03-11

Family

ID=31993231

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB038225255A Expired - Fee Related CN100468108C (zh) 2002-09-24 2003-09-12 电光组件

Country Status (8)

Country Link
US (1) US7039263B2 (zh)
EP (1) EP1543367A2 (zh)
JP (1) JP4163689B2 (zh)
CN (1) CN100468108C (zh)
AU (1) AU2003274975A1 (zh)
MY (1) MY134515A (zh)
TW (1) TWI228608B (zh)
WO (1) WO2004029680A2 (zh)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI254467B (en) * 2005-03-01 2006-05-01 Advanced Semiconductor Eng Semiconductor package having an optical device and the method of making the same
JP6289364B2 (ja) 2011-06-30 2018-03-07 ムラタ エレクトロニクス オサケユキチュア システムインパッケージデバイスを製造する方法、および、システムインパッケージデバイス
US8810024B2 (en) * 2012-03-23 2014-08-19 Stats Chippac Ltd. Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units
KR102009979B1 (ko) 2012-06-07 2019-08-12 삼성전자주식회사 반도체 패키지 및 이를 포함하는 반도체 장치
EP2969058B1 (en) 2013-03-14 2020-05-13 Icon Health & Fitness, Inc. Strength training apparatus with flywheel and related methods
US9403047B2 (en) 2013-12-26 2016-08-02 Icon Health & Fitness, Inc. Magnetic resistance mechanism in a cable machine
US10433612B2 (en) 2014-03-10 2019-10-08 Icon Health & Fitness, Inc. Pressure sensor to quantify work
WO2015191445A1 (en) 2014-06-09 2015-12-17 Icon Health & Fitness, Inc. Cable system incorporated into a treadmill
US10258828B2 (en) 2015-01-16 2019-04-16 Icon Health & Fitness, Inc. Controls for an exercise device
US10953305B2 (en) 2015-08-26 2021-03-23 Icon Health & Fitness, Inc. Strength exercise mechanisms
CN108140688B (zh) * 2015-09-28 2021-01-29 曜晟光电有限公司 半导体结构
US10025033B2 (en) 2016-03-01 2018-07-17 Advanced Semiconductor Engineering, Inc. Optical fiber structure, optical communication apparatus and manufacturing process for manufacturing the same
US10293211B2 (en) 2016-03-18 2019-05-21 Icon Health & Fitness, Inc. Coordinated weight selection
US10493349B2 (en) 2016-03-18 2019-12-03 Icon Health & Fitness, Inc. Display on exercise device
US10561894B2 (en) 2016-03-18 2020-02-18 Icon Health & Fitness, Inc. Treadmill with removable supports
US10625137B2 (en) 2016-03-18 2020-04-21 Icon Health & Fitness, Inc. Coordinated displays in an exercise device
US10272317B2 (en) 2016-03-18 2019-04-30 Icon Health & Fitness, Inc. Lighted pace feature in a treadmill
US10252109B2 (en) 2016-05-13 2019-04-09 Icon Health & Fitness, Inc. Weight platform treadmill
US10441844B2 (en) 2016-07-01 2019-10-15 Icon Health & Fitness, Inc. Cooling systems and methods for exercise equipment
US10241264B2 (en) 2016-07-01 2019-03-26 Advanced Semiconductor Engineering, Inc. Semiconductor device packages
US10471299B2 (en) 2016-07-01 2019-11-12 Icon Health & Fitness, Inc. Systems and methods for cooling internal exercise equipment components
US10500473B2 (en) 2016-10-10 2019-12-10 Icon Health & Fitness, Inc. Console positioning
US10376736B2 (en) 2016-10-12 2019-08-13 Icon Health & Fitness, Inc. Cooling an exercise device during a dive motor runway condition
TWI646997B (zh) 2016-11-01 2019-01-11 美商愛康運動與健康公司 用於控制台定位的距離感測器
US10661114B2 (en) 2016-11-01 2020-05-26 Icon Health & Fitness, Inc. Body weight lift mechanism on treadmill
TWI680782B (zh) 2016-12-05 2020-01-01 美商愛康運動與健康公司 於操作期間抵銷跑步機的平台之重量
TWI756672B (zh) 2017-08-16 2022-03-01 美商愛康有限公司 用於抗馬達中之軸向衝擊載荷的系統
US10729965B2 (en) 2017-12-22 2020-08-04 Icon Health & Fitness, Inc. Audible belt guide in a treadmill
CN109683261B (zh) * 2019-01-22 2020-12-01 国科光芯(海宁)科技股份有限公司 一种探测器电路板与光波导芯片的集成对准封装结构
US11372160B2 (en) * 2020-01-31 2022-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Package, optical device, and manufacturing method of package
CN111934192A (zh) * 2020-09-29 2020-11-13 常州纵慧芯光半导体科技有限公司 一种光发射模组及其封装方法

Family Cites Families (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5168537A (en) 1991-06-28 1992-12-01 Digital Equipment Corporation Method and apparatus for coupling light between an optoelectronic device and a waveguide
US5420954A (en) 1993-05-24 1995-05-30 Photonics Research Incorporated Parallel optical interconnect
JPH0926530A (ja) * 1995-07-11 1997-01-28 Nec Corp 光モジュール
KR100192760B1 (ko) * 1996-02-29 1999-06-15 황인길 메탈 캐리어 프레임을 이용한 bag반도체 패키지의 제조방법 및 그반도체 패키지
DE69715504T2 (de) * 1996-04-26 2003-06-05 Dow Corning Toray Silicone Co. Ltd., Ichihara Elektrisch leitfähige Silikonkautschukzusammensetzung und ihre Anwendung zur Herstellung von Halbleiteranordnungen
US5627931A (en) 1996-05-28 1997-05-06 Motorola Optoelectronic transducer
KR100236432B1 (ko) * 1996-07-31 1999-12-15 미야즈 쥰이치로 광학 편광기, 이의 제조 방법 및 광학 편광기 제조용 블레이드
EP0950204B1 (en) * 1996-12-31 2002-01-23 Honeywell Inc. Flexible optic connector assembly
JPH10319278A (ja) * 1997-05-16 1998-12-04 Nec Corp 光結合回路
US6009632A (en) * 1997-12-12 2000-01-04 Mercury Diagnostics, Inc. Alignment system for optical analyte testing meter components
JP4203152B2 (ja) * 1998-09-11 2008-12-24 株式会社日立メディアエレクトロニクス 弾性表面波装置
JP3775069B2 (ja) * 1998-09-18 2006-05-17 住友電気工業株式会社 光受信モジュール
US6684007B2 (en) * 1998-10-09 2004-01-27 Fujitsu Limited Optical coupling structures and the fabrication processes
US6785447B2 (en) * 1998-10-09 2004-08-31 Fujitsu Limited Single and multilayer waveguides and fabrication process
US6048755A (en) * 1998-11-12 2000-04-11 Micron Technology, Inc. Method for fabricating BGA package using substrate with patterned solder mask open in die attach area
US6243508B1 (en) 1999-06-01 2001-06-05 Picolight Incorporated Electro-opto-mechanical assembly for coupling a light source or receiver to an optical waveguide
JP2001021775A (ja) * 1999-07-09 2001-01-26 Sumitomo Electric Ind Ltd 光学装置
DE19932430C2 (de) 1999-07-12 2002-03-14 Harting Elektrooptische Bauteile Gmbh & Co Kg Opto-elektronische Baugruppe sowie Bauteil für diese Baugruppe
JP3728147B2 (ja) * 1999-07-16 2005-12-21 キヤノン株式会社 光電気混載配線基板
US6271469B1 (en) 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
JP2001196643A (ja) * 2000-01-11 2001-07-19 Toppan Printing Co Ltd 光・電気素子搭載用チップキャリア及びその実装方法並びに光・電気配線基板及びその製造方法並びに実装基板
US7061084B2 (en) * 2000-02-29 2006-06-13 Advanced Semiconductor Engineering, Inc. Lead-bond type chip package and manufacturing method thereof
US6809413B1 (en) * 2000-05-16 2004-10-26 Sandia Corporation Microelectronic device package with an integral window mounted in a recessed lip
US6586822B1 (en) * 2000-09-08 2003-07-01 Intel Corporation Integrated core microelectronic package
US6569248B1 (en) * 2000-09-11 2003-05-27 Allen David Hertz Apparatus for selectively applying solder mask
US6702413B2 (en) * 2000-11-16 2004-03-09 Canon Kabushiki Kaisha Liquid discharge head, liquid discharge apparatus, and IC package structure
NL1016779C2 (nl) * 2000-12-02 2002-06-04 Cornelis Johannes Maria V Rijn Matrijs, werkwijze voor het vervaardigen van precisieproducten met behulp van een matrijs, alsmede precisieproducten, in het bijzonder microzeven en membraanfilters, vervaardigd met een dergelijke matrijs.
JP4831901B2 (ja) * 2000-12-06 2011-12-07 イビデン株式会社 多層プリント配線板
JP2002270860A (ja) * 2000-12-06 2002-09-20 Ibiden Co Ltd Ｉｃチップ実装用基板
US6785458B2 (en) * 2001-02-11 2004-08-31 Georgia Tech Research Corporation Guided-wave optical interconnections embedded within a microelectronic wafer-level batch package
US7101091B2 (en) * 2001-02-21 2006-09-05 Zarlink Semiconductor, Inc. Apparatus for coupling a fiber optic cable to an optoelectronic device, a system including the apparatus, and a method of forming the same
US6570259B2 (en) * 2001-03-22 2003-05-27 International Business Machines Corporation Apparatus to reduce thermal fatigue stress on flip chip solder connections
US6531767B2 (en) * 2001-04-09 2003-03-11 Analog Devices Inc. Critically aligned optical MEMS dies for large packaged substrate arrays and method of manufacture
US6754407B2 (en) * 2001-06-26 2004-06-22 Intel Corporation Flip-chip package integrating optical and electrical devices and coupling to a waveguide on a board
US7110640B2 (en) * 2001-07-19 2006-09-19 Evident Technologies Reconfigurable optical add/drop filter
US6498358B1 (en) * 2001-07-20 2002-12-24 Motorola, Inc. Structure and method for fabricating an electro-optic system having an electrochromic diffraction grating
US6743153B2 (en) * 2001-09-06 2004-06-01 Icon Ip, Inc. Method and apparatus for treadmill with frameless treadbase
US6845211B2 (en) * 2001-09-06 2005-01-18 Corona Optical Systems, Inc. Method of attenuating an optical signal
US6569712B2 (en) * 2001-10-19 2003-05-27 Via Technologies, Inc. Structure of a ball-grid array package substrate and processes for producing thereof
US20030113974A1 (en) * 2001-12-14 2003-06-19 Ning Xian J. Stacked metal-insulator-metal capacitor structures in between interconnection layers
SG115455A1 (en) * 2002-03-04 2005-10-28 Micron Technology Inc Methods for assembly and packaging of flip chip configured dice with interposer
US7418163B2 (en) * 2002-03-28 2008-08-26 Chakravorty Kishore K Optoelectrical package
US20040052468A1 (en) * 2002-04-02 2004-03-18 Pham Cuong Van Alignable electro-optical microelectronic package and method
US20030210865A1 (en) * 2002-05-08 2003-11-13 Kjetil Johannessen Method and apparatus for coupling of optically active devices to a planar lightwave circuit
JP2004031573A (ja) * 2002-06-25 2004-01-29 Oki Electric Ind Co Ltd 光送受信モジュール
US6673649B1 (en) * 2002-07-05 2004-01-06 Micron Technology, Inc. Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages
US7016569B2 (en) * 2002-07-31 2006-03-21 Georgia Tech Research Corporation Back-side-of-die, through-wafer guided-wave optical clock distribution networks, method of fabrication thereof, and uses thereof

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
Bumpless Build-up Layer Packaging. Steven，N.Towle，et，al.2001 ASME INTERNATIONAL MECHANICAL ENGINEERING CONGRESS AND EXPOSITION，第Vol.1卷. 2001
Bumpless Build-up Layer Packaging. Steven，N.Towle，et，al.2001 ASME INTERNATIONAL MECHANICAL ENGINEERING CONGRESS AND EXPOSITION，第Vol.1卷. 2001 *
OpticalReflectivityofMicromachined{111}-OrientedSiliconMirrorsforOpticalInput-output Couplers. Daniel J Sadler et al.JOURNAL OF MICROMECHANICS AND MICROENGINEERING,Vol.Vol.7 No.No.4. 1997
OpticalReflectivityofMicromachined{111}-OrientedSiliconMirrorsforOpticalInput-output Couplers. Daniel J Sadler et al.JOURNAL OF MICROMECHANICS AND MICROENGINEERING,Vol.Vol.7 No.No.4. 1997 *

Also Published As

Publication number Publication date
AU2003274975A1 (en) 2004-04-19
CN1685261A (zh) 2005-10-19
MY134515A (en) 2007-12-31
US7039263B2 (en) 2006-05-02
AU2003274975A8 (en) 2004-04-19
WO2004029680A2 (en) 2004-04-08
TWI228608B (en) 2005-03-01
EP1543367A2 (en) 2005-06-22
JP4163689B2 (ja) 2008-10-08
US20040057649A1 (en) 2004-03-25
TW200408842A (en) 2004-06-01
WO2004029680A3 (en) 2004-08-05
JP2005539274A (ja) 2005-12-22

Similar Documents

Publication Publication Date Title
CN100468108C (zh) 电光组件
CN1949506B (zh) 混合模块和其制造方法
CN100438089C (zh) 光半导体装置及光信号输入输出装置
US7167608B2 (en) Hybrid circuit substrate with optical and electrical interconnects, hybrid circuit module with optical interconnects and manufacturing methods thereof
US20060198570A1 (en) Hybrid module and production method for same, and hybrid circuit device
US20080107375A1 (en) Optoelectric composite substrate and method of manufacturing the same
US7519244B2 (en) Circuit board with optoelectronic component embedded therein
KR20040036614A (ko) 복합 칩 모듈 및 그 제조 방법, 및 복합 칩 유닛 및 그제조 방법
JP5248795B2 (ja) 光電気混載パッケージ及びその製造方法、光素子付き光電気混載パッケージ、光電気混載モジュール
KR20050065038A (ko) 비수직 비아가 구비된 인쇄회로기판 및 패키지
CN102405524A (zh) 集成电路微模块
US7302126B2 (en) Circuit board structure of integrated optoelectronic componenet
KR20120023383A (ko) 임베디드 패키지 및 그 형성방법
US7450793B2 (en) Semiconductor device integrated with opto-electric component and method for fabricating the same
WO2013064592A2 (en) Wafer scale technique for interconnecting vertically stacked dies
US6812560B2 (en) Press-fit chip package
WO2023144248A1 (en) Package with organic integrated circuit substrate embedded in inorganic carrier body and redistribution structure extending along both
CN112188731A (zh) 内埋式元件结构及其制造方法
JP2012137765A (ja) 光電気混載パッケージ及びその製造方法、光素子付き光電気混載パッケージ、光電気混載モジュール
EP3716739A9 (en) Component carrier with embedded tracks protruding up to different heights
EP4307023A1 (en) Package having component carrier and embedded optical and electric chips with horizontal signal path in between
EP4227991A2 (en) Component carrier with connected component having redistribution layer at main surface
EP4247132A2 (en) Component carrier with surface mounted components connected by high density connection region
US20230245990A1 (en) Component Carrier With Embedded IC Substrate Inlay, and Manufacturing Method
WO2024200033A1 (en) Component carrier with stack and optical layer build-up for optical chip

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090311

Termination date: 20100912