CN1667758A - 电介质瓷器组合物以及使用该组合物的叠层陶瓷部件 - Google Patents

电介质瓷器组合物以及使用该组合物的叠层陶瓷部件 Download PDF

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CN1667758A
CN1667758A CN200510009061.5A CN200510009061A CN1667758A CN 1667758 A CN1667758 A CN 1667758A CN 200510009061 A CN200510009061 A CN 200510009061A CN 1667758 A CN1667758 A CN 1667758A
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dielectric
glass
weight
porcelain composition
obtains
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梅本卓史
青柳伦太郎
野野上宽
胁坂健一郎
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Sanyo Electric Co Ltd
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Abstract

本发明提供一种电介质瓷器组合物，含有电介质材料和玻璃，其特征是：所述电介质材料是由组合式a·Li2O－b·(CaO1－X－SrOX)－c·R2O3－d·TiO2 (其中，x满足0≤x＜1，R是从包括La、Y的稀土类元素中选出的至少一种，且a、b、c以及d满足，0≤a≤20mol％、0≤b≤45mol％、0＜c≤20mol％、40≤d≤80mol％、以及a+b+c+d＝100mol％)表示的电介质材料，且所述玻璃是含有Bi2O3在30重量％以上的玻璃。

Description

电介质瓷器组合物以及使用该组合物的叠层陶瓷部件
技术领域
本发明涉及使用于叠层陶瓷部件等的电介质瓷器组合物以及使用该组合物的叠层陶瓷部件。
背景技术
近年来，伴随着电子部件的小型化·薄型化，对叠层陶瓷部件的需求急剧增多。作为叠层陶瓷部件的具有代表性的一例，可举出以下叠层陶瓷部件，即，使用能与Ag等导电材料一同进行烧制的低温烧制材料(LTCC)，在各层上形成感应器或者电容器的电路的叠层陶瓷部件。作为使用于该叠层陶瓷部件的低温烧制材料，一般选择将氧化铝等陶瓷填料和玻璃混合后的电介质瓷器组合物。但是，由于这种组合物的介电常数很低、为10以下，因此应用到LC滤波器上其介电常数不足够大。
为了应用于LC滤波器，不仅要求具有高介电常数、介电损耗少，而且还要求温度系数τf接近于0。作为满足这些特性的电介质瓷器组合物，在特开平5-211007号公报中，公开了具有Li2O-CaO-Sm2O3-TiO2的组成的电介质瓷器组合物。
另外，在特开2003-146742号公报中公开了在(Li0.5(Nd，Sm)0.5)TiO3-(Ca1-XNd2X/3)TiO3中，含有ZnO-B2O3-SiO2系玻璃粉或Li2O-B2O3-SiO2系玻璃粉中的任何一个玻璃粉3～15重量％的电介质瓷器组合物。
然而，在特开平5-211007号公报中公开的电介质瓷器组合物是在1300℃左右的高温下烧制形成，因此很难以该组成，应用于在900℃左右的低温下烧制形成叠层陶瓷部件。
另外，在特开2003-146742号公报中公开的电介质瓷器组合物中，为了提高在900℃左右的低温下的烧结性，不得不增加玻璃的添加量。而增加玻璃的添加量，会引起介电特性的劣化。
发明内容
本发明鉴于以上的事实，其目的在于解决上述技术问题，即提供一种即使在900℃左右的低温下烧制时也能提高烧结性、且能抑制介电特性的劣化的电介质瓷器组合物以及使用该组合物的叠层陶瓷部件。
本发明提供一种电介质瓷器组合物，含有电介质材料和玻璃，其特征是：电介质材料是由组合式a·Li2O-b·(CaO1-X-SrOX)-c·R2O3-d·TiO2(其中，x满足0≤x＜1，R是从包括La、Y的稀土类元素中选出的至少一种，且a、b、c以及d满足，0≤a≤20mol％、0≤b≤45mol％、0＜c≤20mol％、40≤d≤80mol％、以及a+b+c+d＝100mol％)表示的电介质材料，且玻璃是含有Bi2O3在30重量％以上的玻璃。
本发明中使用的Bi2O3系玻璃(含有Bi2O3为30重量％以上的玻璃)的软化点和熔点低，且在900℃左右的烧制工序中成为粘度低的液相。因此，根据本发明，能通过粘度低的液相进行致密化，促进电介质材料的烧结，因此能提高低温下的烧结性。
本发明的Bi2O3系玻璃中的Bi2O3含有量，如上所述是在30重量％以上，但更优选是在50重量％以上。如果Bi2O3含有量少，则可能无法充分获得本发明的效果，即提高烧结性从而提高介电常数。
本发明中使用的Bi2O3系玻璃，优选还含有B2O3。B2O3的含有量优选为5～50重量％，更优选为10～40重量％。
本发明中的电介质材料，只要能由上述组合式表示就可，不作特别限定，例如，可优选使用特开平5-211007号公报中记载的电介质材料。电介质材料一般是通过将原料混合并进行临时烧制而制成的。优选临时烧制的温度在700～1200℃的范围中，且临时烧制时间则优选为1～5小时。
通过使用在上述组合式中R为Nd(钕)的电介质材料，尤其能提高烧结性、提高介电常数。
本发明的电介质瓷器组合物，还可含有以SiO2和B2O3为主成分的硼硅酸盐系玻璃。通过含有硼硅酸盐系玻璃，便于实施抑制介电损耗等介电特性的控制。
本发明的电介质瓷器组合物中，Bi2O3系玻璃的含有量优选为1～10重量％。如果Bi2O3系玻璃的含有量不足1重量％，在900℃左右的烧制中，则可能无法提高电介质瓷器组合物的烧结性。另外，如果Bi2O3系玻璃的含有量超过10重量％，则电介质瓷器组合物的介电特性就有可能劣化。
另外，在使用硼硅酸盐系玻璃时，电介质瓷器组合物中的Bi2O3系玻璃和硼硅酸盐系玻璃的合计含有量优选为1～10重量％。此时，优选将Bi2O3系玻璃的含有量设定在1～5重量％范围内，且将硼硅酸盐系玻璃的含有量设定在1～5重量％范围内。
另外，本发明的电介质瓷器组合物，还可含有B2O3和CuO中的至少一方作为烧结辅助剂。电介质瓷器组合物中的B2O3的含有量优选为15重量％以下，且CuO的含有量优选为5重量％以下。如果相对于电介质瓷器组合物的B2O3的含有量超过15重量％、或者CuO的含有量超过5重量％，则有可能会出现电介质瓷器组合物的介电特性劣化的情况。
本发明的叠层陶瓷部件的特征是：通过对含有所述本发明的电介质瓷器组合物的浆料进行成形而获得的电介质层和导体层进行叠层而获得。
图1是表示本发明的叠层陶瓷部件的立体图；图2是分解立体图。如图1和图2所示，电介质层1上形成有导体层2。另外，通过电介质层1，还有形成有过孔3的电介质层。通过叠层多片这种电介质层，构成叠层陶瓷部件。
根据本发明，可提供一种在900℃左右的低温烧制的情况下也能提高烧结性，且能抑制介电特性的劣化的电介质瓷器组合物。
附图说明
图1是表示本发明的叠层陶瓷部件的一例的立体图。
图2是表示本发明的叠层陶瓷部件的一例的分解立体图。
具体实施方式
下面，基于实施例对本发明进行详细说明，但本发明并不限于以下实施例，只要不改变其主旨，可适当改变进行实施。
[实施例1]
按以下方式调制电介质材料(A)。
(A)Li2O(9mol％)-CaO(15mol％)-SrO(1mol％)-Sm2O3(12mol％)-TiO2(63mol％)
对Li2CO3、CaCO3、SrCO3、Sm2O3以及TiO2进行秤量、混合，以满足上述组合比例。向该混合物中添加异丙醇，并使用氧化锆制罐和由球体构成的球磨机，对其进行24小时湿式混合。在使用球磨机进行湿式混合后，通过在700℃下对混合进行2小时的临时烧制，获得电介质材料(A)。
接着，使用由以上工序获得的电介质材料(A)和Bi2O3系玻璃，调制了电介质瓷器组合物。作为Bi2O3系玻璃，采用了由以下(G1)～(G3)表示的组成。
(G1)Bi2O3(55重量％)-B2O3(35重量％)-ZnO(10重量％)，软化点：约520℃
(G2)Bi2O3(75重量％)-B2O3(15重量％)-ZnO(10重量％)，软化点：约470℃
(G3)Bi2O3(60重量％)-B2O3(25重量％)-ZnO(5重量％)-SiO2(10重量％)，软化点：约540℃
如表1所示，对电介质材料(A)、Bi2O3系玻璃(G1)～(G3)内的一种、以及根据需要添加的B2O3等烧结辅助剂进行混合，并再次使用球磨机对其进行20小时的粉碎处理。
接着，向粉碎得到的混合物中，添加聚乙烯醇等粘合剂造粒分级之后，施加2000kg/cm2的压力，成型为规定大小及形状。在500℃下对该成型物进行2小时的脱粘合剂处理后，以900℃进行了5小时的烧制。
对于所获得的各试料(实施例No.1～No.9)，通过电介质谐振器法(hakki-coleman method)，测定出介电常数以及Qf值。另外，用烧制前后的尺寸，求出收缩率。
[比较例1]
在比较例1中，除了使用由以下(G4)～(G8)表示的软化点不同的硼硅酸盐系玻璃，以替代Bi2O3系玻璃之外，与实施例1相同地调制出电介质瓷器组合物。
(G4)奥野制药社制“G3-3950”，软化点：610℃
(G5)日本电气硝子社制“GA-4”，软化点：630℃
(G6)日本电气硝子社制“GA-12”，软化点：560℃
(G7)日本电气硝子社制“GA-47，软化点：870℃
(G8)日本电气硝子社制“GA-50”，软化点：830℃
对所获得的各试料(比较例No.1～No.8)，通过与所述实施例1相同的方法，测定出收缩率、介电常数以及Qf值。
表1表示关于实施例1和比较例1的各试料的测定结果。
表1
如表1所示，使用Bi2O3系玻璃的实施例No.1～No.9，即使在Bi2O3系玻璃的添加量为很少量即1～5重量％的情况下，其收缩率也很大，并显示了高的烧结性。
关于烧结性提高的理由，认为是：与不含有Bi2O3的玻璃相比，Bi2O3系玻璃的软化点和熔点都更低，且在900℃附近的粘度也低，因此由Bi2O3系玻璃促进了烧制物的致密化。
另外，与在电介质瓷器组合物中不含有B2O3的试料(例如实施例No.1～No.3)相比，含有B2O3作为烧结辅助剂的试料(例如实施例No.6～No.8)不仅烧结性提高了，且介电常数也较高。由此可知，通过使用B2O3等烧结辅助剂，能提高烧结性，并获得较高的介电常数。
[实施例2]
作为玻璃成分，并用Bi2O3系玻璃和硼硅酸盐系玻璃。
作为电介质材，使用了实施例1中的电介质材料(A)，以表2所示的配合比例，将Bi2O3系玻璃(G2)和硼硅酸盐系玻璃(G6)并用，并与实施例1相同地调制出电介质瓷器组合物。
对所获得的试料(实施例No.10～No.13)，与所述实施例1相同地，测定出收缩率、介电常数以及Qf值。表2表示测定结果。
                                       表2
   No.   Bi2O3玻璃   硼硅酸盐系玻璃   收缩率(％)   介电常数   Qf(GHz)
种类   添加量(重量％) 种类   添加量(重量％)
实施例   10   G2   4   G6   2   15.0   72   994
  11   G2   1   G6   5   12.6   54   2619
  12   G2   2   G6   4   15.5   66   985
  13   G2   1   G6   3   9.3   52   3338
由表2所示的结果可看出，通过在Bi2O3系玻璃中、并用硼硅酸盐系玻璃作为玻璃成分，能够提高Qf，并降低介电损耗。
[实施例3]
在实施例3中，除使用以下不含有Li2O的电介质材料(B)替代电介质材料(A)之外，与实施例1相同地调制出电介质瓷器组合物。
(B)CaO(24mol％)-SrO(1mol％)-Sm2O3(12mol％)-TiO2(63mol％)
对所获得的试料(实施例No.14)，通过与实施例1相同的方法，测定出收缩率、介电常数以及Qf值。表3表示了测定结果。
表3
如表3所示，在使用不含有Li2O的电介质材料的实施例No.14的情况下，也与实施例No.1～No.13同样，获得较高的烧结性。
[实施例4]
对Li2CO3、CaCO3、SrCO3、Nd2O3以及TiO2进行秤量、混合，以满足如表4、表5以及表6所示的Li2O-CaO-SrO-Nd2O3-TiO2的组成(摩尔比)。对该混合物添加异丙醇，并使用氧化锆制罐和由球体构成球磨机，对其进行24小时湿式混合。在使用球磨机进行湿式混合后，在1200℃下对混合进行2小时的临时烧制，得到各电介质材料。
接着，向得到的各电介质材料中，添加Bi2O3系玻璃(G2)和硼硅酸盐系玻璃(G6)以满足各表中所示的比例、进行混合，并再次使用球磨机对其进行20小时的粉碎处理。
接着，向粉碎后获得的混合物中添加聚乙烯醇等粘合剂造粒分级之后，施加2000kg/cm2的压力，成型为规定大小及形状。在500℃下对该成型物进行2小时的脱粘合剂处理后，在900℃下进行5小时的烧制。
对于所获得的各试料(实施例No.15～No.26)，采用电介质谐振器法(hakki-coleman method)，测定出介电常数以及Qf值。另外，用烧制前后的尺寸，求出收缩率。表4～表6表示这些测定结果。
                                表4
         Bi2O3系玻璃(G2)1重量％+硼硅酸盐系玻璃(G6)1重量％
                            实施例
  No.     15     16     17     18     19     20
  Li2O     9     9     12     8     10     12
  CaO     15     16     15     15     15     15
  SrO     1     0     1     1     1     1
  Nd2O3     12     12     11     8     10     12
  TiO2     63     63     63     48     56     64
  收缩率(％)     11.0     10.2     11.2     10.4     10.1     8.9
  介电常数     86.5     80.0     88.9     97.1     92.0     81.1
  Qf(GHz)     2487     2690     2350     2356     2380     2279
                    表5
Bi2O3系玻璃(G2)1重量％+硼硅酸盐系玻璃(G6)3重量％
                实施例
  No.     21     22     23
  Li2O     9     12     8
  CaO     15     15     15
  SrO     1     1     1
  Nd2O3     12     11     8
  TiO2     63     63     48
  收缩率(％)     12.9     14.5     13.8
  介电常数     86.1     101.0     108.3
  Qf(GHz)     2319     2198     2392
                     表6
Bi2O3系玻璃(G2)1重量％+硼硅酸盐系玻璃(G6)5重量％
                实施例
  No.     24     25     26
  Li2O     9     12     8
  CaO     15     15     15
  SrO     1     1     1
  Nd2O3     12     11     8
  TiO2     63     63     48
  收缩率(％)     13.4     15.2     13.5
  介电常数     79.1     95.3     94.3
  Qf(GHz)     2361     2075     2485
如表4～表6所示，在稀土类元素选用Nd的任何一个试料中，都获得了优良的烧结性和介电特性。对于该理由推测如下，即：与Sm(钐)相比Nd的离子半径大，因此随着晶格常数的增大，介电常数也提高。另外，由于烧结性提高了从而有助于烧结温度的降低。另外，将烧结后的试料的结晶相通过X射线衍射评价得到结果显示，没有发现当稀土类元素为Sm时看到的由Sm-Ti构成的第二相的峰值(peak)。其结果就是，维持了较高的Qf值。
[实施例5]
本发明的叠层陶瓷部件可通过以下方法获得，即如上所述，叠层由：以本发明的电介质瓷器组合物构成的电介质层、和形成于该电介质层表面的导电体层，构成的电介质印刷电路基板(Green sheet)，并对其进行烧制。例如，向通过与所述实施例相同的方法获得的电介质材料中，添加Bi2O3系玻璃、以及根据需要选择的其他添加剂，并用球磨机将其混合，并向所获得的混合物中添加聚乙烯醇缩丁醛(PVB)系粘合剂，再用球磨机混合添加PVB后获得的混合物，制成浆料。接着，使用刮浆刀装置，将通过以上工序获得的浆料成形为薄片厚度50～100μm的薄片状。将获得的薄片切断成规定大小，并将Ag糊剂印刷成规定的图案，形成电介质印刷电路基板。将该电介质印刷电路基板按图1和图2所示的方式，叠层8～20层并进行压接后，在400℃下进行脱粘合剂处理，接着在900℃下保持2小时以进行烧制，最终制成叠层陶瓷部件。

Claims (9)

1.一种电介质瓷器组合物，含有电介质材料和玻璃，其特征是：
所述电介质材料，是由组合式a·Li2O-b·(CaO1-X-SrOX)-c·R2O3-d·TiO2表示的电介质材料，且所述玻璃是含有Bi2O3为30重量％以上的玻璃，其中，x满足0≤x＜1，R是从包括La、Y的稀土类元素中选出的至少一种，且a、b、c以及d满足0≤a≤20mol％、0≤b≤45mol％、0＜c≤20mol％、40≤d≤80mol％、以及a+b+c+d＝100mol％。
2.如权利要求1所述的电介质瓷器组合物，其特征是：
所述玻璃还含有B2O3。
3.如权利要求1所述的电介质瓷器组合物，其特征是：
含有1～10重量％的所述玻璃。
4.如权利要求1所述的电介质瓷器组合物，其特征是：
还含有以SiO2和B2O3为主成分的硼硅酸盐系玻璃。
5.如权利要求4所述的电介质瓷器组合物，其特征是：
所述玻璃和所述硼硅酸盐系玻璃合计含有1～10重量％。
6.如权利要求1所述的电介质瓷器组合物，其特征是：
还含有1 5重量％以下的B2O3以及5重量％以下CuO中的至少一方作为烧结辅助剂。
7.一种叠层陶瓷部件，其特征是：
通过对含有将如权利要求1所述的电介质瓷器组合物的浆料成形得到的电介质层、以及导体层进行叠层而获得。
8.如权利要求1所述的电介质瓷器组合物，其特征是：
所述组合式中的R是Nd。
9.一种叠层陶瓷部件，其特征是：
通过对含有将如权利要求8所述的电介质瓷器组合物的浆料成形得到的电介质层、以及导体层进行叠层而获得。
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