CN1572018A - 具有浮岛电压维持层的功率半导体器件的制造方法 - Google Patents

具有浮岛电压维持层的功率半导体器件的制造方法 Download PDF

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CN1572018A
CN1572018A CNA028196589A CN02819658A CN1572018A CN 1572018 A CN1572018 A CN 1572018A CN A028196589 A CNA028196589 A CN A028196589A CN 02819658 A CN02819658 A CN 02819658A CN 1572018 A CN1572018 A CN 1572018A
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CN1305122C (zh
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理查德·A·布朗夏尔
让·米歇尔·吉约
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Abstract

一种功率半导体器件及其制造方法，提供衬底(402)，并接着通过在衬底(402)上淀积外延层(401)和在外延层(401)中形成至少一个沟槽而在衬底(402)上形成电压维持区。沿着沟槽壁淀积阻挡材料并穿过阻挡材料把掺杂剂注入到邻近沟槽底部并在沟槽底部之下的部分外延层(401)中。掺杂剂扩散形成第一掺杂层，并至少从沟槽的底部去除阻挡材料。穿过第一掺杂层蚀刻沟槽，并基本上填充沟槽，从而完成电压维持区。在电压维持区上形成至少一个区以在它们之间限定结面。

Description

具有浮岛电压维持层的功率半导体器件的制造方法
技术领域
本发明一般涉及半导体功率器件，尤其涉及使用相反掺杂材料的浮岛形成电压维持层的半导体功率器件，例如MOSFET和其它功率器件。
背景技术
半导体功率器件，例如纵向DMOS、V槽DMOS和沟槽DMOSMOSFET、IGBT以及二极管和双极晶体管应用在例如自动电气系统、供电系统、电动机驱动应用和其它功率控制应用中。虽然在开态(on-state)由于高电流密度而具有低接通电阻或低电压降，在关态(off-state)中这种器件仍需要维持高压。
图1说明N沟道功率MOSFET的一般结构。在N+掺杂硅衬底102上形成的N-外延硅层101包含p体区105a和106a以及用于器件中两个MOSFET单元的N+源区107和108。P体区105和106还可以包括深p体区105b和106b。源体电极112横过外延层101的某些表面部分延伸以接触源区和体区。由在图1中延伸到上半导体表面的N型外延层101部分形成用于两个单元的N型漏。在N+掺杂衬底102的底部设置漏极。包括绝缘和导电层(例如氧化物和多晶硅层)的绝缘栅极118位于体的沟道和漏部分上。
图1所示的常规MOSFET的接通电阻很大程度上由外延层101中的漂移区电阻决定。因为由外延层101维持用在N+掺杂衬底和P+掺杂深体区之间的反向电压，外延层101有时还称为电压维持层。相应地由外延层101的掺杂浓度和厚度决定漂移区电阻。但是，为了增加器件的击穿电压，增加层厚度的同时必须降低外延层101的掺杂浓度。图2中的曲线示出用于常规功率MOSFET作为击穿电压函数的每单位面积的接通电阻。不利地，如曲线所示，器件的接通电阻随着其击穿电压的增加而快速增加。当MOSFET工作在较高电压下，特别是在高于几百伏的电压下时，电阻的这种快速增加存在问题。
图3示出被设计成带有减小的接通电阻、在较高电压下工作的MOSFET。在Cezac等在 Proceeding of the ISPSD，2000年5月，69-72页，和Chen等在 IEEE Transactions on Electron Devices，2000年6月47卷6期1280-1285页中公开了这种MOSFET，在此通过引用将其全部结合进来。这种MOSFET与图1所示的常规MOSFET相似，此外它还包括一连串的纵向分隔P掺杂层3101、3102、3103，…310n(所谓的“浮岛”)，其位于电压维持层301的漂移区中。浮岛3101、3102、3103，…310n产生的电场比没有浮岛结构的电场低。较低电场允许在部分形成电压维持层301的外延层中使用较高的掺杂浓度。浮岛产生锯形电场轮廓，其整体导致维持电压层获得比用于常规器件中的浓度高的掺杂浓度。相应地，该较高的掺杂浓度产生器件的接通电阻具有比没有一层或多层浮岛的器件的接通电阻低。
用包括多步外延淀积步骤的工序可以制造图3所示的结构，每一步之后引入适当的掺杂剂。不利的是执行外延淀积步骤非常昂贵，由此制造使用多步外延淀积步骤的结构非常昂贵。
因此，需要提供一种功率半导体器件(例如图3所示的MOSFET结构)的制造方法，该方法需要最少量的外延淀积步骤，以能够较廉价地生产器件。
发明内容
按照本发明，提供一种形成功率半导体器件的方法。该方法开始于提供第一导电类型的衬底，并接着在衬底上形成电压维持区。通过在衬底上淀积第一导电类型的外延层和在外延层中形成至少一个沟槽来形成电压维持区。沿着沟槽壁淀积阻挡材料。穿过阻挡材料把第二导电类型的掺杂剂注入到邻近沟槽底部并在沟槽底部之下的部分外延层中。掺杂剂扩散在外延层中形成第一掺杂层，并至少从沟槽的底部去除阻挡材料。穿过第一掺杂层蚀刻沟槽，并在沟槽中淀积填充材料以基本上填充沟槽，由此完成电压维持区。在电压维持区上形成至少一个第二导电类型区以在它们之间限定结面。
由本发明方法形成的功率半导体器件可以选自由纵向DMOS、V槽DMOS和沟槽DMOS MOSFET、IGBT、双极晶体管及二极管构成的组。
按照本发明的另一个方面，提供了一种功率半导体器件。该器件包括第一导电类型的衬底和在衬底上设置的电压维持区。电压维持区包括具有第一导电类型的外延层和位于外延层中的至少一个沟槽。具有第二导电类型掺杂剂的至少一个掺杂层位于外延层中，邻近沟槽的侧壁。还提供了基本上填充沟槽的填充材料。在电压维持区上设置至少一个第二导电类型区以在它们之间限定结面。
附图说明
图1示出常规功率MOSFET结构的剖面图。
图2示出用于常规功率MOSFET、作为击穿电压函数的每单位面积的接通电阻。
图3示出包括带有位于体区之下浮岛的电压维持区的MOSFET结构，其被设计成以在相同电压下比与图1所描绘结构的每单位面积接通电阻低的接通电阻工作。
图4示出包括带有在体区之下和之间浮岛的电压维持区的MOSFET结构。
图5(a)-5(f)示出用于制造按照本发明构造的电压维持区的示例工艺步骤顺序。
具体实施方式
按照本发明，以下一般性介绍了在半导体功率器件的电压维持层中形成p型浮岛的方法。首先，在将形成器件电压维持区的外延层中蚀刻至少一个沟槽。每个沟槽居于将被设置的纵向成串岛位置的中心。通过把p型掺杂剂材料注入到沟槽的底部形成这些岛的第一水平面。注入的材料扩散到位于直接邻近沟槽底部和在沟槽底部之下的电压维持区部分。随后蚀刻沟槽到更深的深度，以致通过再次注入和扩散p型掺杂剂材料形成浮岛的第二水平面。该第二蚀刻步骤形成具有圆环形状(当沟槽是圆形的时)并位于第一水平面中的浮岛。如果沟槽具有非圆形的其它形状，例如正方形、矩形或六边形，那么沟槽的形状决定浮岛的形状。重复上述工艺直到形成所需数量的纵向岛层。最后，用不会不利影响器件特性的材料填充沟槽。用于填充沟槽材料的示例材料包括高电阻多晶硅、例如二氧化硅的介质或其它材料和材料的组合。
图4示出按照本发明构造的功率半导体器件。在本发明的该实施例中，假定沟槽是圆形的，因此把浮岛描绘成圆环形。在N+硅衬底402上形成的N型外延硅层401包含P体区405和用于器件中的两个MOSFET单元的N+源区407。如所示，P体区405a还可以包括深P体区405b。源体电极412横过外延层401的某些表面部分延伸以接触源区和体区。由延伸到上半导体表面的N型外延层401部分形成用于两个单元的N型漏。在N+衬底402的底部设置漏极。包括氧化物和多晶硅层的绝缘栅极418位于体的沟道和漏部分上。在由外延硅层401限定的器件电压维持区中设置成串的浮岛410。当从器件的顶部观察时，浮岛被布置成阵列。例如，在图4中，在“y”方向上，由参考标号41011、41012、41013，…4101m代表浮岛，在“z”方向上，由参考标号41011、41021、41031，…410m1代表浮岛。尽管可以应用或不应用位于栅418之下的浮岛列410，但当器件的几何尺寸和外延层401的电阻率需要时会应用它们。
按照以下在图5(a)-5(f)中说明的示例步骤制造图4所示的功率半导体器件。
首先，在常规N+掺杂衬底502上生长N型掺杂外延层501。对于具有5-40ohm-cm电阻率的400-800V的器件，外延层1一般是15-50微米厚。接着，通过用介质层覆盖外延层501的表面而形成介质掩模层，接着常规曝光并构图介质层以保留限定沟槽520位置的掩模部分。通过反应离子蚀刻穿过掩模开口干法蚀刻沟槽520到达5-15微米范围的最初深度。具体来说，如果“x”是所需的等间隔水平浮岛行的数量，那么沟槽520应最初蚀刻到位于体区底部和N+掺杂衬底顶部之间的外延层502厚度的大约1/(x+1)深度。如果需要，使每个沟槽的侧壁变光滑。首先，使用干法化学蚀刻从沟槽侧壁去除氧化物薄层(一般大约500-1000)，以消除由反应离子蚀刻工艺引起的损伤。接着，在沟槽上生长牺牲二氧化硅层。通过缓冲氧化物蚀刻或HF蚀刻去除牺牲层以使最终的沟槽侧壁尽可能光滑。
在图5(b)中，在沟槽520中生长二氧化硅层524。二氧化硅层524的厚度应足够防止注入的原子穿透邻近沟槽520侧壁和在沟槽520侧壁之下的硅，同时使注入的原子穿透在沟槽520底部的氧化层524以使它们能够淀积到邻近沟槽底部和在沟槽底部之下的硅中。接着，穿过在沟槽520底部的氧化物层注入掺杂剂528，例如硼。掺杂剂的总剂量和注入能量应选择成在每个水平面执行随后的扩散和蚀刻步骤之后在外延层501中剩余的掺杂剂量满足最终器件的击穿需要。接着，在图5(c)中，执行高温扩散步骤，纵向和横向地“推进(drive-in)”注入的掺杂剂528。从沟槽520的底部去除氧化物层524。可以从沟槽520的侧壁去除氧化物层524，或也可以不去除。
在图5(d)中，沟槽520深度增加大约等于位于体区底部和N+掺杂衬底之间的外延层501厚度的1/(x+1)的量。接着，重复在沟槽壁上生长氧化物层、穿过沟槽的底部注入并扩散掺杂剂和从沟槽的底部去除氧化物层，从而制造浮岛530的第二水平层。重复该工艺形成“x”层浮岛水平层所需的那么多次，其中选择“x”提供所需的击穿电压。例如，在图5(d)中，示出了四个这样的水平层528、530、532和534。如图5(e)所示，一旦形成最后的水平浮岛阵列，沟槽的深度增加足够蚀刻穿过最后的浮岛水平阵列的量。如果仅应用单个水平浮岛阵列，在本发明的某些实施例中将不是必须蚀刻穿过阵列。
最后，用不会对器件特性产生不利影响的材料填充沟槽520。示例材料包括但不限于热生长二氧化硅、例如二氧化硅的淀积介质、氮化硅或这些或其它材料的热生长和淀积层组合。最后，如图5(f)所示，整平该结构的表面。
在图5(f)中描述的上述工艺步骤顺序产生的结构提供了带浮岛的电压维持层，在浮岛上可以制造任意多个不同的功率半导体器件。如前面所提到的，这些功率半导体器件包括纵向DMOS、V槽DMOS和沟槽DMOS MOSFET、IGBT及其它MOS栅器件。例如，图4示出包括带有按照本发明的原理构造的浮岛的电压维持层的MOSFET实例。应注意到尽管图5示出用于形成圆环形浮岛列的单个沟槽，本发明包括具有形成任意多列具有多种不同形状浮岛的单个或多个沟槽的电压维持区。
一旦如图5所示形成电压维持区和浮岛，按以下方式可以完成图4所示的MOSFET。在形成有源区掩模之后生长栅氧化物。接着，淀积、掺杂和氧化多晶硅层。接着掩模多晶硅形成栅区。使用常规掩模、注入和扩散步骤形成p+掺杂深体区405b。例如，在20至200KeV用从大约1×104到5×1015/cm2的剂量硼注入p+掺杂深体区。以相似的方式形成浅体区405a。在20至100KeV的能量，对该区的注入剂量将为1×1013到5×1014/cm2。
接着，使用光刻掩模工艺形成限定源区407的构图掩模层。接着通过注入和扩散工艺形成源区407。例如，在20至100KeV用砷注入源区，达到一般大约2×1015到1.2×1016/cm2范围的浓度。在注入之后，砷扩散到大约0.5到2.0微米的深度。体区的深度一般在大约1-3微米的范围，P+掺杂深体区(如果存在)将稍深。最后，以常规方法去除掩模层。通过蚀刻氧化物层在前表面上形成接触开口，从而以常规方法完成了DMOS晶体管。还淀积并掩模金属化层来限定源体和栅极。而且，使用焊盘掩模限定焊盘接触。最后，在衬底的底表面上形成漏接触层。
应注意到尽管公开了制造功率MOSFET的特定工序，但在本发明的范围内还可以使用其它工序。例如，可以在限定栅区之前形成深p+掺杂体区。还可以在形成沟槽之前形成深p+掺杂体区。在一些DMOS结构中，P+掺杂深体区可以比P掺杂体区浅，或者在某些情况中，甚至可以不存在P+掺杂体区。
虽然这里特别说明并介绍了各个实施例，应意识到，上面的教导覆盖本发明的改进和变型，并且这些改进和变型在不脱离本发明的精神和确定范围的所附权利要求的范围内。例如，可以提供按照本发明的功率半导体器件，其中各个半导体区的导电性与这里介绍的那些相反。而且，尽管使用纵向DMOS晶体管说明了按照本发明制造器件所需的示例步骤，遵循这些教导还可以制造其它DMOSFET和例如二极管、双极晶体管、功率JFET、IGBT、MCT之类的其它功率半导体器件以及其它MOS栅功率器件。

Claims (40)

1.一种功率半导体器件的制造方法，包括步骤：
A.提供第一导电类型的衬底；
B.通过以下步骤在所述衬底上形成电压维持区：
1.在衬底上淀积外延层，所述外延层具有第一导电类型；
2.在所述外延层中形成至少一个沟槽；
3.沿着所述沟槽的壁淀积阻挡材料；
4.穿过阻挡材料把第二导电类型的掺杂剂注入到邻近所述沟槽底部并在所述沟槽底部之下的部分外延层中；
5.扩散所述掺杂剂以在所述外延层中形成第一掺杂层；
6.至少从沟槽的底部去除阻挡材料；
7.穿过所述第一掺杂层蚀刻沟槽；和
8.在所述沟槽中淀积填充材料以基本上填充所述沟槽；和
C.在所述电压维持区上形成至少一个所述第二导电类型区以在它们之间限定结面。
2.如权利要求1所述的方法，还包括步骤：
蚀刻沟槽到更深的深度并重复步骤(B.3)-(B.6)以在所述第一掺杂层之下纵向形成第二掺杂层；和
蚀刻沟槽穿过所述第二掺杂层。
3.如权利要求1所述的方法，其中，步骤(C)还包括步骤：
在栅介质区上形成栅导体；
在外延层中形成第一和第二体区以在它们之间限定漂移区，所述体区具有第二导电类型；
分别在第一和第二体区中形成第一导电类型的第一和第二源区。
4.如权利要求1所述的方法，其中，所述阻挡材料是氧化物材料。
5.如权利要求4所述的方法，其中，所述氧化物材料是二氧化硅。
6.如权利要求1所述的方法，其中，所述外延层具有给定的厚度，并且还包括步骤：
D.蚀刻沟槽基本上等于所述给定厚度的1/(x+1)的附加量，其中x等于或大于2，并与将在电压维持区中形成的掺杂层的规定数量相一致；
E.重复步骤(B.3)-(B.6)以在所述第一掺杂层之下纵向形成另一层掺杂层；和
F.重复步骤D-E直到形成规定数量的掺杂层；和
G.蚀刻沟槽穿过第x层的所述掺杂层。
7.如权利要求1所述的方法，其中，填充沟槽的所述材料是介质材料。
8.如权利要求7所述的方法，其中，所述介质材料是二氧化硅。
9.如权利要求7所述的方法，其中，所述介质材料是氮化硅。
10.如权利要求1所述的方法，其中，所述掺杂剂是硼。
11.如权利要求3所述的方法，其中，所述体区包括深体区。
12.如权利要求1所述的方法，其中，通过提供限定至少一个沟槽的掩模层并蚀刻由掩模层限定的沟槽而形成所述沟槽。
13.如权利要求3所述的方法，其中，通过把掺杂剂注入并扩散到衬底中而形成所述体区。
14.如权利要求1所述的方法，其中，所述功率半导体器件选自由纵向DMOS、V槽DMOS和沟槽DMOS MOSFET、IGBT及双极晶体管构成的组。
15.一种按照权利要求1所述的方法制造的功率半导体器件。
16.一种按照权利要求6所述的方法制造的功率半导体器件。
17.一种按照权利要求14所述的方法制造的功率半导体器件。
18.一种功率半导体器件，包括：
第一导电类型的衬底；
在所述衬底上设置的电压维持区，所述电压维持区包括：
具有第一导电类型的外延层；
位于所述外延层中的至少一个沟槽；
具有第二导电类型掺杂剂的至少一个掺杂层，所述掺杂层位于邻近所述沟槽侧壁的所述外延层中；
基本上填充所述沟槽的填充材料；和
在所述电压维持区上设置的所述第二导电类型的至少一个区，用以在它们之间限定结面。
19.如权利要求18所述的器件，其中，所述的至少一个掺杂层包括多个掺杂层，每个所述掺杂层相对于另一个位于垂直列中。
20.如权利要求18所述的器件，其中，所述的至少一个区还包括：
栅介质和在所述栅介质上设置的栅导体；
位于外延层中的第一和第二体区，在它们之间限定漂移区，所述体区具有第二导电类型；和
分别位于第一和第二体区中的第一导电类型的第一和第二源区。
21.如权利要求18所述的器件，其中，填充沟槽的所述材料是介质材料。
22.如权利要求21所述的器件，其中，所述介质材料是二氧化硅。
23.如权利要求21所述的器件，其中，所述介质材料是氮化硅。
24.如权利要求18所述的器件，其中，所述掺杂剂是硼。
25.如权利要求20所述的器件，其中，所述体区包括深体区。
26.如权利要求18所述的器件，其中，所述沟槽具有圆形截面。
27.如权利要求26所述的器件，其中，所述至少一个掺杂层是圆环形。
28.如权利要求19所述的器件，其中，多个掺杂层中的至少一个是圆环形。
29.如权利要求18所述的器件，其中，所述沟槽具有选自由正方形、矩形、八边形和六边形构成组的截面形状。
30.一种功率半导体器件的制造方法，包括步骤：
A.提供第一导电类型的衬底；
B.通过以下步骤在所述衬底上形成电压维持区：
1.在衬底上淀积外延层，所述外延层具有第一导电类型；
2.在所述外延层中形成至少一个沟槽；
3.沿着所述沟槽的壁淀积阻挡材料；
4.穿过阻挡材料把第二导电类型的掺杂剂注入到邻近所述沟槽底部并在所述沟槽底部之下的部分外延层中；
5.扩散所述掺杂剂以在所述外延层中形成第一掺杂层；
6.至少从沟槽的底部去除阻挡材料；
7.在所述沟槽中淀积填充材料以基本上填充所述沟槽；和
C.在所述电压维持区上形成至少一个所述第二导电类型区，以在它们之间限定结面。
31.如权利要求30所述的方法，还包括步骤：蚀刻沟槽穿过所述第一掺杂层。
32.如权利要求31所述的方法，还包括步骤：
蚀刻沟槽到更深的深度并重复步骤(B.3)-(B.6)以在所述第一掺杂层之下纵向形成第二掺杂层；和
蚀刻沟槽穿过所述第二掺杂层。
33.如权利要求30所述的方法，其中，步骤(C)还包括步骤：
在栅介质区上形成栅导体；
在外延层中形成第一和第二体区以在它们之间限定漂移区，所述体区具有第二导电类型；
分别在第一和第二体区中形成第一导电类型的第一和第二源区。
34.如权利要求30所述的方法，其中，所述阻挡材料是氧化物材料。
35.如权利要求34所述的方法，其中，所述氧化物材料是二氧化硅。
36.如权利要求31所述的方法，其中，所述外延层具有给定厚度，并且还包括步骤：
D.蚀刻沟槽基本上等于所述给定厚度的1/(x+1)的附加量，其中x等于或大于2，并与将在电压维持区中形成的掺杂层的规定数量相一致；
E.重复步骤(B.3)-(B.6)以在所述第一掺杂层之下纵向形成另一层掺杂层；
F.重复步骤D-E直到形成规定数量的掺杂层；和
G.蚀刻沟槽穿过第x层的所述掺杂层。
37.如权利要求30所述的方法，其中，填充沟槽的所述材料是介质材料。
38.如权利要求37所述的方法，其中，所述介质材料是二氧化硅。
39.如权利要求37所述的方法，其中，所述介质材料是氮化硅。
40.如权利要求30所述的方法，其中，所述掺杂剂是硼。
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Cited By (4)

* Cited by examiner, † Cited by third party
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CN102468177A (zh) * 2010-11-19 2012-05-23 无锡华润上华半导体有限公司 P型dmos器件及其制造方法
CN105489646A (zh) * 2015-12-22 2016-04-13 上海华虹宏力半导体制造有限公司 Igbt电荷存储层形成的方法和电荷存储型igbt
CN114242778A (zh) * 2022-02-23 2022-03-25 山东晶芯科创半导体有限公司 高频率大功率的新型沟槽mos场效应管

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7745289B2 (en) 2000-08-16 2010-06-29 Fairchild Semiconductor Corporation Method of forming a FET having ultra-low on-resistance and low gate charge
US6803626B2 (en) 2002-07-18 2004-10-12 Fairchild Semiconductor Corporation Vertical charge control semiconductor device
US6916745B2 (en) 2003-05-20 2005-07-12 Fairchild Semiconductor Corporation Structure and method for forming a trench MOSFET having self-aligned features
US6818513B2 (en) 2001-01-30 2004-11-16 Fairchild Semiconductor Corporation Method of forming a field effect transistor having a lateral depletion structure
US6710403B2 (en) 2002-07-30 2004-03-23 Fairchild Semiconductor Corporation Dual trench power MOSFET
US6750104B2 (en) * 2001-12-31 2004-06-15 General Semiconductor, Inc. High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching using an etchant gas that is also a doping source
US6656797B2 (en) * 2001-12-31 2003-12-02 General Semiconductor, Inc. High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and ion implantation
US6576516B1 (en) * 2001-12-31 2003-06-10 General Semiconductor, Inc. High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and diffusion from regions of oppositely doped polysilicon
US6686244B2 (en) * 2002-03-21 2004-02-03 General Semiconductor, Inc. Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step
US7161208B2 (en) * 2002-05-14 2007-01-09 International Rectifier Corporation Trench mosfet with field relief feature
US7576388B1 (en) 2002-10-03 2009-08-18 Fairchild Semiconductor Corporation Trench-gate LDMOS structures
US6710418B1 (en) 2002-10-11 2004-03-23 Fairchild Semiconductor Corporation Schottky rectifier with insulation-filled trenches and method of forming the same
TWI223448B (en) * 2003-04-29 2004-11-01 Mosel Vitelic Inc DMOS device having a trenched bus structure
US7638841B2 (en) 2003-05-20 2009-12-29 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US7015104B1 (en) 2003-05-29 2006-03-21 Third Dimension Semiconductor, Inc. Technique for forming the deep doped columns in superjunction
KR100994719B1 (ko) 2003-11-28 2010-11-16 페어차일드코리아반도체 주식회사 슈퍼정션 반도체장치
US7368777B2 (en) 2003-12-30 2008-05-06 Fairchild Semiconductor Corporation Accumulation device with charge balance structure and method of forming the same
US7352036B2 (en) 2004-08-03 2008-04-01 Fairchild Semiconductor Corporation Semiconductor power device having a top-side drain using a sinker trench
GB0417749D0 (en) * 2004-08-10 2004-09-08 Eco Semiconductors Ltd Improved bipolar MOSFET devices and methods for their use
US8004049B2 (en) 2004-08-31 2011-08-23 Freescale Semiconductor, Inc. Power semiconductor device
CN101882583A (zh) 2005-04-06 2010-11-10 飞兆半导体公司 沟栅场效应晶体管及其形成方法
US20090026586A1 (en) * 2005-04-22 2009-01-29 Icemos Technology Corporation Superjunction Device Having Oxide Lined Trenches and Method for Manufacturing a Superjunction Device Having Oxide Lined Trenches
US20060255401A1 (en) * 2005-05-11 2006-11-16 Yang Robert K Increasing breakdown voltage in semiconductor devices with vertical series capacitive structures
US20070012983A1 (en) * 2005-07-15 2007-01-18 Yang Robert K Terminations for semiconductor devices with floating vertical series capacitive structures
US7446018B2 (en) 2005-08-22 2008-11-04 Icemos Technology Corporation Bonded-wafer superjunction semiconductor device
US7378717B2 (en) * 2005-11-15 2008-05-27 International Business Machines Corporation Semiconductor optical sensors
US20070157516A1 (en) * 2006-01-09 2007-07-12 Fischer Bernhard A Staged modular hydrocarbon reformer with internal temperature management
US7446374B2 (en) 2006-03-24 2008-11-04 Fairchild Semiconductor Corporation High density trench FET with integrated Schottky diode and method of manufacture
US7319256B1 (en) 2006-06-19 2008-01-15 Fairchild Semiconductor Corporation Shielded gate trench FET with the shield and gate electrodes being connected together
US7691734B2 (en) * 2007-03-01 2010-04-06 International Business Machines Corporation Deep trench based far subcollector reachthrough
US8580651B2 (en) * 2007-04-23 2013-11-12 Icemos Technology Ltd. Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material
US7723172B2 (en) 2007-04-23 2010-05-25 Icemos Technology Ltd. Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material
CN101868856B (zh) 2007-09-21 2014-03-12 飞兆半导体公司 用于功率器件的超结结构及制造方法
US8012806B2 (en) 2007-09-28 2011-09-06 Icemos Technology Ltd. Multi-directional trenching of a die in manufacturing superjunction devices
US7772668B2 (en) * 2007-12-26 2010-08-10 Fairchild Semiconductor Corporation Shielded gate trench FET with multiple channels
CN101510557B (zh) * 2008-01-11 2013-08-14 艾斯莫斯技术有限公司 具有电介质终止的超结半导体器件及制造该器件的方法
US7880224B2 (en) * 2008-01-25 2011-02-01 Infineon Technologies Austria Ag Semiconductor component having discontinuous drift zone control dielectric arranged between drift zone and drift control zone and a method of making the same
US7846821B2 (en) * 2008-02-13 2010-12-07 Icemos Technology Ltd. Multi-angle rotation for ion implantation of trenches in superjunction devices
US7795045B2 (en) * 2008-02-13 2010-09-14 Icemos Technology Ltd. Trench depth monitor for semiconductor manufacturing
US8030133B2 (en) 2008-03-28 2011-10-04 Icemos Technology Ltd. Method of fabricating a bonded wafer substrate for use in MEMS structures
US20120273916A1 (en) 2011-04-27 2012-11-01 Yedinak Joseph A Superjunction Structures for Power Devices and Methods of Manufacture
US8432000B2 (en) 2010-06-18 2013-04-30 Fairchild Semiconductor Corporation Trench MOS barrier schottky rectifier with a planar surface using CMP techniques
CN110010671B (zh) * 2011-04-27 2022-04-29 飞兆半导体公司 功率器件及其制造方法
US8786010B2 (en) 2011-04-27 2014-07-22 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8673700B2 (en) 2011-04-27 2014-03-18 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8772868B2 (en) 2011-04-27 2014-07-08 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8836028B2 (en) 2011-04-27 2014-09-16 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
JP2014518017A (ja) 2011-05-18 2014-07-24 ビシャイ‐シリコニックス 半導体デバイス
US8946814B2 (en) 2012-04-05 2015-02-03 Icemos Technology Ltd. Superjunction devices having narrow surface layout of terminal structures, buried contact regions and trench gates
KR101367491B1 (ko) * 2012-08-08 2014-02-26 고려대학교 산학협력단 단일 ｆｌｉ 구조를 갖는 반도체 소자의 제조 방법 및 그 제조 방법으로 제조된 반도체 소자
US9048115B2 (en) 2012-10-26 2015-06-02 Vanguard International Semiconductor Corporation Superjunction transistor with implantation barrier at the bottom of a trench
TWI473267B (zh) * 2012-11-06 2015-02-11 Ind Tech Res Inst 金氧半場效電晶體元件
TWI506705B (zh) * 2012-11-14 2015-11-01 Vanguard Int Semiconduct Corp 半導體裝置及其製造方法
CN103413822B (zh) * 2013-08-22 2016-05-18 中国电子科技集团公司第二十四研究所 降低浮空埋层半导体器件漏电流的方法
CN103594503A (zh) * 2013-11-19 2014-02-19 西安永电电气有限责任公司 具有浮结结构的igbt

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4140558A (en) * 1978-03-02 1979-02-20 Bell Telephone Laboratories, Incorporated Isolation of integrated circuits utilizing selective etching and diffusion
US4419150A (en) * 1980-12-29 1983-12-06 Rockwell International Corporation Method of forming lateral bipolar transistors
US4569701A (en) * 1984-04-05 1986-02-11 At&T Bell Laboratories Technique for doping from a polysilicon transfer layer
US4711017A (en) * 1986-03-03 1987-12-08 Trw Inc. Formation of buried diffusion devices
US4893160A (en) * 1987-11-13 1990-01-09 Siliconix Incorporated Method for increasing the performance of trenched devices and the resulting structure
JP2733271B2 (ja) * 1988-12-23 1998-03-30 シャープ株式会社 半導体装置の製造方法
CN1019720B (zh) 1991-03-19 1992-12-30 电子科技大学 半导体功率器件
JP3395473B2 (ja) * 1994-10-25 2003-04-14 富士電機株式会社 横型トレンチｍｉｓｆｅｔおよびその製造方法
JP4047384B2 (ja) * 1996-02-05 2008-02-13 シーメンス アクチエンゲゼルシヤフト 電界効果により制御可能の半導体デバイス
DE19830332C2 (de) * 1998-07-07 2003-04-17 Infineon Technologies Ag Vertikales Halbleiterbauelement mit reduziertem elektrischem Oberflächenfeld
CN1099715C (zh) * 1998-07-23 2003-01-22 电子科技大学 一种用于有浮动电压端的半导体器件的表面耐压层
DE19843959B4 (de) * 1998-09-24 2004-02-12 Infineon Technologies Ag Verfahren zum Herstellen eines Halbleiterbauelements mit einem sperrenden pn-Übergang
US6316336B1 (en) * 1999-03-01 2001-11-13 Richard A. Blanchard Method for forming buried layers with top-side contacts and the resulting structure
KR100773380B1 (ko) * 1999-06-03 2007-11-06 제네럴 세미컨덕터, 인코포레이티드 전력 ｍｏｓｆｅｔ, 이를 형성하는 방법, 및 이 방법에 의해 형성되는 다른 전력 ｍｏｓｆｅｔ
DE19943143B4 (de) * 1999-09-09 2008-04-24 Infineon Technologies Ag Halbleiterbauelement für hohe Sperrspannungen bei gleichzeitig niedrigem Einschaltwiderstand und Verfahren zu dessen Herstellung
GB9929613D0 (en) * 1999-12-15 2000-02-09 Koninkl Philips Electronics Nv Manufacture of semiconductor material and devices using that material
JP4371521B2 (ja) * 2000-03-06 2009-11-25 株式会社東芝 電力用半導体素子およびその製造方法
GB0010041D0 (en) * 2000-04-26 2000-06-14 Koninkl Philips Electronics Nv Trench semiconductor device manufacture

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102468177A (zh) * 2010-11-19 2012-05-23 无锡华润上华半导体有限公司 P型dmos器件及其制造方法
CN102420251A (zh) * 2011-12-05 2012-04-18 电子科技大学 一种具有非均匀浮岛结构的vdmos器件
CN105489646A (zh) * 2015-12-22 2016-04-13 上海华虹宏力半导体制造有限公司 Igbt电荷存储层形成的方法和电荷存储型igbt
CN114242778A (zh) * 2022-02-23 2022-03-25 山东晶芯科创半导体有限公司 高频率大功率的新型沟槽mos场效应管
CN114242778B (zh) * 2022-02-23 2022-05-17 山东晶芯科创半导体有限公司 高频率大功率的沟槽mos场效应管

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US6465304B1 (en) 2002-10-15

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