CN1503988A - 无凸点半导体器件 - Google Patents

无凸点半导体器件 Download PDF

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CN1503988A
CN1503988A CNA028084640A CN02808464A CN1503988A CN 1503988 A CN1503988 A CN 1503988A CN A028084640 A CNA028084640 A CN A028084640A CN 02808464 A CN02808464 A CN 02808464A CN 1503988 A CN1503988 A CN 1503988A
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semiconductor device
salient point
welding zone
conducting particles
electrode welding
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CN100342513C (zh
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������ɽ����
山田幸男
֮
中村雅之
菱沼启之
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Dexerials Corp
Sony Corp
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Abstract

本发明的课题是一种无凸点半导体器件,系通过将导电粒子4与在周围设置了钝化膜3的半导体器件的电极焊区2进行金属键合而进行连接,它谋求抑制短路、减少连接成本、抑制向连接部的应力集中、以及减少附加于IC芯片1及电路基板5的损伤,能用倒装芯片方式以高可靠性且以低成本连接IC芯片1与电路基板5。使用在树脂粒子的表面上形成了金属镀层的复合粒子作为导电粒子4。该无凸点半导体器件可通过(a)使导电粒子4以静电方式吸附于平板的一面上,(b)将该平板的导电粒子吸附面重叠在半导体器件的电极焊区面上,进行超声压焊,使导电粒子4与电极焊区2进行金属键合,从该平板复制到电极焊区2上而制造。

Description

无凸点半导体器件
技术领域
本发明涉及无凸点半导体器件。
背景技术
当采用倒装芯片方式将裸露IC芯片连接到电路基板上时,为了防止在未被钝化膜覆盖的划片线处短路的发生,必须在IC芯片与电路基板之间进行隔离。因此,在IC芯片上广泛地形成了高度约为10μm~80μm的连接用凸点(图3~图5)。
在图3的实施形态的情况下,对具有用柱形凸点法形成的金凸点31的IC芯片32的该金凸点31和电路基板33的连接端子34,通过将导电粒子35分散在粘结成分36中构成的各向异性导电粘结剂37(膜或膏)进行热压焊。另外,在图4的实施形态的情况下,对具有用柱形凸点法形成的金凸点41的IC芯片42的该金凸点41和电路基板43的连接端子44,通过绝缘性粘结材料45(膜或膏)进行热压焊。
再有,在图3和图4的实施形态中,由于凸点31(41)与连接端子34(44)无相互的金属键合,IC芯片与电路基板之间的粘结力依赖于各向异性导电粘结剂中(绝缘性粘结剂中)的粘结成分的凝结力。
另外,在图5的实施形态的情况下,利用焊锡膏印刷/回流法等,将形成了焊锡凸点51的IC芯片52的该焊锡凸点51与电路基板53上用焊剂处理过的连接端子54接触,通过加热到焊锡的熔点以上,将焊锡凸点51与连接端子54连接起来,用底层填料55充填在IC芯片52与电路基板53的间隙。这时,在底层填料55充填前,通常要进行去除焊剂的清洗操作。
然而,在图3~图5的实施形态的情况下,由于全部前提为在IC芯片上形成加工成本高的凸点,所以存在IC芯片的形状方面的自由度降低,而且难以使IC芯片与电路基板之间的连接成本降低的问题。
另外,在图3和图4的实施形态中,由于凸点31(41)与连接端子34(44)之间无金属键合,IC芯片与电路基板之间的粘结力不得不依赖于各向异性导电粘结剂中(绝缘性粘结剂中)的粘结成分的凝结力,在使用各向异性导电粘结剂的图3的实施形态的情况下,可确保连接可靠性,但在未使用各向异性导电粘结剂的图4的实施形态的情况下,与金属键合的情况相比,存在连接可靠性降低的问题。
此外,在图3的实施形态的情况下,伴随凸点间距的微细化和凸点尺寸的微小化,为了使导电粒子35确实存在于凸点31与连接端子34之间,如果增加各向异性导电粘结剂37中导电粒子35的含有比例,则存在增大发生短路的危险性的问题。另外,由于导电粒子35的采购成本较高,所以存在IC芯片32与电路基板33之间的连接成本也增大的问题。在图4的实施形态的情况下,由于对凸点41与连接端子44直接压接而不使导电粒子夹在凸点41与连接端子44之间,所以存在应力集中于连接部,连接可靠性更加降低的问题。另外,由于必须增高压焊时的压力,所以IC芯片及电路基板有可能受到较大的损伤。
另一方面,在图5的实施形态的情况下,焊锡凸点51与连接端子54进行了金属键合,连接可靠性比较充分,但如果为了形成金属键合而确保充分的凸点尺寸,则存在焊锡凸点51的微细间距难以实现的问题。此外,还存在焊剂F的清洗工序和底层填料55的充填工序增加的问题。
发明内容
本发明就是要解决以上的现有技术的课题的发明,其目的在于:在将裸露IC芯片等的半导体器件以倒装芯片方式连接到电路基板上时,在半导体器件中不形成凸点,谋求抑制短路、减少连接成本、抑制向连接部的应力集中、以及减少附加于IC芯片及电路基板的损伤,使得以高可靠性并且以低成本连接IC芯片与电路基板成为可能。
本发明人发现,一旦将导电粒子以静电方式吸附在玻璃板等的平板上,通过将该平板的导电粒子吸附面重叠在半导体器件的电极焊区一侧表面上,进行超声压焊,则只在电极焊区处可对导电粒子进行金属键合,从而使本发明得以完成。
即,本发明是电极焊区被设置在表面上并且钝化膜被设置在电极焊区的周围的无凸点半导体器件,它提供了一种无凸点半导体器件,其特征在于:通过将导电粒子与电极焊区进行金属键合而进行连接。
另外,本发明提供了一种无凸点半导体器件的制造方法,其特征在于,具有以下的工序(a)和(b):
(a)使导电粒子以静电方式吸附于平板的一面上的工序;以及
(b)通过将该平板的导电粒子吸附面重叠在将电极焊区设置在表面上并且将钝化膜设置在电极焊区的周围的无凸点半导体器件的电极焊区面上,进行超声压焊,使导电粒子与电极焊区进行金属键合,从该平板复制到电极焊区上的工序。
另外,本发明提供了一种连接结构体,其特征在于:用绝缘性粘结材料将该无凸点半导体器件与电路基板进行键合,以便将与该无凸点半导体器件的连接焊区进行了金属键合的导电粒子与电路基板的连接端子接触。
附图说明
图1是本发明的无凸点半导体器件的概略剖面图。
图2是本发明的无凸点半导体器件和连接结构体的制造工序图。
图3是IC芯片与电路基板的现有的连接形态的说明图。
图4是IC芯片与电路基板的现有的连接形态的说明图。
图5是IC芯片与电路基板的现有的连接形态的说明图。
具体实施方式
以下,参照附图详细地说明本发明。
图1是将本发明的无凸点半导体器件应用于IC芯片的例子。该IC芯片1具有无凸点结构,系将铝等的电极焊区2设置在表面上,而在电极焊区2的周围设置其表面位置水平比电极焊区2的表面位置水平高的钝化膜3。然后利用导电粒子4与电极焊区2进行金属键合而进行连接。从而,电极焊区2与导电粒子4之间的连接可靠性能做到与在图3~图5所示的在现有的IC芯片上形成的凸点匹敌。而且,在使导电粒子4与电极焊区2进行金属键合时,不用繁杂且成本高的现有的凸点形成法,可用超声压焊法等较低成本的方法进行金属键合。此外,由于作为导电粒子4存在,导电粒子4与电路基板的连接端子(被连接体)之间的连接可靠性也可与现有的各向异性导电连接法的匹敌。
在本发明中,作为导电粒子4,可使用焊锡粒子、镍粒子等的金属粒子,或在苯并鸟粪胺等的树脂粒子(核)的表面形成了镍或金等的金属镀层的复合粒子。其中,最好使用以可减缓施加于连接部分的应力的树脂粒子为核的复合粒子。
导电粒子4的粒径最好采取这样的大小,使进行了金属键合的导电粒子4的至少一部分突出于钝化膜3的表面外侧。即,最好比钝化膜3与电极焊区2之间的表面位置水平之差要大。由此,可抑制划片线中短路的发生,并且可提高对被连接体(电路基板)的连接可靠性。这时,在与电极焊区2可进行金属键合的范围内,虽然可使导电粒子4的粒径做得比电极焊区2的直径大,但为了更有效地抑制导电粒子4彼此之间在横向的短路,最好将导电粒子4的粒径做得比电极焊区2的直径小。具体地说,当为金属粒子时,导电粒子4的粒径最好为1~50μm,如为3~40μm则更好,当为复合粒子时,树脂粒子的直径最好为1~50μm,如为3~40μm则更好,而且金属镀层的厚度最好为10nm~1μm,如为15nm~1μm则更好。
另外,作为导电粒子4的最外层,最好形成约5nm~0.5μm厚度的薄的金镀层,从减小接触电阻的观点看,这是比较理想的。
再有,作为图1的实施形态中的IC芯片1、电极焊区2、钝化膜3的具体结构,可分别采用熟知的现有结构。
接着,在每道工序中说明本发明的无凸点半导体器件(IC芯片)的制造方法。
工序(a)
如图2(a)所示,首先,使上述的导电粒子4以静电方式吸附于玻璃平板等的平板21的一面上。这时,为了有效地进行工序(b)中的超声压焊时的导电粒子的转移,以单层吸附为宜。作为以静电方式将导电粒子4吸附于平板21上的方法,可用聚酯布等擦拭平板21的表面使之带静电,然后将导电粒子4散布在该面上。关于未曾吸附的导电粒子,可通过使平板21倾斜或翻转,并且对平板21轻轻地给予振动而除去。
工序(b)
接着,如图2(b)所示,将平板21的导电粒子吸附面重叠在将电极焊区2设置在表面上并且将钝化膜3设置在电极焊区2的周围的IC芯片1的电极焊区面2上,最好从箭头的方向进行超声压焊(图2(c))。由此,可使导电粒子4与电极焊区2进行金属键合,从该平板21复制到电极焊区2上。再有,对于作为绝缘膜的钝化膜3,由于导电粒子不进行金属键合,因而不转移。
作为超声压焊条件,例如可举出使用10~100KHz的频率,在1~100Mpa(每个电极焊区)的压力下焊接0.1~20秒的认可条件。作为可使用的具体装置可举出“超声微焊接系统”(Ultrasonic MicroWelding System(SH40MP,ULTAX公司制))。
工序(c)
根据需要,如将附着了钝化膜3的导电粒子4转移到市售的粘结片上,或通过吹气处理吹除,则可得到图2(d)所示的无凸点半导体器件(IC芯片)1。
采用图2(d)所示的无凸点半导体器件(IC芯片)1,可实现具有高的接触可靠性的连接结构体。具体地说,可举出用熟知的膜状或膏状的绝缘性粘结材料7将无凸点半导体器件1与电路基板5键合起来的连接结构体(图2(e)),使得与连接焊区2进行了金属键合的导电粒子4与电路基板5的连接端子6接触。
实施例
以下,利用实施例具体地说明本发明。
实施例1~8和比较例1~4
在用聚酯布擦拭玻璃平板的一面以后,在该面上散布并吸附表1的导电粒子,多余的导电粒子通过使玻璃平板倾斜并轻轻地振动而除去。其中,实施例6使用了在Ni核的表面上设置Au镀层的金属粒子作为导电粒子,而在其它的实施例和比较例中却使用了在苯并鸟粪胺(核心树脂粒子)的表面上形成Ni镀层和Au镀层的复合粒子。
将该玻璃平板的导电粒子吸附面重叠于在一面上铝电极焊区以80μm的间距设置500个的10mm见方的IC芯片的电极焊区形成面上,从玻璃平板一侧,利用超声压焊装置“超声微焊接系统”(UltrasonicMicro Welding System(SH40MP,ULTAX公司制))进行超声压焊处理(频率10、50或100kHz;压力49Mpa;处理时间10秒)。由此,通过将导电粒子与IC芯片的电极焊区进行金属键合而使之转移。附着在钝化膜上的多余的导电粒子通过吹气处理被吹掉,得到图1所示的无凸点半导体器件(IC芯片)。
                       表1
                     导电粒子                     超声压焊
       核心树脂粒子直径  Ni镀层厚度  Au镀层厚度     频率
          (μm)             (μm)       (nm)        (kHz)实施例1     5               0.15         20          50
      2     1               0.15         20          50
      3     50              0.15         20          50
      4     5               0.15         10          50
      5     5               0.15         1000        50
      6     10              -            20          50
      7     5               0.15         20          10
      8     5               0.15         20          100
比较例1     0.5             0.15         10          50
      2     55              0.15         20          10
      3     5               0.15         20          50
      4     5               0.15         1100        50
接着,使所得到的无凸点半导体装置的电极焊区对着25μm厚的聚酰亚胺电路基板的连接端子(在8μm高度的铜上镀了金的电路图形(80μm间距))进行对位,在它们之间夹以热固化型环氧类绝缘性粘结膜(从各向异性导电粘结膜(FP16613,索尼化学公司制)除去导电粒子而得到的膜),在190℃、压力1960kPa、10秒的条件下进行热压焊,得到连接结构体。
对所得到的连接结构体进行-55℃←→125℃之间的热振动(1000个循环)试验,在使用了实施例1~5、7~8的无凸点半导体器件的连接结构体中,其电阻上升全部在10mΩ以内,表现出优越的连接可靠性。另外,在使用了实施例6的无凸点半导体器件的连接结构体中,其电阻上升为200mΩ左右,而这在实用上却是没有问题的水平。
另一方面,在使用了比较例1的无凸点半导体器件的连接结构体中,由于核心树脂粒子直径过小,其电阻上升超过1Ω。在使用了比较例2的无凸点半导体器件的连接结构体中,由于核心树脂粒子直径过大,出现了不能装载于焊区上的粒子,初始电阻值增高,不适合使用。在使用了比较例3的无凸点半导体器件的连接结构体中,由于核心树脂粒子表面的金属镀层的厚度过薄,出现了导电粒子不转移的电极焊区,初始电阻值增高,不适合使用。另外,在使用了比较例4的无凸点半导体器件的连接结构体中,由于核心树脂粒子表面的金属镀层的厚度过厚,导电粒子彼此之间凝聚,短路发生了。
工业上的可利用性
按照本发明,在将IC芯片等以倒装芯片方式连接到电路基板上时,在半导体器件上不形成凸点,谋求抑制短路、减少连接成本、抑制向连接部的应力集中、以及减少附加于IC芯片及电路基板的损伤,能以高可靠性并且以低成本连接IC芯片与电路基板。

Claims (6)

1.一种无凸点半导体器件,它是电极焊区被设置在表面上并且钝化膜被设置在电极焊区的周围的无凸点半导体器件,其特征在于:
通过将导电粒子与电极焊区进行金属键合而进行连接。
2.如权利要求1所述的无凸点半导体器件,其特征在于:
导电粒子是在树脂粒子的表面上形成了金属镀层的复合粒子。
3.如权利要求2所述的无凸点半导体器件,其特征在于:
树脂粒子的直径为1~50μm,金属镀层的厚度为10nm~1μm。
4.如权利要求1~3的任一项中所述的无凸点半导体器件,其特征在于:
进行了金属键合的导电粒子的至少一部分突出于钝化膜表面的外侧。
5.如权利要求1~4的任一项中所述的无凸点半导体器件的制造方法,其特征在于,具有以下的工序(a)和(b):
(a)使导电粒子以静电方式吸附于平板的一面上的工序;以及
(b)通过将该平板的导电粒子吸附面重叠在将电极焊区设置在表面上并且将钝化膜设置在电极焊区的周围的无凸点半导体器件的电极焊区面上,进行超声压焊,使导电粒子与电极焊区进行金属键合,从该平板复制到电极焊区上的工序。
6.一种连接结构体,其特征在于:
用绝缘性粘结材料将该无凸点半导体器件与电路基板进行键合,以便将与权利要求1~4的任一项中所述的无凸点半导体器件的连接焊区进行了金属键合的导电粒子与电路基板的连接端子接触。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103079343A (zh) * 2011-10-26 2013-05-01 日立化成工业株式会社 电路零件
CN102053395B (zh) * 2009-10-28 2013-05-01 财团法人工业技术研究院 凸块结构、芯片封装结构及该凸块结构的制备方法

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7045884B2 (en) * 2002-10-04 2006-05-16 International Rectifier Corporation Semiconductor device package
JP2005108871A (ja) * 2003-09-26 2005-04-21 Sekisui Chem Co Ltd 金属バンプ、金属バンプの形成方法、半導体チップ及び導電接続構造体
US20050110126A1 (en) * 2003-11-25 2005-05-26 Kai-Chiang Wu Chip adhesive
US6993835B2 (en) * 2003-12-04 2006-02-07 Irvine Sensors Corp. Method for electrical interconnection of angularly disposed conductive patterns
JP3997991B2 (ja) * 2004-01-14 2007-10-24 セイコーエプソン株式会社 電子装置
US7438395B2 (en) * 2004-09-24 2008-10-21 Brother Kogyo Kabushiki Kaisha Liquid-jetting apparatus and method for producing the same
KR101084777B1 (ko) * 2005-02-03 2011-11-21 파나소닉 주식회사 플립 칩 실장체와 그 실장 방법 및 범프 형성 방법
KR100801073B1 (ko) * 2005-10-06 2008-02-11 삼성전자주식회사 도전성 입자를 포함하는 범프를 구비하는 반도체 칩 및 이의 제조 방법
US7550846B2 (en) * 2005-12-21 2009-06-23 Palo Alto Research Center Conductive bump with a plurality of contact elements
KR100665363B1 (ko) * 2005-12-28 2007-01-09 삼성전기주식회사 Cmos 공정을 이용한 반도체 칩 패키지 및 그 제조방법
KR101309319B1 (ko) * 2006-11-22 2013-09-13 삼성디스플레이 주식회사 액정표시장치 구동회로 및 그의 제조방법과 액정표시장치구동회로가 실장 된 액정표시장치
TWI397978B (zh) * 2007-12-12 2013-06-01 Ind Tech Res Inst 晶片結構及其製程與覆晶封裝結構及其製程
US8563357B2 (en) * 2008-06-26 2013-10-22 Infineon Technologies Ag Method of packaging a die
TWI412107B (zh) * 2009-10-02 2013-10-11 Ind Tech Res Inst 凸塊結構、晶片封裝結構及該凸塊結構之製備方法
US20120228768A1 (en) * 2011-03-07 2012-09-13 Reza Argenty Pagaila Integrated circuit packaging system using b-stage polymer and method of manufacture thereof
KR20200130550A (ko) 2019-05-08 2020-11-19 삼성디스플레이 주식회사 표시 장치 및 표시 장치의 제조 방법

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54152470A (en) 1978-05-22 1979-11-30 Nec Corp Semiconductor device
US4618739A (en) * 1985-05-20 1986-10-21 General Electric Company Plastic chip carrier package
JPH0740496B2 (ja) 1989-03-01 1995-05-01 シャープ株式会社 電極上への導電性粒子の配置方法
JPH0327542A (ja) 1989-06-23 1991-02-05 Seiko Epson Corp 半導体装置の実装構造
JPH03185894A (ja) 1989-12-15 1991-08-13 Canon Inc 電極端子の相互接続方法
ATE138225T1 (de) 1989-08-17 1996-06-15 Canon Kk Prozess zur gegenseitigen konnektion von elektrodenanschlüssen
JP2704033B2 (ja) 1990-07-23 1998-01-26 キヤノン株式会社 電極端子の相互接続方法
JPH0547839A (ja) 1991-08-09 1993-02-26 Seiko Epson Corp 半導体集積回路素子実装方法
JPH05110243A (ja) 1991-10-17 1993-04-30 Fujitsu Ltd ワイヤ接合方法
JPH0682749A (ja) * 1992-09-01 1994-03-25 Seiko Epson Corp チップ実装方法、並びにチップ実装構造及びそれを用いた電気光学装置及び電子印字装置
US5420520A (en) * 1993-06-11 1995-05-30 International Business Machines Corporation Method and apparatus for testing of integrated circuit chips
JPH0737890A (ja) 1993-07-16 1995-02-07 Matsushita Electric Ind Co Ltd 半田ボール接合装置およびその接合方法
JPH07297228A (ja) * 1994-04-22 1995-11-10 Victor Co Of Japan Ltd 基板の接続方法
AU6015596A (en) * 1995-06-13 1997-01-09 Hitachi Chemical Company, Ltd. Semiconductor device, wiring board for mounting semiconducto r and method of production of semiconductor device
US5917242A (en) * 1996-05-20 1999-06-29 Micron Technology, Inc. Combination of semiconductor interconnect
US5677567A (en) * 1996-06-17 1997-10-14 Micron Technology, Inc. Leads between chips assembly
EP0951064A4 (en) 1996-12-24 2005-02-23 Nitto Denko Corp PREPARATION OF A SEMICONDUCTOR DEVICE
JP3660175B2 (ja) * 1998-11-25 2005-06-15 セイコーエプソン株式会社 実装構造体及び液晶装置の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102053395B (zh) * 2009-10-28 2013-05-01 财团法人工业技术研究院 凸块结构、芯片封装结构及该凸块结构的制备方法
CN103079343A (zh) * 2011-10-26 2013-05-01 日立化成工业株式会社 电路零件

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