CN101872754B - 焊线接合结构、强化焊线接合的方法及半导体封装构造的制造方法 - Google Patents

焊线接合结构、强化焊线接合的方法及半导体封装构造的制造方法 Download PDF

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CN101872754B
CN101872754B CN2009101370452A CN200910137045A CN101872754B CN 101872754 B CN101872754 B CN 101872754B CN 2009101370452 A CN2009101370452 A CN 2009101370452A CN 200910137045 A CN200910137045 A CN 200910137045A CN 101872754 B CN101872754 B CN 101872754B
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conductive adhesive
adhesive material
wire
connection pad
bonding wire
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CN101872754A (zh
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张效铨
蔡宗岳
赖逸少
唐和明
陈建成
易维绮
洪常瀛
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Advanced Semiconductor Engineering Inc
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Abstract

一种焊线接合结构包含一焊线、一接垫及一非导电胶材。该焊线包含一线状部及一块状部，其中该块状部连接于该线状部，且该块状部的剖面面积大于该线状部的剖面面积。该接垫接合于该块状部。该非导电胶材覆盖该接垫，并包覆该焊线的整个块状部。

Description

焊线接合结构、强化焊线接合的方法及半导体封装构造的制造方法
技术领域
本发明有关于一种强化焊线接合的方法，更特别有关于一种焊线接合结构，其非导电胶材覆盖铝制接垫并包覆该铜制焊线。
背景技术
参考图1，在半导体封装构造工艺中，焊线接合方法的技术广泛地将焊线14应用于芯片10的接垫11与基板12的接垫13间的电性连接。打线接合工艺是以金线为主，但铜线具有低成本的优势。相较于金，铜具有较佳的导电性及导热性，可使铜制焊线的线径较细及散热效率较佳。然而，铜具有延性不足及易氧化的缺点，使铜制焊线在应用上仍有所限制。
目前，铜制焊线只能应用在大尺寸的芯片接垫或低介电值材料(low-K)晶圆的芯片接垫，其原因在于铜制焊线接合工艺的成功将取决于芯片接垫的结构强度。为了避免铜制焊线接合工艺的失败，小尺寸芯片接垫将被限制。
参考图2至4，其显示已知铜制焊线接合方法。参考图2，经由一打线机，提供一铜制焊线20，其包含一铜线22及一铜球24。该铜球24是利用放电的方法或氢焰烧结成球而连接于该铜线22的一端。参考图3，将该铜球24施压而变形。参考图4，经由一振动工艺，将该铜球24接合于一铝制接垫32。然而，先前技术未揭示新增一黏力，用以强化铜制焊线与铝制接垫之间的接合效果。
美国专利第7,115,446B2号，标题为“用以加强黏力在覆晶封装工艺及内建金属层结构的基板的覆晶接合方法(Flip chip bonding method for enhancingadhesion force in flip chip packaging process and metal layer-builtstructure of substrate for the same)”，揭示一种覆晶接合方法及基板结构，可经由形成凸块54在芯片50的接垫51或基板52的接垫53上，以加强该芯片50与基板52之间的接合效果。
参考图5，虽然美国专利第7,115,446B2号所揭示的黏层56可加强覆晶接合工艺的黏力，但是该黏层56并未应用于焊线接合工艺。再者，该黏层56并未包覆整个凸块54，因此无法产生模锁效果。
因此，便有需要提供一种强化焊线接合的方法，能够解决前述的问题。
发明内容
本发明提供一种焊线接合结构，包含一焊线、一接垫及一非导电胶材。该焊线包含一线状部及一块状部，其中该块状部连接于该线状部，且该块状部的剖面面积大于该线状部的剖面面积。该接垫接合于该块状部。该非导电胶材覆盖该接垫，并包覆该焊线的整个块状部。
根据本发明的上述焊线接合结构，该非导电胶材覆盖该铝制接垫并包覆该铜制焊线，因此可强化铜制焊线与铝制接垫之间的接合效果。再者，根据本发明的上述焊线接合结构，该非导电胶材包覆该铜制焊线的整个块状部，因此可产生模锁效果。另外，该非导电胶材覆盖该铝制接垫并包覆该铜制焊线，因此可具有防氧化及防漏电效果，且使该些铝制接垫之间达到微间距(fine pitch)。
为了让本发明的上述和其它目的、特征、和优点能更明显，下文将配合所附图标，作详细说明如下。
附图说明
图1为先前技术的焊线接合方法的剖面示意图。
图2至4为先前技术的铜制焊线接合方法的剖面示意图。
图5为先前技术的覆晶接合方法的剖面示意图。
图6至16为本发明的第一实施例的半导体封装构造的制造方法的剖面示意图。
图17及18为本发明的第二实施例的半导体封装构造的制造方法中的强化焊线接合的方法的剖面示意图。
主要组件符号说明：
10芯片    11接垫
12基板    13接垫
14焊线
20焊线    22铜线
24铜球    32接垫
50芯片        51接垫
52基板        53接垫
54凸块        56黏胶
100晶圆
102打线机     104黏胶
106载板       107接垫
110芯片       112保护层
120焊线       122线状部
124块状部     125端
126端         132接垫
140胶材       140’胶材
具体实施方式
参考图6至17，其显示本发明的第一实施例的半导体封装构造的制造方法。参考图6，提供一晶圆100，其定义有数个数组式排列的芯片110。参考图7，其显示该芯片的局部放大图。每一芯片110包含一保护层112及至少一接垫(诸如铝制接垫132)。该铝制接垫132电性连接于该芯片110的线路(图未示)。该保护层112覆盖该铝制接垫132，并裸露出一部分的该铝制接垫132。参考图8，将一非导电胶材140形成于该铝制接垫132上。该非导电胶材140的形成步骤可先经由一旋涂(spin coating)工艺，将该非导电胶材140(诸如黏胶)形成于该铝制接垫132上，然后再将该非导电胶材140由液态固化成半固态。或者，该非导电胶材140的形成步骤可先经由一网印(printing)工艺，将该非导电胶材140(诸如黏胶)形成于该铝制接垫132上，然后再将该非导电胶材140由液态固化成半固态。或者，该非导电胶材140的形成步骤可将具有半固态的该非导电胶材140(诸如胶带)直接配置于该铝制接垫132上。
参考图9，将该晶圆100切割成数个芯片110，如此以形成具有铝制接垫132及非导电胶材140的芯片110。参考图10，经由诸如黏胶104将该芯片110固定于一载板106上。该载板106可为基板或导线架。
参考图11a或11b，经由一打线机102，提供一焊线(诸如铜制焊线120)，其包含一线状部122及一块状部124，其中该块状部124连接于该线状部122的一端，且该块状部124的剖面面积大于该线状部122的剖面面积。该块状部124可为球形或非球形。
参考图12，将该铜制焊线120的整个块状部124插入该非导电胶材140中。参考图13，可经由一施压工艺，将该块状部124接触于该铝制接垫132，并施压而变形。参考图14，可经由一振动工艺，将该铜制焊线120的块状部124接合于该铝制接垫132，其中该非导电胶材140覆盖该铝制接垫132，并包覆该铜制焊线120的整个块状部124。参考图15，将该非导电胶材140由半固态固化成固态，如此以形成本发明的焊线接合结构及强化焊线接合的方法。
参考图16，该铜制焊线120的一端125电性连接于该铝制接垫132，该铜制焊线120的另一端126可电性连接于该载板106的接垫107，如此以完成本发明的半导体封装构造的制造方法。
根据本发明的上述焊线接合结构，该非导电胶材覆盖该铝制接垫并包覆该铜制焊线，因此可强化铜制焊线与铝制接垫之间的接合效果。再者，根据本发明的上述焊线接合结构，该非导电胶材包覆该铜制焊线的整个块状部，因此可产生模锁效果。另外，该非导电胶材覆盖该铝制接垫并包覆该铜制焊线，因此可具有防氧化及防漏电效果，且使该些铝制接垫之间达到微间距(fine pitch)。
参考图17及18，其显示本发明的第二实施例的半导体封装构造制造方法。该第二实施例的半导体封装构造制造方法大体上类似于该第一实施例的半导体封装构造制造方法，相同组件标示相同的标号。两者的不同处是在于第二实施例的半导体封装构造制造方法中的强化焊线接合的方法包含下列步骤：参考图17，先将该铜制焊线120的块状部124接合于该铝制接垫132。参考图18，然后再将一非导电胶材140’覆盖该铝制接垫132，并包覆该铝制接垫132的整个块状部124。最后，将该非导电胶材140’由液态固化成固态，如此以形成本发明的焊线接合结构。
根据本发明的上述焊线接合结构，该非导电胶材覆盖该接垫并包覆该铜制焊线，因此亦可强化铜制焊线与铝制接垫之间的接合效果。根据本发明的上述焊线接合结构，该非导电胶材包覆该铜制焊线的整个块状部，因此亦可产生模锁效果。另外，该非导电胶材覆盖该铝制接垫并包覆该铜制焊线，因此亦可具有防氧化及防漏电效果，且使该些铝制接垫之间达到微间距(fine pitch)。
虽然本发明已以前述实施例揭示，然其并非用以限定本发明，任何本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作各种的更动与修改。因此本发明的保护范围当视后附的权利要求书所界定者为准。

Claims (16)

1.一种焊线接合结构，包含：
一焊线，包含一线状部及一块状部，其中该块状部连接于该线状部，且该块状部的剖面面积大于该线状部的剖面面积；
一接垫，接合于该块状部；以及
一非导电胶材，覆盖该接垫，并包覆该焊线的整个块状部，
其中，该非导电胶材具有一厚度，该厚度小于该接垫与该焊线的最高部之间的距离。
2.依权利要求1所述的焊线接合结构，其中该块状部为球形或非球形中的一者。
3.依权利要求1所述的焊线接合结构，其中该焊线为铜制焊线。
4.依权利要求1所述的焊线接合结构，其中该接垫为铝所制。
5.一种强化焊线接合的方法，包含下列步骤：
提供一接垫；
将一非导电胶材形成于该接垫上；
提供一焊线，其包含一线状部及一块状部，其中该非球形块状部连接于该线状部，且该块状部的剖面面积大于该线状部的剖面面积；
将该焊线的整个块状部插入该非导电胶材中；
将该焊线的块状部接合于该接垫，其中该非导电胶材覆盖该接垫，并包覆该焊线的整个块状部；以及
将该非导电胶材固化，
其中，该非导电胶材具有一厚度，该厚度小于该接垫与该焊线的最高部之间的距离。
6.依权利要求5所述的强化焊线接合的方法，该非导电胶材的形成步骤包含下列步骤：
经由一旋涂(spin coating)工艺，将该非导电胶材形成于该接垫上。
7.依权利要求6所述的强化焊线接合的方法，该非导电胶材的形成步骤另包含下列步骤：
将该非导电胶材由液态固化成半固态。
8.依权利要求5所述的强化焊线接合的方法，该非导电胶材的形成步骤包含下列步骤：
经由一网印(printing)工艺，将该非导电胶材形成于该接垫上，并覆盖该接垫。
9.依权利要求8所述的强化焊线接合的方法，该非导电胶材的形成步骤另包含下列步骤：
将该非导电胶材由液态固化成半固态。
10.一种半导体封装构造的制造方法，包含下列步骤：
提供一晶圆，其定义有数个数组式排列的芯片，每一芯片包含至少一接垫；
将一非导电胶材形成于该接垫上；
将该晶圆切割成数个芯片；
将该芯片固定于一载板上；
提供一焊线，其包含一线状部及一块状部，其中该非球形块状部连接于该线状部，且该块状部的剖面面积大于该线状部的剖面面积；
将该焊线的整个块状部插入该非导电胶材中；
将该焊线的块状部接合于该接垫，其中该非导电胶材覆盖该接垫，并包覆该焊线的整个块状部；以及
将该非导电胶材由半固态固化成固态，
其中，该非导电胶材具有一厚度，该厚度小于该接垫与该焊线的最高部之间的距离。
11.依权利要求10所述的半导体封装构造的制造方法，该非导电胶材的形成步骤包含下列步骤：
经由一旋涂(spin coating)工艺，将该非导电胶材形成于该接垫上。
12.依权利要求11所述的半导体封装构造的制造方法，该非导电胶材的形成步骤另包含下列步骤：
将该非导电胶材由液态固化成半固态。
13.依权利要求10所述的半导体封装构造的制造方法，该非导电胶材的形成步骤包含下列步骤：
经由一网印(printing)工艺，将该非导电胶材形成于该接垫上，并覆盖该接垫。
14.依权利要求13所述的半导体封装构造的制造方法，该非导电胶材的形成步骤另包含下列步骤：
将该非导电胶材由液态固化成半固态。
15.一种强化焊线接合的方法，包含下列步骤：
提供一接垫；
提供一焊线，其包含一线状部及一块状部，其中该块状部连接于该线状部，且该块状部的剖面面积大于该线状部的剖面面积；
将该焊线的块状部接合于该接垫；
将一非导电胶材覆盖该接垫，并包覆该焊线的整个块状部；以及
将该非导电胶材固化，
其中，该非导电胶材具有一厚度，该厚度小于该接垫与该焊线的最高部之间的距离。
16.一种半导体封装构造的制造方法，包含下列步骤：
提供一晶圆，其定义有数个数组式排列的芯片，每一芯片包含至少一接垫；
将该晶圆切割成数个芯片；
将该芯片固定于一载板上；
提供一焊线，其包含一线状部及一块状部，其中该块状部连接于该线状部，且该块状部的剖面面积大于该线状部的剖面面积；
将该焊线的块状部接合于该接垫；
将一非导电胶材覆盖该接垫，并包覆该焊线的整个块状部；以及
将该非导电胶材由液态固化成固态，
其中，该非导电胶材具有一厚度，该厚度小于该接垫与该焊线的最高部之间的距离。
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US5318651A (en) * 1991-11-27 1994-06-07 Nec Corporation Method of bonding circuit boards
US6091140A (en) * 1998-10-23 2000-07-18 Texas Instruments Incorporated Thin chip-size integrated circuit package

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Publication number Priority date Publication date Assignee Title
US5318651A (en) * 1991-11-27 1994-06-07 Nec Corporation Method of bonding circuit boards
US6091140A (en) * 1998-10-23 2000-07-18 Texas Instruments Incorporated Thin chip-size integrated circuit package

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