CN1497690A - 电路装置的制造方法 - Google Patents

电路装置的制造方法 Download PDF

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CN1497690A
CN1497690A CNA031603327A CN03160332A CN1497690A CN 1497690 A CN1497690 A CN 1497690A CN A031603327 A CNA031603327 A CN A031603327A CN 03160332 A CN03160332 A CN 03160332A CN 1497690 A CN1497690 A CN 1497690A
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conducting film
layer
conductive wiring
circuit arrangement
wiring layer
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CN1254859C (zh
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五十岚优助
水原秀树
坂本则明
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Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Abstract

一种电路装置的制造方法，目前开发了：以具有导电图案的挠性板为支承衬底、在其上安装半导体元件并进行整体模装的半导体装置。这种情况下，会产生不能形成多层配线结构的问题及制造工序中绝缘树脂板的挠曲明显的问题。本发明的电路装置的制造方法中，用设有具有斜面13S的开口部13的光致抗蚀剂层PR覆盖第一导电膜11和第二导电膜12层积而成的层积板10，在该开口部电解镀敷形成导电配线层14，形成反向倾斜面14R，然后，在用密封树脂层21进行覆盖时，将密封树脂层21咬入反向倾斜面14R，使其具有锚固效应，从而加强密封树脂层21和导电配线层14的结合。

Description

电路装置的制造方法
技术领域
本发明涉及电路装置的制造方法，特别是涉及使用了导电配线层的薄型电路装置的制造方法，其中所述导电配线层在具有锚固效应的周边具有反向倾斜面。
背景技术
近年来，IC组件在移动设备或小型高密度安装设备的采用正在发展，以往的IC组件及其安装概念正在发生很大的变化。例如特开2000-133678号公报所公开的。其是有关作为绝缘树脂板的一例采用挠性板即聚酰亚胺树脂板的半导体装置的技术。
图10～图12是将挠性板50用作插入式选择(インタ-ポ-ザ)衬底的图。另外，各图中上面的图为平面图，下面的图为A-A线剖面图。
首先，在图10所示的挠性板50之上面通过粘接剂粘合铜箔图案51备用。该铜箔图案51根据安装的半导体元件为晶体管、IC其图案不同，但是，通常形成有焊盘51A和岛51B。符号52是用于将电极自挠性板50的背面取出的开口部，所述铜箔图案51露出。
然后，该挠性板50被输送到装片机，如图11所示，安装半导体元件53。之后，该挠性板50被搬运到引线接合器，用金属配线54电连接焊盘51A和半导体元件53的焊盘。
最后，如图12(A)所示，在挠性板50的表面上设置密封树脂55进行密封。在此，进行传递模模装，覆盖焊盘51A、岛51B、半导体元件53和金属配线54。
之后，如图12(B)所示，设置焊锡或焊球等连接装置56，使其通过焊锡反射炉，经开口部52形成和焊盘51A熔接的球状焊锡56。而且，由于在挠性板50上半导体元件53矩阵状形成，故经如图12所示进行切割，而被一个个分离。
图12(C)所示的剖面图是在挠性板50的两面形成有作为电极的51A和51D的图。该挠性板50通常两面制图由厂家提供。
专利文献1：美国专利第5976912号说明书(第23栏第4行～第24栏第9行，图22a～图22g)。
发明内容
由于使用上述挠性板50的半导体装置不使用公知的金属框，故具有可实现极小型且薄型的封装结构的优点，但实质上仅由设在挠性板50表面的一层铜箔图案51进行配线。这由于挠性板很柔软，故在导电膜的图案形成前后会产生变形，层积的层间位置偏移大，存在不适于多层配线结构的问题。
为了抑制板的变形，要提高支承强度，为此，需要使挠性板足够厚，约为200μm，这有违薄型化。
另外，在制造方法中，在所述制造装置例如装片机、引线接合器、传递模装置及反射炉中，挠性板50要被搬运安装在称作工作台或桌子的部分。
但是，当减薄作为挠性板50的基座的绝缘树脂的厚度使其为50μm左右时，形成在表面上的铜箔图案51的厚度也很薄为9～35μm，此时，如图13所示，会因挠曲等而使搬运性非常不好，或向所述工作台或桌子的安装性能很差。这可以考虑因绝缘树脂自身非常薄而导致的挠曲和铜箔图案51与绝缘树脂的热膨胀系数之差引起的挠曲。
开口部52的部分在模装时要自上方加压，故会作用使焊盘51A的周边向上挠曲的力，使焊盘51A的粘接性能恶化。
若构成挠性板50的树脂材料自身无挠性或为了提高导热型而混入填充物，则变硬。在该状态下，有时在由引线接合器进行接合时会在接合部产生裂纹。在传递模模装时，有时在模型接触的部分也会产生裂纹。如图13所示在存在挠曲时，这一点会更明显。
如上说明的挠性板50都是背面未形成电极的挠性板，但是如图12(C)所示，有时在挠性板50的背面也形成电极51D。此时，电极51D会与所述制造装置接触，或与该制造装置间的搬运装置的搬运面接触，故会损伤电极51D的背面。由于在带有该损伤的状态下直接构成电极，故存在因之后的加热等而在电极51D自身产生裂纹的问题或在向母板进行焊接时使焊剂浸润性降低的问题。
在进行传递模模装时，也会产生挠性板50及铜箔图案51与绝缘树脂的粘接性能变弱，不能实现充分密封结构的问题。
本发明的第一方面提供一种电路装置的制造方法，其特征在于，包括下述工序：准备层积了第一导电膜和覆盖该第一导电膜的一主面的第二导电膜的衬底；在所述第二导电膜上以所希望的图案并用具有向开口部倾斜的斜面的光致抗蚀剂层进行覆盖；在所述光致抗蚀剂层的开口部选择性形成导电配线层，并在该导电配线层周围形成反向倾斜面；将所述导电配线层作为掩模除去所述第二导电膜；将半导体元件固定在所述第一导电膜上，将所述半导体元件的电极和规定的所述导电配线层电连接；用密封树脂层覆盖所述半导体元件，用所述导电配线层的所述反向倾斜面使所述密封树脂层产生锚固效应；除去所述第一导电膜，使所述密封树脂层及位于所述导电配线层背面的所述第二导电膜露出。尤其是利用光致抗蚀剂层的开口部周围的斜面，在导电配线层的周围形成反向倾斜面，并使其具有密封树脂层的锚固效应这一点上具有特征。
本发明第二方面的特征在于，所述第二导电膜利用银电镀形成。
本发明第三方面的特征在于，所述光致抗蚀剂层显影后进行加热处理，在所述开口部形成倾斜面。
本发明第四方面的特征在于，作为所述光致抗蚀剂层使用正型光致抗蚀剂层，显影时利用图象分辨率的不良度在所述开口部形成倾斜面。
本发明第五方面的特征在于，所述导电配线层以所述第一导电膜为电极利用铜电镀形成于所述开口部。
本发明第六方面的特征在于，所述第二导电膜的蚀刻液为碘系溶液。
本发明第七方面的特征在于，蚀刻所述第一导电膜时剩余的所述第二导电膜及所述密封树脂层用作蚀刻的阻挡层。
本发明第八方面的特征在于，作为进行所述蚀刻的溶液使用包含氯化铜或氯化铁的溶液。
本发明第九方面的特征在于，将焊剂附着在剩余的所述第二导电膜上形成外部电极。
附图说明
图1是说明本发明电路装置制造方法的剖面图；
图2是说明本发明电路装置制造方法的剖面图；
图3是说明本发明电路装置制造方法的剖面图；
图4是说明本发明电路装置制造方法的剖面图；
图5是说明本发明电路装置制造方法的剖面图；
图6是说明本发明电路装置制造方法的剖面图；
图7是说明本发明电路装置制造方法的剖面图；
图8是说明本发明电路装置制造方法的剖面图；
图9是说明本发明电路装置制造方法的剖面图；
图10是说明现有半导体装置制造方法的图；
图11是说明现有半导体装置制造方法的图；
图12是说明现有半导体装置制造方法的图；
图13是说明现有挠性板的图。
具体实施方式
本发明的电路装置的制造方法包括下述工序：准备层积了第一导电膜11和覆盖该第一导电膜11的一主面的第二导电膜12的衬底10；在所述第二导电膜12上以所希望的图案并用具有向开口部13倾斜的斜面13S的光致抗蚀剂层PR进行覆盖；在所述光致抗蚀剂层PR的开口部13选择性形成导电配线层14，并在该导电配线层14周围形成反向倾斜面14R；将所述导电配线层14作为掩模除去所述第二导电膜12；将半导体元件17固定在所述第一导电膜11上，将所述半导体元件17的电极和规定的所述导电配线层14电连接；用密封树脂层21覆盖所述半导体元件17，用所述导电配线层14的所述反向倾斜面14R使所述密封树脂层21产生锚固效应；除去所述第一导电膜11，使所述密封树脂层21及位于所述导电配线层14背面的所述第二导电膜12露出。下面说明上述各工序。
如图1所示，本发明的第一工序是准备层积了第一导电膜11和覆盖该第一导电膜11的一主面的第二导电膜12的衬底10。
层积板10的表面实质上在整个区域形成第一导电膜11，在其表面上形成第二导电膜12。第一导电膜11理想的是由以铜为主材的材料或公知的引线架材料构成。第一导电膜11及第二导电膜12可由镀敷法、蒸镀法或溅射法形成，或粘贴由压延法或镀敷法形成的金属箔。另外，作为第一导电膜11也可以是铝、铁、铁镍合金及公知的引线架材料等。
第二导电膜12的材料采用不被除去第一导电膜11时使用的蚀刻液蚀刻的材料。另外，由于在第二导电膜12背面形成由焊锡等构成的外部电极24，故也要考虑外部电极24的粘接性能。具体地说，作为第二导电膜12的材料可采用金、银、钯构成的导电材料。
第一导电膜11的厚度由于要机械支承整体，故形成得较厚，其厚度是35～150μm左右。第二导电膜12在蚀刻第一导电膜11时起阻挡层的作用，其厚度是2～20μm左右。因此，通过较厚地形成第一导电膜11，可维持层积板10的平坦性，可提高后道工序的操作性。
另外，第一导电膜11由于要经过各个工序，故会产生损伤。但是由于第一导电膜11要在后道工序除去，故可防止作为成品的电路装置产生损伤。由于可维持平坦性并硬化密封树脂，故也可使封装的背面平坦，形成于层积板10背面的外部电极也可平整地配置。因此，可使安装衬底上的电极和层积板10背面的电极接触，可防止焊剂缺陷。
下面说明上述层积板10的具体制造方法。层积板10可通过电镀进行的层积或压延接合进行制造。在由电镀制造层积板10时，首先要准备第一导电膜11。然后，在第一导电膜11的背面设置电极，利用电镀法层积第二导电膜12。在利用压延制造层积板时，用压辊等施加压力接合准备成板状的第一导电膜11及第二导电膜12。
如图2所示，本发明的第二工序在于，在所述第二导电膜12上以所希望的图案并用具有向开口部13倾斜的斜面13S的光致抗蚀剂层PR进行覆盖；
在本工序中，如图1所示，在用光致抗蚀剂层PR覆盖第二导电膜12之上后，为按所希望的配线图案的形状形成开口部13，进行曝光显影，用显影液除去对应开口部13的部分的光致抗蚀剂层PR。
然后，如图2所示，在光致抗蚀剂层PR的开口部13形成斜面13S。第一种方法是将显影后的光致抗蚀剂层PR在120～180℃左右进行加热处理，形成向上方倾斜的斜面13S。第二种方法是作为光致抗蚀剂层PR使用正型光致抗蚀剂材料，这样，图象分辨率差，显影时形成向上方扩展倾斜的斜面13S。
如图3及图4所示，本发明的第三工序在于，在光致抗蚀剂层PR的开口部13选择性形成导电配线层14，并在该导电配线层14周围形成反向倾斜面14R；
以第一导电膜11为共用电极，在光致抗蚀剂层PR的开口部13选择性进行铜的电解镀敷，形成导电配线层14。此时，光致抗蚀剂层PR作为掩模起作用，在开口部13露出的第二导电膜12上以所希望的图案形成导电配线层14。该导电配线层14埋入光致抗蚀剂层PR的开口部13，形成约20μm的厚度，在导电配线层14的与光致抗蚀剂层PR接触的周边形成反向倾斜面14R，该反向倾斜面14R以与开口部13的斜面13S反向的倾斜形成。导电配线层14在此采用了铜，但也可以采用Au、Ag、Pd等。
然后，如图4所示，在导电配线层14上选择性形成由第三导电膜15构成的焊盘15A。导电配线层14除去形成焊盘的区域外由光致抗蚀剂层PR覆盖，并进行镍的底镀，然后，进行金或银的电解镀敷，形成焊盘15A。另外，此时，第一导电膜11的背面由光致抗蚀剂层PR或外敷树脂覆盖，防止形成焊盘。
如图5所示，本发明的第四工序在于，将导电配线层14作为掩模，除去第二导电膜12。
在本工序中，除去光致抗蚀剂层PR，将导电配线层14作为掩模，选择性除去第二导电膜12。这里使用的蚀刻液使用蚀刻第二导电膜12且不会蚀刻导电配线层14的蚀刻液。也就是说，在导电配线层14主要由铜形成且第二导电膜12是银的情况下，可通过使用碘系蚀刻液仅除去第二导电膜12。另外，由于在由银形成焊盘15A的情况下，会被该蚀刻除去，故需要由光致抗蚀剂层(未图示)覆盖进行保护。
在此剩余的第二导电膜12用作外部电极24。
如图6所示，本发明的第五工序在于，将半导体元件17固定在第一导电膜11上，将半导体元件17的电极和规定的导电配线层14电连接。
半导体元件17以裸片状态由绝缘粘接层18接合在第一导电膜11上。
半导体元件17的各电极焊盘用接合引线19与设于周边的导电配线层14的规定部位设置的焊盘15A连接。半导体元件17也可以面朝下安装。这种情况下，要在半导体元件17的各电极焊盘表面设置焊球或补片，在层积板10的表面，在与焊球位置对应的部分设置与由导电配线层14构成的焊盘同样的电极。
下面说明进行引线接合时使用层积板10的优点。通常，在进行金线的引线接合时，要加热到200℃～300℃。此时，若第一导电膜11很薄，层积板10就会挠曲，当在该状态下，通过焊接头对层积板10加压时，就有可能使层积板10损伤。但是，通过较厚地形成第一导电膜11自身，可以解决这些问题。
如图7所示，本发明的第六工序在于，用密封树脂层21覆盖半导体元件17，并由导电配线层14的反向倾斜面14R在密封树脂层21产生锚固效应。
层积板10被设置在模装装置上进行树脂模装。模装方法可使用传递模模装、注射模模装、涂敷、罐封等进行。但是考虑到批量生产，则适用传递模模装、注射模模装。
在本工序中具有下述优点，在用密封树脂层21进行模装时，要将密封树脂层21填充到形成于第一导电膜11表面的导电配线层14的反向倾斜面14R，密封树脂层21和导电配线层14的结合因锚固效应而更牢固。
在本工序中，层积板10必须平整地接触模腔的下模，厚的第一导电膜11起该作用。而且，自模腔取出后，直至密封树脂层21的收缩结束，也会由第一导电膜11维持封装的平坦性。也就是说，本工序之前层积板10的机械支承作用由第一导电膜11承担。
如图8所示，本发明的第七工序在于，除去第一导电膜11使密封树脂层21及位于导电配线层14背面的第二导电膜12露出。
在本工序中，通过不用掩模进行蚀刻，将第一导电膜11整面除去。该蚀刻可以是使用氯化铁或氯化铜的化学蚀刻，第一导电膜11被整面除去。这样，整面除去第一导电膜11而剩余的第二导电膜12自密封树脂层21露出。如上所述，第二导电膜12由在蚀刻第一导电膜11的溶液中不被蚀刻的材料形成，故在本工序中第二导电膜12不被蚀刻。
本工序的特征在于，在通过蚀刻除去第一导电膜11时，即使不用掩模密封树脂层21及第二导电膜12也会作为阻挡层起作用，并使密封树脂层21及第二导电膜12构成的背面平坦地形成。第一导电膜11由于通过蚀刻被整面除去，故在蚀刻的最终阶段，第二导电膜12也会接触蚀刻液。如上所述，第二导电膜12由下述材料构成，这种材料是不会被蚀刻由铜构成的第一导电膜11的氯化铁及氯化铜蚀刻的材料。因此，在第二导电膜12的下面蚀刻停止，故第二导电膜12具有作为蚀刻的阻挡层的功能。另外，在本工序之后，整体由密封树脂层21机械支承。
如图9所示，本发明的最终工序在于形成接合面栅阵列(Land Grid Arrey)结构或焊球阵列(Ball Grid Arrey)结构。
在接合面栅阵列结构的情况下，自整面除去第一导电膜11的前工序起，除去形成外部电极24的部分用外敷树脂23覆盖第二导电膜12，切割密封树脂层21及外敷树脂23，将它们分离为一个个电路装置。
在焊球阵列结构的情况下，第二导电膜12使形成外部电极24的部分露出，对由溶剂溶解的环氧树脂等进行网印，用外敷树脂23覆盖大部分。然后，利用乳酪焊剂的网印及焊剂的回流在该露出部分形成突出的外部电极24B。接着，在层积板10矩阵状形成多个电路装置，切割密封树脂层21及外敷树脂层23，将它们分离为一个个电路装置。
在本工序中，由于可通过切割密封树脂层21及外敷树脂层23，分离为一个个电路装置，故可减少进行切割的切割机的磨损。
根据本发明，在形成导电配线层的工序中，利用光致抗蚀剂层的斜面，在导电配线层形成反向倾斜面，可加强导电配线层和密封树脂层的锚固效应，加强密封树脂层和导电配线层的咬合，具有可实现良好密封状态的优点。
通过以导电配线层为掩模超量蚀刻第二导电膜，可自调节形成凹入第二导电膜周围的锚固部，并在其后由密封树脂层覆盖时，充填该锚固部，故具有可使密封树脂层和导电图案层的咬合更加牢固的优点。
并且，第二导电膜在整面除去第一导电膜时与密封树脂层一起作为蚀刻阻挡层起作用，故具有可无掩模地除去第一导电膜的优点。
另外，由于第二导电膜和密封树脂层形成平坦的背面，故无论接合面栅阵列结构还是焊球阵列结构均可采用，具有剩余的第三导电膜自身可构成外部电极的全部或局部的结构的优点。

Claims (9)

1、一种电路装置的制造方法，其特征在于，包括下述工序：准备层积了第一导电膜和覆盖该第一导电膜的一主面的第二导电膜的衬底；在所述第二导电膜上以所希望的图案并用具有向开口部倾斜的斜面的光致抗蚀剂层进行覆盖；在所述光致抗蚀剂层的开口部选择性形成导电配线层，并在该导电配线层周围形成反向倾斜面；将所述导电配线层作为掩模除去所述第二导电膜；将半导体元件固定在所述第一导电膜上，将所述半导体元件的电极和规定的所述导电配线层电连接；用密封树脂层覆盖所述半导体元件，用所述导电配线层的所述反向倾斜面使所述密封树脂层产生锚固效应；除去所述第一导电膜，使所述密封树脂层及位于所述导电配线层背面的所述第二导电膜露出。
2、如权利要求1所述的电路装置的制造方法，其特征在于，所述第二导电膜利用银电镀形成。
3、如权利要求1所述的电路装置的制造方法，其特征在于，所述光致抗蚀剂层显影后进行加热处理，在所述开口部形成倾斜面。
4、如权利要求1所述的电路装置的制造方法，其特征在于，作为所述光致抗蚀剂层使用正型光致抗蚀剂层，显影时利用图象分辨率的不良度在所述开口部形成倾斜面。
5、如权利要求1所述的电路装置的制造方法，其特征在于，所述导电配线层以所述第一导电膜为电极利用铜电镀形成于所述开口部。
6、如权利要求1所述的电路装置的制造方法，其特征在于，所述第二导电膜的蚀刻液为碘系溶液。
7、如权利要求1所述的电路装置的制造方法，其特征在于，蚀刻所述第一导电膜时剩余的所述第二导电膜及所述密封树脂层用作蚀刻的阻挡层。
8、如权利要求6所述的电路装置的制造方法，其特征在于，作为进行所述蚀刻的溶液使用包含氯化铜或氯化铁的溶液。
9、如权利要求1所述的电路装置的制造方法，其特征在于，将焊剂附着在剩余的所述第二导电膜上形成外部电极。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102356462A (zh) * 2009-03-17 2012-02-15 凸版印刷株式会社 半导体元件用基板的制造方法及半导体器件
CN104157583A (zh) * 2014-08-28 2014-11-19 山东华芯半导体有限公司 一种芯片封装方法及模具
CN105190870A (zh) * 2013-03-19 2015-12-23 友立材料株式会社 半导体元件搭载用基板的制造方法
CN111785705A (zh) * 2016-10-25 2020-10-16 Tdk株式会社 电子部件模块及其制造方法

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004119727A (ja) * 2002-09-26 2004-04-15 Sanyo Electric Co Ltd 回路装置の製造方法
JP2004119729A (ja) * 2002-09-26 2004-04-15 Sanyo Electric Co Ltd 回路装置の製造方法
JP2004119726A (ja) * 2002-09-26 2004-04-15 Sanyo Electric Co Ltd 回路装置の製造方法
JP4086607B2 (ja) 2002-09-26 2008-05-14 三洋電機株式会社 回路装置の製造方法
JP4115228B2 (ja) * 2002-09-27 2008-07-09 三洋電機株式会社 回路装置の製造方法
US6992376B2 (en) * 2003-07-17 2006-01-31 Intel Corporation Electronic package having a folded package substrate
JP3886513B2 (ja) * 2004-02-02 2007-02-28 松下電器産業株式会社 フィルム基板およびその製造方法
FI117814B (fi) * 2004-06-15 2007-02-28 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi
US7358119B2 (en) * 2005-01-12 2008-04-15 Asat Ltd. Thin array plastic package without die attach pad and process for fabricating the same
FI119714B (fi) 2005-06-16 2009-02-13 Imbera Electronics Oy Piirilevyrakenne ja menetelmä piirilevyrakenteen valmistamiseksi
FI122128B (fi) * 2005-06-16 2011-08-31 Imbera Electronics Oy Menetelmä piirilevyrakenteen valmistamiseksi
US7556984B2 (en) * 2005-06-17 2009-07-07 Boardtek Electronics Corp. Package structure of chip and the package method thereof
US20070216033A1 (en) * 2006-03-20 2007-09-20 Corisis David J Carrierless chip package for integrated circuit devices, and methods of making same
US8051557B2 (en) * 2006-03-31 2011-11-08 Princo Corp. Substrate with multi-layer interconnection structure and method of manufacturing the same
JP5629969B2 (ja) 2008-09-29 2014-11-26 凸版印刷株式会社 リードフレーム型基板の製造方法と半導体装置の製造方法
US7830024B2 (en) * 2008-10-02 2010-11-09 Advanced Semiconductor Engineering, Inc. Package and fabricating method thereof
JP4811520B2 (ja) * 2009-02-20 2011-11-09 住友金属鉱山株式会社 半導体装置用基板の製造方法、半導体装置の製造方法、半導体装置用基板及び半導体装置
US9177832B2 (en) * 2011-09-16 2015-11-03 Stats Chippac, Ltd. Semiconductor device and method of forming a reconfigured stackable wafer level package with vertical interconnect
CN104283524B (zh) * 2014-10-22 2017-07-14 应达利电子股份有限公司 一种压电石英晶体谐振器及其制作方法
JP6524533B2 (ja) * 2016-02-25 2019-06-05 大口マテリアル株式会社 半導体素子搭載用基板、半導体装置及び光半導体装置、並びにそれらの製造方法
JP6615654B2 (ja) * 2016-03-14 2019-12-04 大口マテリアル株式会社 半導体素子搭載用基板、半導体装置、半導体素子搭載用基板の製造方法、及び半導体装置の製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5258649A (en) * 1989-05-20 1993-11-02 Hitachi, Ltd. Semiconductor device and electronic apparatus using semiconductor device
US5135606A (en) * 1989-12-08 1992-08-04 Canon Kabushiki Kaisha Process for preparing electrical connecting member
EP2287897A3 (en) * 1996-05-27 2011-11-02 Dai Nippon Printing Co., Ltd. Circuit member for semiconductor device, semiconductor device using the same, and process for producing said circuit member and said semiconductor device
JP2004119729A (ja) 2002-09-26 2004-04-15 Sanyo Electric Co Ltd 回路装置の製造方法
JP2004119727A (ja) 2002-09-26 2004-04-15 Sanyo Electric Co Ltd 回路装置の製造方法
JP4086607B2 (ja) 2002-09-26 2008-05-14 三洋電機株式会社 回路装置の製造方法
JP2004119726A (ja) 2002-09-26 2004-04-15 Sanyo Electric Co Ltd 回路装置の製造方法
JP4115228B2 (ja) 2002-09-27 2008-07-09 三洋電機株式会社 回路装置の製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102356462A (zh) * 2009-03-17 2012-02-15 凸版印刷株式会社 半导体元件用基板的制造方法及半导体器件
CN105190870A (zh) * 2013-03-19 2015-12-23 友立材料株式会社 半导体元件搭载用基板的制造方法
CN105190870B (zh) * 2013-03-19 2018-02-27 友立材料株式会社 半导体元件搭载用基板的制造方法
CN104157583A (zh) * 2014-08-28 2014-11-19 山东华芯半导体有限公司 一种芯片封装方法及模具
CN104157583B (zh) * 2014-08-28 2017-01-25 山东华芯半导体有限公司 一种芯片封装方法及模具
CN111785705A (zh) * 2016-10-25 2020-10-16 Tdk株式会社 电子部件模块及其制造方法

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