CN1489209A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN1489209A
CN1489209A CNA031424732A CN03142473A CN1489209A CN 1489209 A CN1489209 A CN 1489209A CN A031424732 A CNA031424732 A CN A031424732A CN 03142473 A CN03142473 A CN 03142473A CN 1489209 A CN1489209 A CN 1489209A
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China
Prior art keywords
pad
options
semiconductor device
conductor
protection film
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Pending
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CNA031424732A
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English (en)
Inventor
柴田润
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Publication of CN1489209A publication Critical patent/CN1489209A/zh
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Abstract

本发明目的在于，防止在用选项设定焊盘的电压来设定功能与状态(以下称为选项)的半导体装置的选项设定时，层间膜的裂纹或焊盘剥离。本发明的半导体装置的半导体基片的主面上设有选项设定部分10，其中，用以设定半导体装置的选项的、其外周边缘部分被表面保护膜11a覆盖的选项设定焊盘5C和用以供给固定电位的、其外周边缘部分被保护绝缘膜11a覆盖的固定电位焊盘5D，隔着表面保护膜11b相邻接。半导体装置的选项设定，通过是否设置覆盖选项设定焊盘5C、固定电位焊盘5D以及表面保护膜11a、11b而形成的柱形凸起15加以实现。

Description

半导体装置
技术领域
本发明涉及一种设有多个功能与状态(以下称为选项)，并能用从外部供给的电压来设定这种选项的半导体装置。
背景技术
传统的半导体装置，从表面保护膜上形成的开口，露出以非电接触状态而接近布置的多个焊盘(pad)来构成选项设定部分，并将选项设定部分的焊盘之间通过柱形凸起(stud bump)是否短路来进行选项设定。例如日本专利文献特开2001-135794号公报(第1-4页，第1-3图)。
传统的半导体装置，由于在焊盘之间没有表面保护膜的层间绝缘膜上形成柱形凸起，在层间绝缘膜上发生裂纹而降低产品的可靠性的问题。并且，在焊盘相对的边上，由于焊盘表面上没有表面保护膜，在形成柱形凸起时，根据从柱形凸起切断导线时产生的张力，会发生焊盘剥离的问题。
发明内容
本发明克服了所述之问题，其目的在于：获得不易发生由选项设定而来的层间绝缘膜的裂纹或焊盘剥离等的半导体装置。
本发明第一方面的半导体装置中设有：半导体基片，在该半导体基片上设置的层间绝缘膜，在该层间绝缘膜上设置的、外周边缘部分被表面保护膜覆盖的固定电位焊盘，在所述层间绝缘膜上设置的、隔着表面保护膜跟所述固定电位焊盘相对的、外周边缘部分被表面保护膜覆盖的选项设定焊盘，以及在所述所有表面保护膜和所述固定电位焊盘和所述选项设定焊盘之上连续设置的导体。
并且，本发明第二方面的半导体装置中，固定电位焊盘或选项设定焊盘的至少一方的面积小于半导体基片主面上的其它焊盘的面积。
再有，本发明第三方面的半导体装置中，导体连接的表面保护膜跟半导体基片主面上的其它表面保护膜隔离。
而且，本发明第四方面的半导体装置中，其导体在两个以上的选项设定焊盘和固定电位焊盘上连续设置。
再有，本发明第五方面的半导体装置中，其固定电位焊盘和选项设定焊盘在两边以上相向配置。
并且，本发明第六方面的半导体装置中，设有间隔着表面保护膜对着固定电位焊盘和选项设定焊盘两方的、其外周边缘部分被表面保护膜覆盖的伪焊盘，导体在所述所有表面保护膜和所述固定电位焊盘和所述伪焊盘以及所述选项设定焊盘上连续连接。
再有，本发明第七方面的半导体装置，导体跟固定电位焊盘主面接触的面积和所述导体跟选项设定焊盘主面接触的面积不同。
又，本发明第八方面的半导体装置，导体由在固定电位焊盘或选项设定焊盘之一和与之相邻的表面保护膜上形成的第一导体和在所述第一导体上和所述另一焊盘上形成的第二导体构成。
再有，本发明第九方面的半导体装置，导体由在固定电位焊盘主面上形成的第三导体、在选项设定焊盘主面上形成的第四导体以及在所述第三导体和所述第四导体两方相接触而形成的第五导体构成。
并且，本发明第十方面的半导体装置中设有：半导体基片，在该半导体基片上设置的层间绝缘膜，在该层间绝缘膜上设置的、其一方隔着表面保护膜设于另一方的主面内部、且另一方的外周边缘部分为表面保护膜所覆盖的固定电位焊盘和选项设定焊盘，以及在该选项设定焊盘和所述固定电位焊盘上连续设置的导体。
附图说明
图1是截去依据本发明实施例1的半导体装置的密封树脂上半部分而表示的平面图。
图2是表示依据本发明实施例1的半导体装置的选项设定部分的平面图及其I-I剖视图。
图3是依据本发明实施例1的半导体装置的选项设定焊盘和内部电路的连接部分的示意图。
图4是表示依据本发明实施例2的半导体装置的选项设定部分的平面图及其II-II剖视图。
图5是依据本发明实施例2的半导体装置的选项设定焊盘和内部电路的连接部分的示意图。
图6是表示依据本发明实施例3的半导体装置的选项设定部分的平面图。
图7是表示依据本发明实施例4的半导体装置的选项设定部分的平面图及其III-III剖视图。
图8是表示依据本发明实施例4的另一半导体装置的选项设定部分的平面图及其IV-IV剖视图。
图9是表示依据本发明实施例5的半导体装置的选项设定部分的平面图。
图10是表示依据本发明实施例6的半导体装置的选项设定部分的平面图及其V-V剖视图。
图11是表示依据本发明实施例7的半导体装置的选项设定部分的平面图。
图12是表示依据本发明实施例7的另一半导体装置的选项设定部分的平面图。
图13是表示依据本发明实施例8的半导体装置的选项设定部分的平面图及其VI-VI剖视图。
图14是表示依据本发明实施例9的半导体装置的选项设定部分的平面图及其VII-VII剖视图。
图15是表示依据本发明实施例10的半导体装置的选项设定部分的平面图及其VIII-VIII剖视图。
图16是表示依据本发明实施例11的半导体装置的选项设定部分的平面图及其IX-IX剖视图。
图17是表示依据本发明实施例11的其它半导体装置的选项设定部分的平面图及其X-X剖视图。
[符号说明]
半导体装置      1；     半导体基片          2；
焊盘            5；     选项设定焊盘        5C；
固定电位焊盘    5D；    内部电路            8；
选项设定部分    10；    表面保护膜          11；
表面保护膜(焊盘外周边缘部分)                11a；
表面保护膜(焊盘之间)                        11b；
表面保护膜(选项设定部分以外)                11c；
焊盘开口部      14；     导体               15；
第一导体        15a；    第二导体           15b；
第三导体        15c；    第四导体           15d；
第五导体        15e；    伪焊盘             22
具体实施方式
[实施例1]
图1是截去依据本发明的实施例1的半导体装置的密封树脂上半部分而表示的平面图。图中，1是半导体装置；2是半导体基片；3是承载半导体基片2的芯片垫(die pad)；4是把半导体装置1跟外部装置(未图示)电连接的引线端子；5是进行半导体基片2的电源供给或信号输入输出的焊盘；6是电连接引线端子4和焊盘5的金属细线；7是用以保护半导体基片2或金属细线6等的密封树脂；8是实现半导体装置1的功能的内部电路；9是电连接焊盘5和内部电路8的内部布线；10是用以进行半导体装置1的选项设定的选项设定部分；15是电连接多个焊盘5的导体柱形凸起。再有，由于图1中的内部电路8、内部布线9、以及焊盘5的一部分在其它构成部件的下层，所以用虚线表示。
图2详细描述了选项设定部分10，其中，(a)是平面图，(b)是I-I剖视图。选项设定部分10中设有：输入选项设定用电压的选项设定焊盘5C和维持任意的一恒定电压的固定电位焊盘5D(以下的图中固定电位焊盘在电源电压时用5Da，在GND时用5Db来表示)，它们隔着表面保护膜11b(以下的图中位于焊盘之间的表面保护膜用11b表示)配置。13是用以隔离在半导体基片2上以层状形成的构成内部电路8的元件(来图示)或布线(未图示)的层间绝缘膜。另外，虽然图中没有特别描述，但也有在半导体基片2和层间绝缘膜13之间再形成内部布线9，且层间绝缘膜13形成为多个层状的情形。焊盘5，其表面外周边缘部分被表面保护膜11a(以下的图中覆盖焊盘外缘上部的表面保护膜用11a表示)所覆盖，没有被表面保护膜11a覆盖的部分成为其表面向外部露出的焊盘开口部14。另外，11c是覆盖选项设定部分10以外的半导体基片表面的表面保护膜。
图1的半导体装置1中，设于半导体装置1左边的选项设定部分10用来决定内部电路的工作频率，因此，将内部电路8设计成：在选项设定焊盘5C上供给电源电压时以100MHz工作、在选项设定焊盘5C成为开路状态时以120MHz工作。并且，设于半导体装置1下边的选项设定部分10是用来选择处理标准，因此，把内部电路8设计成：在选项设定焊盘5C上供给GND时按照标准A、在选项设定焊盘5C成为开路状态时按照标准B来进行输入数据的运算。
图3是图1所示的两个部位的选项设定部分10的选项设定焊盘5C和内部电路8的连接部分的示意图，图1中半导体装置1左边的选项设定部分10的选项设定焊盘5C，如图3(a)所示，经由电阻21下拉至GND，开关断开(无柱形凸起15)时内部电路8上供给GND，开关导通(有柱形凸起15)时内部电路8上供给电源电压。
另一方面，图1中半导体装置1下边的选项设定部分10的选项设定焊盘5C，如图3(b)所示，经由电阻21上拉至电源电压，开关断开(无柱形凸起15)时内部电路8被供给电源电压，开关导通(有柱形凸起15)时内部电路8被供给GND。
为了使半导体装置1以100MHz的工作速度且按照标准A来进行运算，形成柱形凸起15，使其覆盖：用现有的引线接合技术设定于电源电压的半导体装置1左边的选项设定部分10的固定电位焊盘5Da、覆盖固定电位5Da的外周边缘部分的表面保护膜11a、固定电位焊盘5Da和选项设定焊盘5C之间的表面保护膜11b、覆盖选项设定焊盘5C外周边缘部分的表面保护膜11a以及选项设定焊盘5C；也可以这样形成柱形凸起15，使其覆盖：在半导体装置1下方的选项设定部分10的设定为GND的固定电位焊盘5Db、覆盖固定电位焊盘5Db的外周边缘部分的表面保护膜11a、固定电位焊盘5Db和选项设定焊盘5C之间的表面保护膜11b、覆盖选项设定焊盘5C外周边缘部分的表面保护膜11a以及选项设定焊盘5C。另外，从用金属细线6连接的电源引线端子4Da(跟外部电源连接的引线端子)给固定电位焊盘5Da供给预定电压，从用内部布线9连接到内部电路8的GND布线(未图示)给固定电位焊盘5Db供给预定电压。这里，作为固定电位焊盘5D的电压供给方法，使用金属细线6，但是也可以将固定电位焊盘5D的电压供给全由内部布线9来进行，而取消用于固定电位焊盘的引线端子4D或用以跟引线端子4D连接的金属细线6。
本实施例1的半导体，由于将柱形凸起15形成于焊盘5之间的表面保护膜11b上，不易发生对表面保护膜11b下层的层间绝缘膜13的损伤。并且，实施例1的半导体装置1，由于焊盘的外围全边由表面保护膜11a所覆盖，从柱形凸起15切断导线(未图示)时的拉力也不易剥离焊盘5。
另外，实施例1的半导体装置中使用的柱形凸起15，可以以金或其它金属为材料，采用通常的引线结合法以一般的方法来形成。并且，也可以将镀膜形成的金属凸起、蒸镀形成的金属被膜、梁式引线以及导电树脂等作为导体使用来取代柱形凸起15。再有，实施例1的半导体装置1是引线端子型的封装件，但是可以是采用球形网格式阵列(ball grid array)或带载方式(tape-carrier type)的封装件。
[实施例2]
图4是依据本发明实施例2的半导体装置的选项设定部分10的平面图及其II-II剖视图，图5是依据本发明实施例2的半导体装置的选项设定焊盘5C和内部电路8的连接部分的示意图。另外，跟图1至图3所示的实施例1相同或相等的部分上标同一符号且省略其说明。选项设定部分10中设有：选项设定焊盘5C、设定于电源电压的固定电位焊盘5Da、设定于GND的固定电位焊盘5Db、位于焊盘5之间的表面保护膜11b。另外，这些选项设定焊盘5C、固定电位焊盘5Da、5Db的焊盘表面外周边缘部分，由表面保护膜11a加以覆盖。
选项设定焊盘5C和与之连接的内部电路8的构成为如图5所示，若选项设定焊盘5C通过柱形凸起15跟设定于电源电压的固定电位焊盘5Da连接，就向内部电路8供给电源电压，内部电路8进行对应于电源电压输入的操作。另一方面，若选项设定焊盘5C通过柱形凸起15跟设定于GND的固定电位焊盘5Db连接，就向内部电路8供给GND，内部电路8进行对应于GND输入的操作。
实施例1的半导体装置1的场合，如图1所示，具有可以用选项设定焊盘5C和一个固定电位焊盘5D来构成选项设定部分10的优点，但是，例如图3(a)所示，把选项设定焊盘5C和设定于电源电压的固定电位焊盘5Da通过柱形凸起15来连接的场合，电阻21上会有常时电流，因此存在增加耗电的问题。但是，实施例2的半导体装置的场合，如图5所示，把选项设定焊盘5C跟设定于电源电压的固定电位焊盘5Da或设定于GND的固定电位焊盘5Db连接，都不会有常时电流流过，耗电不会增加。
[实施例3]
图6是表示依据本发明实施例3的半导体装置的选项设定部分的平面图。实施例3的选项设定部10中设有：隔着表面保护膜11b而布置的三个选项设定焊盘5C、隔着表面保护膜11b对着这三个选项设定焊盘5C布置的设定为电源电压的固定电位焊盘5Da以及隔着表面保护膜11b对着这三个选项设定焊盘5C布置的设定为GND的固定电位焊盘5Db。另外，选项设定焊盘5C和固定电位焊盘5Da、5Db的焊盘表面外周边缘部分由表面保护膜11a加以覆盖。
该选项设定部分10中，为了将图中左边的选项设定焊盘5C设定为电源电压，形成柱形凸起15使跟图中左边的选项设定焊盘5C和设定为电源电压的固定电位焊盘5Da相连接；再有，为了将图中正中央和图中右边的选项设定焊盘5C设定为GND，形成另一柱形凸起15使图中正中央的选项设定焊盘5C、图中右边的选项设定焊盘5C以及设定为GND的固定电位焊盘5Db上连接。
实施例3的半导体装置1，由于在选项设定部分10上含有多个选项设定焊盘5C，能够进行多种选项设定。再有，实施例3的半导体装置1，由于多个选项设定焊盘5C成为跟同一的固定电位焊盘5D相连的结构，可减少固定电位焊盘数，可实现半导体基片2的小型化。并且，实施例3的半导体装置1中，可以由一个柱形凸起15来进行多个选项设定焊盘15C的电压设定，因此，能够以少的工时数来制造选项设定的半导体装置1。
[实施例4]
图7是依据本发明实施例4的半导体装置的选项设定部分10的平面图以及III-III剖视图。实施例4的半导体装置1中，使固定电位焊盘5D的面积小于其它焊盘的面积。如实施例1所描述，由于对固定电位焊盘5D的固定电压供给是由内部布线9来进行，固定电位焊盘5D的主面上，将不需要单独引线接合的面积，形成用以跟选项设定焊盘5C连接的柱形凸起的约一半的大小即可。因此，能够减小固定电位焊盘5D的焊盘面积，从而可以将半导体基片2小型化。
实施例4的半导体装置1中，使固定电位焊盘5D的面积小于其它焊盘的面积，但基于同样的理由也可使选项设定焊盘5C的面积小于其它焊盘的面积。再有，如图8所示，能够将选项设定焊盘5C或固定电位焊盘5D的面积均小于选项设定部分10以外的焊盘面积。
[实施例5]
图9是依据本发明实施例5的半导体装置的选项设定部分10的平面图，(a)是柱形凸起15形成之前，(b)是柱形凸起15形成之后。实施例5的半导体装置1中，使选项设定焊盘5C和固定电位焊盘5D相互在两条边以上地相对设置，如选项设定焊盘5C上设有凸部，固定电位焊盘5D上设有凹部，使它们相互嵌入而设置。另外，在选项设定焊盘5C、固定电位焊盘5D的焊盘表面外周边缘部分上覆盖表面保护膜11a。并且，在选项设定焊盘5C和固定电位焊盘5D之间有表面保护膜11b。
实施例5的半导体装置1中，由于采用选项设定焊盘5C和固定电位焊盘5D设有多个相对边的结构，对于形成柱形凸起15时位置偏移的余量就会增大，可以稳定地连接选项设定焊盘5C和固定电位焊盘5D。即，在图2所示的实施例1的半导体装置1的场合，若柱形凸起15在图中稍微偏左时柱形凸起15将不会与固定电位焊盘5D接触，但实施例5的半导体装置1的场合，如图9(b)所示，柱形凸起15在图中上下部分均与固定电位焊盘5D接触，因此，柱形凸起15即使稍有左右偏移也可以跟选项设定焊盘5C和固定电位焊盘5D接触。并且，即使上下偏移，柱形凸起15也可以跟固定电位焊盘5D的图中的上方或下方部分接触。
[实施例6]
图10是依据本发明实施例6的半导体装置的选项设定部分10的平面图以及V-V剖视图。图中，22是隔着表面保护膜11b跟选项设定焊盘5C和固定电位焊盘5D相邻的、由铝等和其它焊盘5相同材料形成的伪焊盘。另外，伪焊盘22的表面外周边缘部分被表面保护膜11a所覆盖。
这种半导体装置1的选项设定这样实现：形成柱形凸起15，使之连接在选项设定焊盘5C、在选项设定焊盘5C和伪焊盘22之间的表面保护膜11b、伪焊盘22、在伪焊盘22和固定电位焊盘5D之间的表面保护膜11b、固定电位焊盘5D以及为覆盖各焊盘表面外周边缘部分的表面保护膜11a上。
通过将选项设定部10设置成实施例6所示的结构，柱形凸起15能够跟选项设定焊盘5C的开口部14、固定电位焊盘5D的开口部14上增加的伪焊盘22的开口部14相连接，因此，增加焊盘5和柱形凸起15的接合强度，柱形凸起15的剥离不易发生。
[实施例7]
图11是依据本发明实施例7的半导体装置的选项设定部分10的平面图，23是从选项设定焊盘5C的焊盘开口部14到固定电位焊盘5D的焊盘开口部14的表面保护膜的沟，它是为了将其上部形成了柱形凸起15的表面保护膜(图中的11b以及11a上对着焊盘5的部分)跟表面保护膜的其它部分(图中的11c以及11a上不对着焊盘5的部分)相分离，用蚀刻法除去了覆盖焊盘5C、5D的表面保护膜11a的一部分和选项设定部分以外的表面保护膜11c的一部分而形成的。再有，沟23的底面露出焊盘5与层间绝缘膜13。
形成柱形凸起15时，柱形凸起15下面的表面保护膜11可能会因应力而受损伤，但通过设置沟23可以防止损害扩大到表面保护膜11整体的情形。
另外，实施例7中，把这种沟23形成于覆盖焊盘5的表面保护膜11a和选项设定部分10以外的表面保护膜11c上，但如图12所示，也可以在覆盖焊盘5的表面保护膜11a和焊盘5之间的表面保护膜11b上形成。并且，实施例7中，由蚀刻形成沟23，但也可以采用最初就不形成沟23部分的表面保护膜11的方法。
[实施例8]
图13是依据本发明实施例8的半导体装置的选项设定部分10的平面图及其VI-VI剖视图。实施例8的半导体装置中，使柱形凸起15和焊盘5以及表面保护膜11之间的接触面的中心偏向选项设定焊盘5C侧而形成柱形凸起15。依据这样的结构，比图13(a)中的柱形凸起15的上下方向的宽度较大的部分跟选项设定焊盘5C相连接，能够增大柱形凸起15和焊盘5之间的连接强度。还有，将柱形凸起15和焊盘5以及表面保护膜11等的接触面的中心偏向固定电位焊盘5D侧，也可以得到相同的效果。
[实施例9]
图14是依据本发明实施例9的半导体装置的选项设定部分10的平面图及其VII-VII剖视图。实施例9的半导体装置中，选项设定焊盘5C和固定电位焊盘5D的连接，用覆盖选项设定焊盘5C和选项设定焊盘5C与固定电位焊盘5D之间的表面保护膜11b而形成的柱形凸起15a，以及覆盖固定电位焊盘5D和柱形凸起15a而形成的柱形凸起15b加以实现。
通过将柱形凸起15设置成这样的结构，能够增加柱形凸起15和焊盘5的接触面积，因此，能够可靠地进行两者的连接。并且，相互间的柱形凸起15起到扩大导电部分的面积的作用，因此，也增大形成柱形凸起时的位置偏移余量。再有，实施例9中，先设置选项设定焊盘5C侧的柱形凸起15a之后，再设置固定电位焊盘5D侧的柱形凸起15b，但以相反的顺序进行也无妨。
[实施例10]
图15是依据本发明实施例10的半导体装置的选项设定部分10的平面图及其VIII-VIII剖视图。实施例10的半导体装置1中，选项设定焊盘5C和固定电位焊盘5D的连接，用选项设定焊盘5C上形成的柱形凸起15c、在固定电位焊盘5D上形成的柱形凸起15d以及为接触柱形凸起15c和柱形凸起15d而形成的柱形凸起15e来实现。通过将柱形凸起15设置成这种结构，能够减小形成柱形凸起15时焊盘5之间的表面保护膜11b所受的损伤。
[实施例11]
图16(a)是依据本发明的实施例11的半导体装置的选项设定部分10的平面图，(b)是形成柱形凸起15之前的IX-IX剖视图，(c)是形成柱形凸起15之后的IX-IX剖视图。实施例11的半导体装置1中，在选项设定焊盘5C的主面内部形成由表面保护膜11b隔离的固定电位焊盘5D。另外，内部的固定电位焊盘上，由内部布线9以及层间连接塞24来供给来自内部电路(未图示)的预定电压。并且，本实施例11的半导体装置1中，选项设定焊盘5C和固定电位焊盘5D之间的连接，用固定电位焊盘5D的整个面、固定电位焊盘5D和选项设定焊盘5C之间的表面保护膜11b的整个面以及为覆盖选项设定焊盘5C而形成的柱形凸起15加以实现。
将选项设定部分10设置成这种结构，在形成柱形凸起15时，表面保护膜11b所受的损害不致影响到选项设定部分10以外的表面保护膜(未图示)。并且，由于表面保护膜11b整个面被柱形凸起15所覆盖，即使表面保护膜11b受到损害，由于其表面由柱形凸起15所保护，也不易降低可靠性。
本实施例11中，在选项设定焊盘5C的主面内部形成用以隔离固定电位焊盘5D和焊盘5的表面保护摸11b，但也可以在固定电位焊盘5D的主面内部设置用以隔离选项设定焊盘5C和焊盘5的表面保护膜11b。并且，如图17所示，也可以在选项设定焊盘5C的内部设置多个固定电位焊盘5D。在将这种半导体装置1的选项设定焊盘5C设定为电源电压的场合，这样形成柱形凸起15，如图17(c)所示，将设定为电源电压的固定电位焊盘5Da整个面、用以分离固定电位焊盘5Da和选项设定焊盘5C的表面保护膜11b的整个面和选项设定焊盘5C加以覆盖；在将选项设定焊盘5C设定为GND的场合，这样形成柱形凸起15，将设定为GND的固定电位焊盘5Db整个面、用以分离固定电位焊盘5Db和选项设定焊盘5C的表面保护膜11b的整个面和选项设定焊盘5C加以覆盖。通过将选项设定焊盘10设置成这种结构，可以把选项设定焊盘5C设定为电源电压或GND。
[发明效果]
如上所述，本发明第一方面的半导体装置中设有：半导体基片，在该半导体基片上设置的层间绝缘膜，在该层间绝缘膜上设置的、且外周边缘部分被表面保护膜覆盖的固定电位焊盘，在所述层间绝缘膜上设置的、且隔着表面保护膜跟所述固定电位焊盘相对的外周边缘部分被表面保护膜覆盖的选项设定焊盘，以及在所述所有表面保护膜和所述固定电位焊盘和所述选项设定焊盘之上连续设置的导体，因此，在选项设定过程中不易产生层间绝缘膜裂纹或焊盘剥离。
并且，本发明第二方面的半导体装置中，固定电位焊盘或选项设定焊盘的至少一方的面积小于半导体基片主面上的其它焊盘的面积，因此，可以小型化半导体装置。
再有，本发明第三方面的半导体装置中，导体连接的表面保护膜跟半导体基片主面上的其它表面保护膜分离，因此，可防止表面保护膜的损伤的扩大。
而且，本发明第四方面的半导体装置的导体在两个以上的选项设定焊盘和固定电位焊盘上连续设置，因此，可减少制造工时数。
再有，本发明第五方面的半导体装置中，其固定电位焊盘和选项设定焊盘有两边以上相对，因此，可稳定地连接固定电位焊盘和选项设定焊盘。
并且，本发明第六方面的半导体装置中，设有在固定电位焊盘和选项设定焊盘的两方隔着表面保护膜相对的外周边缘部分由表面保护膜覆盖而构成的伪焊盘，导体在所述所有表面保护膜、所述固定电位焊盘、所述伪焊盘以及所述选项设定焊盘上连续连接，因此，能稳定地连接固定电位焊盘和选项设定焊盘。
再有，本发明第七方面的半导体装置中，导体跟固定电位焊盘主面接触的面积和所述导体跟选项设定焊盘主面接触的面积不同，因此，柱形凸起上宽度较大的部分跟一方的焊盘连接，能够增加柱形凸起和焊盘之间的连接强度。
又，本发明第八方面的半导体装置中，导体由在固定电位焊盘与选项设定焊盘之一和与之相邻的表面保护膜上形成的第一导体和在所述第一导体上与所述另一焊盘上形成的第二导体所构成，因此，能够稳定地连接固定电位焊盘和选项设定焊盘。
再有，本发明第九方面的半导体装置中，导体由在固定电位焊盘主面上形成的第三导体、在选项设定焊盘主面上形成的第四导体、以及在所述第三导体和所述第四导体两方相接触而形成的第五导体所构成，因此，可减少表面保护膜的损伤。
并且，本发明第十方面的半导体装置中设有：半导体基片，在该半导体基片上设置的层间绝缘膜，在该层间绝缘膜上设置的、同时其一方隔着该表面保护膜位于另一方的主面内部、且另一方的外周边缘部分被表面保护膜覆盖的固定电位焊盘和选项设定焊盘，以及跨越该选项设定焊盘和所述固定电位焊盘两方连续设置的导体；因此，表面保护膜的损伤不会扩大到其它表面保护膜上。

Claims (11)

1.一种半导体装置，其特征在于设有：半导体基片，在所述半导体基片上设置的层间绝缘膜，在所述层间绝缘膜上设置的、且其外周边缘部分被第一表面保护膜覆盖的第一焊盘，在所述层间绝缘膜上设置的、隔着第二表面保护膜跟所述第一焊盘相对的、其外周边缘部分被第三表面保护膜覆盖的第二焊盘，以及在所述第一焊盘、所述第一至第三表面保护膜和所述第二焊盘上连续设置的导体。
2.如权利要求1所述的半导体装置，其特征在于：所述第一焊盘为固定电位焊盘，所述第二焊盘为选项设定焊盘。
3.如权利要求1所述的半导体装置，其特征在于：还设有在所述半导体基片和所述层间绝缘膜之间形成的内部布线和设于所述层间绝缘膜上的、被连接金属细线的第三焊盘；所述第一焊盘跟内部布线连接，其面积小于所述第三焊盘的面积。
4.如权利要求1所述的半导体装置，其特征在于：所述第一至第三表面保护膜上，连接所述导体的部分被和其它部分相分离。
5.如权利要求2所述的半导体装置，其特征在于：所述导体还包含在其上连续设置的一个或一个以上的选项设定焊盘。
6.如权利要求1所述的半导体装置，其特征在于：所述第一焊盘和所述第二焊盘在两边或两边以上相对地配置。
7.如权利要求1所述的半导体装置，其特征在于：还包括在所述第一焊盘和所述第二焊盘之间形成的、其外周边缘部分被第四表面保护膜覆盖的伪焊盘，所述导体也在所述伪焊盘和所述第四表面保护膜上连续设置。
8.如权利要求1所述的半导体装置，其特征在于：所述导体跟所述第一焊盘的接触面积和所述导体跟所述第二焊盘的接触面积不同。
9.如权利要求1所述的半导体装置，其特征在于：所述导体由在所述第一焊盘和所述第一与第二表面保护膜上设置的第一导体，以及在所述第一导体、所述第二焊盘和所述第三表面保护膜上设置的第二导体构成。
10.如权利要求1所述的半导体装置，其特征在于：所述导体是由在所述第一焊盘上设置的第三导体，在所述第二焊盘上设置的第四导体，以及在所述第三导体和所述第四导体上设置的第五导体构成。
11.一种半导体装置，其特征在于设有：半导体基片，在所述半导体基片上设置的层间绝缘膜，在所述层间绝缘膜上设置的、其外周边缘部分由第五表面保护膜覆盖的第四焊盘，在所述第四焊盘内侧隔着第六表面保护膜设置的第五焊盘，以及在所述第四焊盘、所述第六表面保护膜和所述第五焊盘上连续设置的导体。
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