CN1433060A - 半导体器件的元件隔离膜的形成方法 - Google Patents

半导体器件的元件隔离膜的形成方法 Download PDF

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CN1433060A
CN1433060A CN02128190A CN02128190A CN1433060A CN 1433060 A CN1433060 A CN 1433060A CN 02128190 A CN02128190 A CN 02128190A CN 02128190 A CN02128190 A CN 02128190A CN 1433060 A CN1433060 A CN 1433060A
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shallow trench
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朴哲秀
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TONG-BOO ELECTRONICS Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H01L21/76235Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS

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Abstract

本发明提供一种半导体器件的元件隔离膜的形成方法。本发明特征在于包括:依次在硅衬底上形成衬垫氧化膜和衬垫氮化膜的步骤;在衬垫氮化膜上形成定义元件隔离区的感光膜图形的步骤;以感光膜图形作为掩膜,腐蚀所述衬垫氮化膜、衬垫氧化膜和衬底的规定部位以形成浅沟槽的步骤;以感光膜图形作为掩膜,在浅沟槽底面进行场注入工序以形成场停止注入膜的步骤;除去感光膜的步骤;洗净所述结构的浅沟槽内部的步骤;使浅沟槽的内部热生长以形成第1氧化膜的步骤;以及在所得结构上蒸镀第2氧化膜后,在第2氧化膜上进行化学机械研磨(CMP)工序以形成元件隔离膜的步骤。

Description

半导体器件的元件隔离膜的形成方法
技术领域
本发明涉及半导体器件的元件隔离膜的形成方法,更具体地说,涉及在浅沟槽隔离膜(Shallow Trench Isolation,以下称为“STI”)形成时,通过将沟槽深度减至1/3水准,以高浓度杂质离子(High dose)注入进行场停止注入(Field Stop Implant),使得STI干法腐蚀工序容易进行,而且使注入高浓度杂质离子的区域的场厚度与STI侧壁(sidewall)的氧化膜厚度相比长成最高5倍以上,从而减小由等离子体造成的硅损伤的半导体器件的元件隔离膜的形成方法。
背景技术
一般地说,在半导体技术进步的同时,正在进行半导体元件的高速化、高集成化,与此相随的是对于图形的微细化的必要性更加提高,图形尺寸也要求高密度化。这也适用于在半导体元件中占有大区域的元件隔离区。
作为现在的半导体器件的元件隔离膜,大部分利用硅的局部氧化(LOCOS:Locoal Oxidation of Silicon)的氧化膜。这种硅局部氧化方式的元件隔离膜通过有选择性地对衬底局部氧化获得。
但是,所述硅局部氧化方式的元件隔离膜,在其边缘部分产生鸟的嘴状的鸟嘴(BIRD’S BEAK),存在一边使元件隔离膜的面积增大,一边又产生泄漏电流的缺点。
因此,在现有提出有较小宽度、具有优良的元件隔离特性的STI(shallowtrench isolation)方式的元件隔离膜。参照图1说明现有的STI元件隔离膜的形成方法。
如图所示,在硅衬底1上依次形成起缓冲器作用的衬垫氧化膜2和抑制氧化的衬垫氮化膜3。之后,在衬垫氮化膜3上部形成用于使预定元件隔离区露出的抗蚀剂图形4。此时,为形成宽度窄的元件隔离膜,利用析像清晰度优良的DUV(deep ultra violet)光源形成抗蚀剂图形4。之后,以抗蚀剂图形4作为掩膜,将衬垫氮化膜3、衬垫氧化膜2及硅衬底1腐蚀到规定深度的程度,形成浅沟槽(ST)。在用公知方法除去抗蚀剂图形4后,在浅沟槽(ST)内埋置绝缘膜(未图示)。接着,用公知方法除去半导体衬底1表面上存在的衬垫氮化膜3和衬垫氧化膜2,完成STI元件隔离膜。
但是,利用现有的STI方式进行的元件隔离膜的形成方法虽然电气特性优秀,但由于沟槽深度(depth)深,进行干法腐蚀有负担多的作用。特别是在沟槽宽度(width)为0.10μm以下由高宽比(Aspect Ratio)的增加以及微负载效应(Micro-1oading Effect)的增加进行干法腐蚀时存在困难。此外,存在由于沟槽深度变深使干法腐蚀的高宽比(Aspect Ratio)增加带来隔离短路(Isolation Short)的问题。
发明内容
因此,本发明是为解决上述问题而提出的,其目的在于提供一种半导体器件的元件隔离膜的形成方法,该方法在STI形成时通过将沟槽深度减至1/3水准,以高浓度杂质离子(High dose)注入进行场停止注入(Field StopImplant),使场阈值电压提高,从而使得STI干法腐蚀工序顺利地进行,并由此使隔离(Isolation)效果最大。
此外,本发明的另一目的在于提供一种半导体器件的元件隔离膜的形成方法,该方法通过在STI形成时减小沟槽深度,使因STI侧壁和底部长时间暴露于等离子体中而产生的缺陷(defect)减少,从而可减小由单元产生的泄漏电流。
此外,本发明的再一目的在于提供一种半导体器件的元件隔离膜的形成方法,该方法在STI形成时通过将沟槽深度减至1/3水准,利用掺杂浓度差使以高浓度杂质离子(High dose)注入进行场停止注入(Field Stop Implant)的区域的场厚度与STI侧壁(sidewall)的氧化膜厚度相比最高长成5倍以上,从而可减小因等离子体造成的硅损伤,使沟槽深度增加而形成元件隔离膜。
用于实现上述目的的本发明的半导体器件的元件隔离膜的形成方法包括:
依次在硅衬底上形成衬垫氧化膜和衬垫氮化膜的步骤;在衬垫氮化膜上形成定义元件隔离区的感光膜图形的步骤;以感光膜图形作为掩膜,腐蚀所述衬垫氮化膜、衬垫氧化膜和衬底的规定部位以形成浅沟槽的步骤;以感光膜图形作为掩膜,在浅沟槽底面进行场注入工序以形成场停止注入膜的步骤;除去感光膜的步骤;洗净所述结构的浅沟槽内部的步骤;使浅沟槽的内部热生长以形成第1氧化膜的步骤;以及在所得结构上蒸镀第2氧化膜后,在第2氧化膜上进行化学机械研磨(CMP)工序以形成元件隔离膜的步骤。
最好将所述第1氧化膜形成为在所述浅沟槽底面的厚度与侧壁厚度相比为5-10倍。
最好进行场停止注入(Field Stop Implant)工序来形成所述第1氧化膜,所述场停止注入的浓度以1015atons/cm2以上的高浓度来实施。
最好所述第1氧化膜分开进行干法氧化工序和湿法氧化工序。
最好在进行所述场停止注入工序时以低浓度进行杂质离子注入,以便只使场阈值电压提高。
以上的本发明目的和其他特征及优点等通过下面参照本发明优选实施例的说明会变得明确。
附图说明
图1是用于说明现有的STI元件隔离膜形成方法的剖面图;
图2A到图2D是用于说明本发明STI元件隔离膜形成方法的剖面图。
具体实施方式
以下参照附图详细说明本发明的实施例。
另外,在用于说明实施例的全部图面中具有相同功能的部件使用相同符号,省略反复的说明。
图2A到图2D是用于说明本发明STI元件隔离膜形成方法的剖面图。
参照图2A,依次形成起缓冲器作用的第1衬垫氧化膜12和抑制氧化的衬垫氮化膜13。
接着,在衬垫氮化膜13上部形成用于使预定元件隔离区露出的抗蚀剂图形14。此时,为形成宽度窄的元件隔离膜,利用析像清晰度优良的DUV(deepultra violet)光源形成所述抗蚀剂图形膜14。之后,以所述抗蚀剂图形膜14作为掩膜,将所述衬垫氮化膜13、所述第1衬垫氧化膜12及所述硅衬底11腐蚀到规定深度的程度,形成浅沟槽(Shallow trench;ST)。
之后,通过在形成了所述浅沟槽(ST)的整个结构物上实施场停止注入(Field Stop Implant)15工序,在所述浅沟槽(ST)的底面形成场停止注入膜16。
之后,如图2B所示,用公知方法除去所述抗蚀剂图形膜14后,洗净所述浅沟槽(ST)的内部。
之后,如图2C所示,使所述浅沟槽(ST)的内部热生长,形成第2衬垫氧化膜17。
此时,通过以高浓度(High Doping)(>1015atons/cm2)实施场停止注入(Field Stop Implant)形成所述第2衬垫氧化膜17,以形成所述浅沟槽(ST)底面(bottem)的氧化膜厚度借助于掺杂剂(dopant)的浓度产生与侧壁(sidewall)氧化膜的厚度相比最高5倍以上的差。
此外,通过分开进行干法氧化工序和湿法氧化工序,所述第2衬垫氧化膜17在浅沟槽(ST)的上部边缘部分的圆形(rounding)大大改善。因此,可控制晶体管的峰值(hump)现象,可防止栅绝缘膜的变薄(thinning)现象。之后,在厚蒸镀第3衬垫氧化膜18,填充(gap fill)所述浅沟槽(ST)内部后,实施化学机械研磨(Chemical Mechanical Polishing:CMP)或整体蚀刻(BlanketEtchback)工序,使所述衬垫氮化膜13露出,如此将所述第2衬垫氧化膜18平坦化。
之后,如图2D所示,以高浓度的磷腐蚀剂(Hot Phosphoric Etchant)除去所述衬垫氮化膜13,完成元件隔离膜的制造工序。
另一方面,如果用图2C的场停止注入(Field Stop Implant)工序以低浓度注入杂质(dose),则本发明可以只使场阈值电压(Vt)提高。
综上所述,在利用本发明的半导体器件的元件隔离膜的形成方法时,由于在STI形成时将沟槽深度减至1/3水准,以高浓度的杂质离子注入进行场停止注入(Field Stop Implant)提高场阈值电压,因此可顺利地进行STI干法腐蚀工序,使隔离(Isolation)效果极大化。而且,通过以高浓度的杂质离子注入进行场停止注入(Field Stop Implant)的区域的场厚度与STI侧壁(sidewall)的氧化膜厚度相比最高长成5倍以上,可以减少因等离子体造成的硅损伤。
另外,通过减小STI形成时的沟槽深度,可减少自单元发生的泄漏电流。
同时,本发明的优选实施例是为例示的目的而公开的,本领域技术人员在本发明思想和范围内可进行各种修改、变更、添加等,应看出这样的修改变更等属于以下的权利要求的范围。

Claims (6)

1.一种半导体器件的元件隔离膜的形成方法,其特征在于,包括:
依次在硅衬底上形成衬垫氧化膜和衬垫氮化膜的步骤;
在所述衬垫氮化膜上形成定义元件隔离区的感光膜图形的步骤;
以所述感光膜图形作为掩膜,腐蚀所述衬垫氮化膜、衬垫氧化膜和衬底的规定部位以形成浅沟槽的步骤;
以所述感光膜图形作为掩膜,在所述浅沟槽的底面实施场注入工序以形成场停止注入膜的步骤;
除去所述感光膜的步骤;
洗净所述结构的浅沟槽内部的步骤;
使所述浅沟槽的内部热生长以形成第1氧化膜的步骤;以及
在所得结构上蒸镀第2氧化膜后,在所述第2氧化膜上进行化学机械研磨(CMP)工序以形成元件隔离膜的步骤。
2.如权利要求1所述的半导体器件的元件隔离膜的形成方法,其特征在于,将所述第1氧化膜形成为在所述浅沟槽底面的厚度与侧壁厚度相比为5-10倍。
3.如权利要求1所述的半导体器件的元件隔离膜的形成方法,其特征在于,进行场停止注入(Field Stop Implant)工序来形成所述第1氧化膜。
4.如权利要求3所述的半导体器件的元件隔离膜的形成方法,其特征在于,所述场停止注入的浓度以1015atons/cm2以上的高浓度来实施。
5.如权利要求2所述的半导体器件的元件隔离膜的形成方法,其特征在于,所述第1氧化膜分开进行干法氧化工序和湿法氧化工序。
6.如权利要求1所述的半导体器件的元件隔离膜的形成方法,其特征在于,在进行所述场停止注入工序时以低浓度进行杂质离子注入,以便只使场阈值电压提高。
CNB021281904A 2001-12-20 2002-12-20 半导体器件的元件隔离膜的形成方法 Expired - Fee Related CN1254865C (zh)

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CN113594085B (zh) * 2021-07-12 2023-10-03 长鑫存储技术有限公司 半导体结构的制作方法

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