CN1378703A - 用于电可擦可编程只读存储器的高温氧化物沉积方法 - Google Patents
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Abstract
一种于二位EEPROM装置(10)制造ONO浮动栅极电极(26)的方法,包括使用高温氧化物(HTO)沉积处理形成顶氧化物层(32),其中HTO处理是在700至约800℃温度利用LPCVD或RTCVD沉积处理器进行。该方法进一步包括使用原位LPCVD或RTCVD沉积处理循序形成一层氮化硅层(30)及一层顶氧化物层(32),其中于形成顶氧化物层(32)之前,氮化硅层(30)未暴露于周围气氛。使用HTO沉积处理形成顶氧化物层(32),经由减少ONO浮动栅极电极(26)的电荷泄漏而提供改进的二位EEPROM内存装置(10)。
Description
技术领域
本发明涉及制造半导体装置的方法，尤其涉及制造二位EEPROM装置的方法。
背景技术
非易失性内存装置目前广用于当电力中断时仍然需要保有信息的电子组件。非易失性内存装置包括只读存储器(ROM)，可编程只读存储器(PROM)，可擦可编程只读存储器(EPROM)以及电可擦可编程只读存储器(EEPROM)装置。EEPROM装置与其它非易失性内存装置的差异在于其可利用电力编程规划以及擦除。快闪EEPROM装置类似EEPROM装置在于内存单元可以电力编程规划以及擦除。但快闪EEPROM装置可使用单一电流脉冲而让装置内的全部内存单元被擦除。
典型EEPROM装置包括储存电荷的浮动栅极电极。浮动栅极电极覆于沟道区上，沟道区驻在半导体基片的源极区与漏极区间。浮动栅极电极连同源极区及漏极区形成加强式晶体管。经由储存电荷于浮动栅极电极，加强式晶体管的阈电压被调整至相对高值。相对地，当电荷由浮动栅极电极移开时，加强式晶体管的阈电压被调整至相对低值。加强式晶体管的阈电压值决定当晶体管藉施加适当电压至源极及漏极而被导通时流经晶体管的电流。当阈电压高时，无电流流经晶体管，定义为逻辑0态。相对地，当阈电压低时，电流将流经晶体管，且被定义为逻辑1态。
于快闪EEPROM装置，电子经由覆盖于加强式晶体管的沟道区上方的一层电介质层被转移至浮动栅极电极。电子的转移由热电子注入而引发或藉法勒诺海(Fowler-Nordheim)隧道效应而被引发。任一种电转移机构中，电压经由上方覆盖的控制栅极电极而施加至浮动栅极。控制栅极电极容性耦合至浮动栅极电极，因此施加于控制栅极电极的电压耦合至浮动栅极电极。快闪EEPROM装置经由施加高正电压的控制栅极电极以及低正电压的漏极区而编程规划，将电子由沟道区移转至浮动栅极电极。快闪EEPROM装置经由控制栅极电极接地，以及经由加强式晶体管的源极或漏极区施加高正电压而被擦除。于擦除电压条件下，电子由浮动栅极电极被去除且移转至半导体基片的源极或漏极区。
EEPROM装置技术的产品开发努力焦点集中在提高编程规划速度，降低编程规划及读取电压，提高资料保有时间，缩短单元擦除时间以及缩小单元维度。前述多项研究目标可经由发展浮动栅极电极的制造材料及制造方法而予解决。最近，发展的努力的焦点集中于制造浮动栅极电极的电介质材料。氮化硅组合二氧化硅已知可于加强式晶体管的控制栅极电极与沟道区间提供满意的电介质分隔，同时具有足够储存电荷的电力特征。
制造浮动栅极电极的一项重要电介质材料为氧化物-氮化物-氧化物(ONO)结构。编程规划期间，电荷由ONO结构的基片移转至氮化硅层。电压施加至栅极及漏极，形成垂直及横向电场，其加速电子顺着沟道长度方向移动速度。当电子沿沟道移动时部分电子获得足够能量可跳越底层二氧化硅层的电位障壁而变成被捕捉于氮化硅层。由于接近漏极的电场最强，故电子被捕捉于接近漏极区。反相施加于源极及漏极的电位将使电子于相反方向顺着沟道移动而变成注入接近源极区的氮化硅层。由于氮化硅不具导电性，故导入氮化硅层的电荷倾向于维持于局限化。如此依据施加的电压电位而定，电荷可储存于单一连续氮化硅层的多个分立区。
非易失性内存设计时利用电子储存于氮化硅层的局限化性质，已经设计出内存电路，其利用电荷储存于ONO层的两区。此种类型的非易失性内存装置称作为二位(two-bit)EEPROM。二位EEPROM可储存如同相等大小内存矩阵的已有EEPROM的信息量的两倍。一左一右位储存于氮化硅层的实体不同区，接近各内存单元的左区及右区。然后编程规划方法用以让二位同时进行编程规划及读取。内存单元的二位可经由施加适当擦除电压至栅极以及施加至源极或漏极区而个别擦除。
虽然最近EEPROM技术的进展已经可让内存设计时使用二位资料储存，而让EEPROM矩阵的内存容量加倍，但此种装置内部材料层的制造上仍然存在有多种挑战。特别ONO层必须小心制造以防形成于ONO层内部提供电荷泄漏路径的界面状态。如此ONO制造技术的进展为确保二位EEPROM装置使用的ONO结构的适当电隔离所需。
发明概述
本发明为一种于二位EEPROM装置制造ONO浮动栅极电极的方法。使用ONO浮动栅极电极制造二位EEPROM装置要求形成高品质ONO结构。原因在于二位EEPROM装置的适当发挥功能要求ONO结构内部的局限化电荷储存。特别顶氧化物层必须具有足够使电荷陷阱的形成减至最低的密度。电荷陷阱形成于顶氧化物层可能导致非期望的电荷泄漏于顶氧化物层，以及泄漏于顶氧化物层与下方氮化硅层间的界面。于适当形成的ONO结构中，全部电荷皆储存于氮化硅层。经由制造高品质顶氧化物层，ONO结构的储存电荷保持局限化于氮化硅层的预定区内部。
一种形式中，ONO浮动栅极电极的制法包括提供半导体基片，以及热生长第一氧化硅层于半导体基片上。然后氮化硅层形成于第一氧化硅层上。然后第二氧化硅层形成而覆盖于氮化硅层上，第二氧化硅层使用高温氧化物(HTO)沉积法形成。高温氧化物沉积法是在约700至约800℃的温度进行。
附图说明
图1以剖面图说明根据本发明制造的半导体基片的一部分，含有一浮动栅极晶体管其结合一ONO结构；以及
图2至4以剖面图说明根据本发明制造ONO结构的制程步骤。
需了解为求简化说明及清晰，附图显示各组件不必照比例绘制。例如部分组件的尺寸被相对于彼此夸大以求清晰。进一步若视为适当，各图中参考编号可重复指示对应的组件。
具体实施方式
图1以剖面图显示一种适合用于二位EEPROM装置的浮动栅极晶体管10。浮动栅极晶体管10包括源极/漏极区12及14位于半导体基片16且由一沟道区18隔开。第一及第二位线氧化物区20及22分别覆于源极/漏极区12及14上。控制栅极电极24覆盖于沟道区18上且由ONO结构26隔开。控制栅极电极24及ONO结构26形成堆栈栅极结构。
ONO结构26包括第一氧化硅层28覆于沟道区18上方。氮化硅层30覆于第一氧化硅层28上方。第二氧化硅层(或顶氧化物层)32覆于氮化硅层30上方。
浮动栅极晶体管10操作时，电压施于控制栅极电极24以及施于源极/漏极区12及14，造成电荷由源极/漏极区12及14传播跨沟道区1 8。一旦电荷遭遇够强的垂直电场，则电荷被注入或由沟道区18穿隧进入氮化硅层30。举例言之，依据施加于控制栅极电极24以及施加于源极/漏极区12及14的特殊电压位准而定，电荷34移转至氮化硅层30且局限于源极/漏极区12或源极/漏极区14附近。
业界人士了解二位EEPROM装置发挥适当功能必然要求电荷34保持隔离于其最初被导入的氮化硅层30该区。电荷34适当维持于氮化硅层30的局限区对二位EEPROM装置发挥适当性能具有关键重要性。特别ONO结构26品质必须可使第一及第二氧化硅层28及32与氮化硅层30间的界面处电荷泄漏减至最低。此外，第二氧化硅层32必须具有够高密度，因此于氧化硅材料内部的电荷陷阱数量减至最少。
根据本发明，ONO结构26内部的电荷泄漏经由形成高品质顶氧化物层而减至最低。藉本发明所得较低电荷泄漏以及改进浮动栅极晶体管性能经由根据本发明进行的ONO制造过程将更为明了。
参照图2，第一氮化硅层28形成而覆盖于半导体基片16表面上。较佳半导体基片16为单晶硅基片。半导体基片16具有先前经处理而去除碎屑(debris)及天然氧化物的上表面36。较佳第一氧化硅层28是在升高温度于干分子氧存在下藉热氧化表面36形成。较佳氧化过程是在约900至约1100℃温度进行。氧化处理形成氧化硅层，较佳具有厚度约50至约150埃，及更佳具有厚度约100埃。氧化处理可以批次型热氧化炉或另外于单一晶圆氧化装置进行。
形成第一氧化硅层28后，氮化硅层30形成而覆盖于第一氧化硅层28上，如图3说明。较佳氮化硅层30利用快速热化学气相沉积(RTCVD)方法形成。RTCVD方法是在约700至约800℃的温度进行。氮化硅材料经由氨(NH3)与二氯硅烷(SiCl2H2)或硅烷(SiH4)反应形成。该方法进行一段时间且于足够形成氮化硅层较佳具有厚度约50至约150埃，及更佳约100埃的气体流速进行。本发明的一具体实施例中，氨以约每分钟一标准升(slpm)的流速被导入RTCVD装置内，以及二氯硅烷或硅烷以约30至约50每分钟标准立方厘米(sccm)的流速被导入。RTCVD方法以三步骤进行，包括初步温度升高步骤、沉积步骤、冷却步骤。较佳基片16于RTCVD装置的总停驻时间约3分钟。较佳氮化硅层的步骤于约2分钟完成。
另外，氮化硅层30可利用低压化学气相沉积(LPCVD)方法形成。替代方法中，氮化硅可于批次沉积装置形成。LPCVD方法较佳是在约200至约6666.13kPa的压力于700至800℃温度使用氨气以及二氯硅烷或硅烷气体进行。
形成氮化硅层30后，第二氧化硅层32形成而覆盖于氮化硅层30上，如图4所示。根据本发明，第二氧化硅层32通过RTCVD或LPCVD方法形成。第二氧化硅层32使用氧化亚氮(N2O)以及二氯硅烷于RTCVD装置形成。RTCVD方法较佳是在约700至约800℃温度进行经历约3分钟的总处理时间。类似用以沉积氮化硅层30的RTCVD方法，使用三步骤沉积顺序包括温度升高步骤、沉积步骤及冷却步骤。于RTCVD装置的总处理时间约3分钟。较佳沉积步骤其间使用约1至约3slpm及更佳约2slpm氧化亚氮。此外使用约25至约75sccm及更佳约50sccm二氯硅烷。RTCVD方法形成氧化硅层具有较佳厚度约50至约150埃及更佳约100埃。LPCVD方法中，第二氧化物于批次型炉内于700至800℃温度沉积于氮化物上。
前述形成氮化硅层及顶氧化物层二者的RTCVD处理可有利地提供原位(in-situ)处理用以循序形成个别层于ONO结构。特别，以循序原位沉积顺序形成氮化硅层30及第二氧化硅层32可减少氮化硅/氧化硅界面的污染。此外，可减少无法控制的天然氧化作用，以确保单纯高密度氧化硅层沉积于氮化硅层30上。
本发明的主要特征方面包括于氮化硅层30未暴露于周围气氛的条件下，循序形成氮化硅层30及第二氧化硅层32。氮化硅层30沉积于第一氧化硅层28后，基片16是在真空条件下移送至氧化物沉积腔室内而基片未暴露于周围气氛。另外，晶圆移转过程中，可导入正压惰性气体气氛。原位氮化物及氧化物沉积反应可于批次型LPCVD系统进行。
业界人士了解存在有多种手段可确保氮化硅层30于第二氧化硅层32的沉积之前不会暴露于周围气氛。例如使用丛集/工具(cluster/tool)装置，其中半导体基片16是在连续真空环境下或正压惰性气体气氛下，由氮化物沉积腔室移转至氧化物沉积腔室。另外，氮化物沉积过程及氧化物沉积过程可于单一沉积腔室进行，该单一沉积腔室配置成可容纳各种处理气体。如此所有这些变化及修改意图皆涵盖于本发明的范围。
形成ONO结构26后，经由沉积一层栅极形成材料于第二氧化硅层32上而完成图1所示堆栈栅极结构。然后进行光刻术图案化以及蚀刻处理，以界定控制栅极电极34以及ONO浮动栅极电极。业界人士了解多种栅极形成材料可用于制造控制栅极电极24。例如控制栅极电极24可使用多晶硅、非晶硅、耐热金属硅化物等形成。
如此根据本发明揭示一种于一种二位EEPROM装置制造一种ONO浮动栅极电极的方法，其全然可提供前文说明的各项优点。虽然已经参照特定具体实施例说明本发明，但本发明绝非囿限于这些具体实施例。业界人士了解可未脱离本发明的精神而做出多种修改及变化。例如组成ONO结构的各层厚度可与此处揭示厚度不同。因此预期所有这些落入本发明权利要求范围及其相当范围的这些变化及修改皆含括于本发明。
Claims (10)
1.一种于一个二位EEPROM装置(10)制造一种ONO浮动栅极电极(26)的方法，包含下列步骤：
提供一半导体基片(16)；
热生长一层第一氧化硅层(28)覆盖于半导体基片(16)上；
形成一层氮化硅层(30)覆于第一氧化硅层(28)上；以及
使用高温氧化物沉积方法沉积一层第二氧化硅层(32)覆于氮化硅层(30)上，
其中高温氧化物沉积处理是在约700至约800℃的温度进行。
2.如权利要求1所述的方法，其中沉积第二氧化物层(32)的步骤包括使用氧化亚氮以及第二种选自硅烷及二氯硅烷组成的组群的气体进行低压化学气相沉积。
3.如权利要求2所述的方法，其中沉积第二氧化物层(32)的步骤包含使用由0.5至约2slpm氧化亚氮以及约10至约50sccm所述第二气体进行低压化学气相沉积。
4.如权利要求1所述的方法，其中沉积第二氧化物层(32)的步骤包含使用氧化亚氮以及二氯硅烷进行快速热化学气相沉积。
5.如权利要求4所述的方法，其中沉积第二氧化物层(32)的步骤包括使用约1至约3slpm氧化亚氮及约25至约75sccm二氯硅烷进行快速热化学气相沉积而形成一层厚约5至约15埃的氧化硅层。
6.一种在半导体基片(16)上于一个二位EEPROM装置(10)制造包括一ONO浮动栅极电极(26)的堆栈栅极结构的方法，该半导体基片具有一层第一位线氧化物层(20)以及一层第二位线氧化物层(22)其间由一基片表面区(18)隔开，其特征在于所述方法包含下列步骤：
形成一层ONO层(26)于基片表面区(18)上，形成方式为首先，经由热生长第一氧化硅层(28)于基片表面区(18)上，其次，形成一氮化硅层(30)覆于第一氧化硅层(28)上，以及第三，使用高温氧化物沉积方法沉积第二氧化硅层(32)于氮化硅层(30)上，
其中高温氧化硅沉积方法是在约700至约800℃的温度进行；
沉积一层栅极电极层(24)于ONO层(26)上；以及
形成一堆栈栅极结构于基片表面区(18)上，
其中该堆栈栅极结构包括一控制栅极电极(24)覆于一ONO浮动栅极电极(26)上。
7.如权利要求6所述的方法，其中沉积第二氧化物层(32)的步骤包括使用氧化亚氮以及第二种选自硅烷及二氯硅烷组成的组群的气体进行低压化学气相沉积。
8.如权利要求6所述的方法，其中沉积第二氧化物层(32)的步骤包含使用氧化亚氮以及二氯硅烷进行快速热化学气相沉积。
9.一种于一个二位EEPROM装置(10)制造一种ONO浮动栅极电极(26)的方法，包含下列步骤：
提供一具有一硅表面区(18)半导体基片(16)；
热生长氧化硅层(28)覆于该表面区(18)上；以及
使用选自RTCVD以及LPCVD组成的组群中的一种沉积方法，沉积一层氮化硅层(30)于氧化硅层(28)上以及一层顶氧化硅层(32)；
其中该氮化硅层(30)及该顶氧化硅层(32)是在未暴露于周围气氛的条件下循序沉积；以及
其中沉积处理是在约700至约800℃的温度进行。
10.如权利要求9所述的方法，其中RTCVD方法包含三步骤顺序包括一温度升高步骤、一沉积步骤经历约1分钟以及一冷却步骤。
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| US09/426,672 | 1999-10-25 |
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| US (1) | US6265268B1 (zh) |
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| DE (1) | DE60031155T2 (zh) |
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- 2000-10-16 EP EP00970962A patent/EP1234324B1/en not_active Expired - Lifetime
- 2000-10-16 CN CNB00814074XA patent/CN100447953C/zh not_active Expired - Lifetime
- 2000-10-16 KR KR1020027005319A patent/KR100784472B1/ko not_active IP Right Cessation
- 2000-10-16 WO PCT/US2000/028696 patent/WO2001031695A1/en active IP Right Grant
- 2000-10-18 TW TW089121772A patent/TW523815B/zh not_active IP Right Cessation
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1316574C (zh) * | 2003-06-11 | 2007-05-16 | 旺宏电子股份有限公司 | Ono介电质及其制造方法 |
| CN100444402C (zh) * | 2003-09-04 | 2008-12-17 | 株式会社日立制作所 | 半导体装置 |
| CN100377335C (zh) * | 2004-04-30 | 2008-03-26 | 东部亚南半导体株式会社 | 制造闪存器件的方法 |
| CN100382282C (zh) * | 2004-10-20 | 2008-04-16 | 力晶半导体股份有限公司 | 非挥发性存储单元的制作方法 |
| CN106463419A (zh) * | 2014-04-30 | 2017-02-22 | 惠普发展公司有限责任合伙企业 | 集成电路 |
| CN106463419B (zh) * | 2014-04-30 | 2019-05-14 | 惠普发展公司有限责任合伙企业 | 集成电路 |
| CN109003879A (zh) * | 2017-06-06 | 2018-12-14 | 中芯国际集成电路制造(上海)有限公司 | 栅介质层的形成方法 |
| CN109003879B (zh) * | 2017-06-06 | 2021-03-19 | 中芯国际集成电路制造(上海)有限公司 | 栅介质层的形成方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2001031695A1 (en) | 2001-05-03 |
| JP2003513445A (ja) | 2003-04-08 |
| EP1234324B1 (en) | 2006-10-04 |
| ATE341832T1 (de) | 2006-10-15 |
| KR100784472B1 (ko) | 2007-12-11 |
| DE60031155D1 (de) | 2006-11-16 |
| TW523815B (en) | 2003-03-11 |
| CN100447953C (zh) | 2008-12-31 |
| KR20020080330A (ko) | 2002-10-23 |
| EP1234324A1 (en) | 2002-08-28 |
| US6265268B1 (en) | 2001-07-24 |
| JP4907815B2 (ja) | 2012-04-04 |
| DE60031155T2 (de) | 2007-07-05 |
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