CN1331157C - 带有测试功能和冗余功能的半导体存储装置 - Google Patents

带有测试功能和冗余功能的半导体存储装置 Download PDF

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Publication number
CN1331157C
CN1331157C CNB031216943A CN03121694A CN1331157C CN 1331157 C CN1331157 C CN 1331157C CN B031216943 A CNB031216943 A CN B031216943A CN 03121694 A CN03121694 A CN 03121694A CN 1331157 C CN1331157 C CN 1331157C
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China
Prior art keywords
data
output
test
input
gate
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Expired - Fee Related
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CNB031216943A
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English (en)
Chinese (zh)
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CN1516199A (zh
Inventor
前野秀史
大泽德哉
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Publication of CN1516199A publication Critical patent/CN1516199A/zh
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Publication of CN1331157C publication Critical patent/CN1331157C/zh
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/32—Serial access; Scan testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C2029/3202—Scan chain
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/848—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching

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  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
CNB031216943A 1998-01-16 1998-09-18 带有测试功能和冗余功能的半导体存储装置 Expired - Fee Related CN1331157C (zh)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP652498 1998-01-16
JP6524/1998 1998-01-16
JP6524/98 1998-01-16
JP104752/1998 1998-04-15
JP104752/98 1998-04-15
JP10104752A JPH11265597A (ja) 1998-01-16 1998-04-15 半導体集積回路装置

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN 98119300 Division CN1223443A (zh) 1998-01-16 1998-09-18 半导体集成电路装置

Publications (2)

Publication Number Publication Date
CN1516199A CN1516199A (zh) 2004-07-28
CN1331157C true CN1331157C (zh) 2007-08-08

Family

ID=26340697

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB031216943A Expired - Fee Related CN1331157C (zh) 1998-01-16 1998-09-18 带有测试功能和冗余功能的半导体存储装置

Country Status (5)

Country Link
US (1) US6275963B1 (enExample)
JP (1) JPH11265597A (enExample)
KR (1) KR100288671B1 (enExample)
CN (1) CN1331157C (enExample)
TW (1) TW392170B (enExample)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7720672B1 (en) * 1995-12-29 2010-05-18 Wyse Technology Inc. Method and apparatus for display of windowing application programs on a terminal
JP2001035196A (ja) * 1999-07-26 2001-02-09 Mitsubishi Electric Corp 故障解析機能を備えた半導体集積回路装置
JP2001165999A (ja) * 1999-12-14 2001-06-22 Mitsubishi Electric Corp 半導体集積回路およびこれを用いた半導体集積回路装置
JP2001208798A (ja) 2000-01-26 2001-08-03 Mitsubishi Electric Corp 半導体回路のテスト方法および装置
US6801524B2 (en) * 2000-01-31 2004-10-05 Sonim Technologies, Inc. System for dispatching information packets and method therefor
JP4497695B2 (ja) * 2000-10-13 2010-07-07 株式会社ルネサステクノロジ 半導体集積回路装置
US6779139B2 (en) 2000-11-06 2004-08-17 Renesas Technology Corp. Circuit for reducing test time and semiconductor memory device including the circuit
JP2002203400A (ja) * 2000-11-06 2002-07-19 Mitsubishi Electric Corp テスト容易化回路および当該回路を含む半導体記憶装置
US6717222B2 (en) * 2001-10-07 2004-04-06 Guobiao Zhang Three-dimensional memory
US6593801B1 (en) 2002-06-07 2003-07-15 Pericom Semiconductor Corp. Power down mode signaled by differential transmitter's high-Z state detected by receiver sensing same voltage on differential lines
CN1182577C (zh) * 2002-11-08 2004-12-29 清华大学 降低非扫描可测试性设计管脚开销的方法
US7174486B2 (en) * 2002-11-22 2007-02-06 International Business Machines Corporation Automation of fuse compression for an ASIC design system
JP2005326203A (ja) * 2004-05-13 2005-11-24 Matsushita Electric Ind Co Ltd 半導体集積回路の実速度検査方法
US7496809B2 (en) * 2005-06-10 2009-02-24 Stmicroelectronics Pvt. Ltd. Integrated scannable interface for testing memory
JP4773791B2 (ja) * 2005-09-30 2011-09-14 富士通セミコンダクター株式会社 半導体記憶装置、およびメモリテスト回路
JP4894376B2 (ja) * 2006-06-29 2012-03-14 富士通セミコンダクター株式会社 半導体集積回路装置
JP5223735B2 (ja) * 2009-03-10 2013-06-26 富士通株式会社 メモリ試験回路及びプロセッサ
CN103295646B (zh) * 2012-02-27 2015-10-14 晨星软件研发(深圳)有限公司 运用于高速输出入端上的内建自测试电路
CN103576082B (zh) * 2012-08-06 2018-01-12 恩智浦美国有限公司 低功率扫描触发器单元
US10311150B2 (en) 2015-04-10 2019-06-04 Commvault Systems, Inc. Using a Unix-based file system to manage and serve clones to windows-based computing clients
US10033359B2 (en) * 2015-10-23 2018-07-24 Qualcomm Incorporated Area efficient flip-flop with improved scan hold-margin
US9966953B2 (en) 2016-06-02 2018-05-08 Qualcomm Incorporated Low clock power data-gated flip-flop
CN109212408B (zh) * 2017-06-29 2021-04-02 龙芯中科技术股份有限公司 一种扫描单元、冗余触发器的输出控制方法及装置
CN111750581A (zh) * 2019-03-26 2020-10-09 北京海益同展信息科技有限公司 保温装置、保温盒和送餐机器人
KR102889555B1 (ko) * 2019-08-26 2025-11-24 에스케이하이닉스 주식회사 테스트 회로, 이를 포함하는 반도체 장치 및 테스트 시스템

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5202625A (en) * 1991-07-03 1993-04-13 Hughes Aircraft Company Method of testing interconnections in digital systems by the use of bidirectional drivers
US5228000A (en) * 1990-08-02 1993-07-13 Mitsubishi Denki Kabushiki Kaisha Test circuit of semiconductor memory device
US5703818A (en) * 1996-08-26 1997-12-30 Mitsubishi Denki Kabushiki Kaisha Test circuit
EP0845788A2 (en) * 1996-11-27 1998-06-03 Texas Instruments Incorporated A memory array test circuit with failure notification

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5185722A (en) * 1989-11-22 1993-02-09 Sharp Kabushiki Kaisha Semiconductor memory device having a memory test circuit
EP0522413A3 (en) * 1991-07-03 1993-03-03 Hughes Aircraft Company A high impedance technique for testing interconnections in digital systems
JPH07245000A (ja) 1994-03-08 1995-09-19 Matsushita Electric Ind Co Ltd メモリテスト回路
JP3325727B2 (ja) 1994-05-26 2002-09-17 三菱電機株式会社 半導体メモリの検査装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5228000A (en) * 1990-08-02 1993-07-13 Mitsubishi Denki Kabushiki Kaisha Test circuit of semiconductor memory device
US5202625A (en) * 1991-07-03 1993-04-13 Hughes Aircraft Company Method of testing interconnections in digital systems by the use of bidirectional drivers
US5703818A (en) * 1996-08-26 1997-12-30 Mitsubishi Denki Kabushiki Kaisha Test circuit
EP0845788A2 (en) * 1996-11-27 1998-06-03 Texas Instruments Incorporated A memory array test circuit with failure notification

Also Published As

Publication number Publication date
JPH11265597A (ja) 1999-09-28
KR100288671B1 (ko) 2001-05-02
CN1516199A (zh) 2004-07-28
TW392170B (en) 2000-06-01
US6275963B1 (en) 2001-08-14
KR19990066768A (ko) 1999-08-16

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Granted publication date: 20070808

Termination date: 20091019