CN1327498C - 半导体装置和半导体装置的制造方法 - Google Patents

半导体装置和半导体装置的制造方法 Download PDF

Info

Publication number
CN1327498C
CN1327498C CNB2004101012197A CN200410101219A CN1327498C CN 1327498 C CN1327498 C CN 1327498C CN B2004101012197 A CNB2004101012197 A CN B2004101012197A CN 200410101219 A CN200410101219 A CN 200410101219A CN 1327498 C CN1327498 C CN 1327498C
Authority
CN
China
Prior art keywords
layer
semiconductor substrate
silicon layer
amorphous silicon
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2004101012197A
Other languages
English (en)
Chinese (zh)
Other versions
CN1638065A (zh
Inventor
宫野清孝
大内和也
水岛一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of CN1638065A publication Critical patent/CN1638065A/zh
Application granted granted Critical
Publication of CN1327498C publication Critical patent/CN1327498C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
CNB2004101012197A 2002-01-31 2003-01-29 半导体装置和半导体装置的制造方法 Expired - Fee Related CN1327498C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002023548A JP3657915B2 (ja) 2002-01-31 2002-01-31 半導体装置および半導体装置の製造方法
JP023548/2002 2002-01-31

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CNB031020909A Division CN1237620C (zh) 2002-01-31 2003-01-29 半导体装置和半导体装置的制造方法

Publications (2)

Publication Number Publication Date
CN1638065A CN1638065A (zh) 2005-07-13
CN1327498C true CN1327498C (zh) 2007-07-18

Family

ID=27606400

Family Applications (2)

Application Number Title Priority Date Filing Date
CNB2004101012197A Expired - Fee Related CN1327498C (zh) 2002-01-31 2003-01-29 半导体装置和半导体装置的制造方法
CNB031020909A Expired - Fee Related CN1237620C (zh) 2002-01-31 2003-01-29 半导体装置和半导体装置的制造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
CNB031020909A Expired - Fee Related CN1237620C (zh) 2002-01-31 2003-01-29 半导体装置和半导体装置的制造方法

Country Status (4)

Country Link
US (2) US6891232B2 (enExample)
JP (1) JP3657915B2 (enExample)
CN (2) CN1327498C (enExample)
TW (1) TWI284373B (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100540341B1 (ko) * 2003-12-31 2006-01-11 동부아남반도체 주식회사 반도체 소자 제조방법
US7102201B2 (en) * 2004-07-15 2006-09-05 International Business Machines Corporation Strained semiconductor device structures
JP2006295025A (ja) * 2005-04-14 2006-10-26 Sharp Corp 半導体装置およびその製造方法
JP2007299991A (ja) * 2006-05-01 2007-11-15 Toshiba Corp 半導体装置及びその製造方法
US7874011B2 (en) * 2006-12-01 2011-01-18 International Business Machines Corporation Authenticating user identity when resetting passwords
US7482270B2 (en) * 2006-12-05 2009-01-27 International Business Machines Corporation Fully and uniformly silicided gate structure and method for forming same
KR100844933B1 (ko) * 2007-06-26 2008-07-09 주식회사 하이닉스반도체 반도체 소자의 트랜지스터 및 그 제조 방법
US20090004851A1 (en) * 2007-06-29 2009-01-01 Taiwan Semiconductor Manufacturing Co., Ltd. Salicidation process using electroless plating to deposit metal and introduce dopant impurities
US7772074B2 (en) * 2007-10-18 2010-08-10 Applied Materials, Inc. Method of forming conformal silicon layer for recessed source-drain
KR20090065570A (ko) * 2007-12-18 2009-06-23 삼성전자주식회사 반도체 소자의 및 이의 제조방법
US20100044804A1 (en) * 2008-08-25 2010-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Novel high-k metal gate structure and method of making
WO2021209284A1 (en) 2020-04-15 2021-10-21 Basf Se A laminate comprising aqueous polyurethane dispersion and 2-component polyurethane and the use thereof
KR102874702B1 (ko) * 2021-02-25 2025-10-21 주식회사 디비하이텍 알에프 스위치 소자 및 제조방법

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1214540A (zh) * 1997-10-15 1999-04-21 世界先进积体电路股份有限公司 具有p+多晶硅栅极的金属氧化物半导体晶体管的制作方法
US5950098A (en) * 1995-06-26 1999-09-07 Mitsubishi Denki Kabushiki Kaisha Manufacturing method of a semiconductor device with a silicide layer
US6008124A (en) * 1996-02-22 1999-12-28 Matsushita Electric Industrial Co., Ltd. Semiconductor device having improved lamination-structure reliability for buried layers, silicide films and metal films, and a method for forming the same
JP2000323689A (ja) * 1999-05-14 2000-11-24 Toshiba Corp 半導体エピタキシャル基板及びその製造方法
JP2001189451A (ja) * 1999-12-28 2001-07-10 Toshiba Corp 半導体装置の製造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5470794A (en) * 1994-02-23 1995-11-28 Advanced Micro Devices Method for forming a silicide using ion beam mixing
US5824586A (en) * 1996-10-23 1998-10-20 Advanced Micro Devices, Inc. Method of manufacturing a raised source/drain MOSFET
US6071782A (en) * 1998-02-13 2000-06-06 Sharp Laboratories Of America, Inc. Partial silicidation method to form shallow source/drain junctions
US6232641B1 (en) * 1998-05-29 2001-05-15 Kabushiki Kaisha Toshiba Semiconductor apparatus having elevated source and drain structure and manufacturing method therefor
US6559036B1 (en) * 1998-08-07 2003-05-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
US6395624B1 (en) * 1999-02-22 2002-05-28 International Business Machines Corporation Method for forming implants in semiconductor fabrication
US6207995B1 (en) * 1999-02-23 2001-03-27 Advanced Micro Devices, Inc. High K integration of gate dielectric with integrated spacer formation for high speed CMOS
US6174791B1 (en) * 1999-03-25 2001-01-16 United Microelectronics Corp. Method for a pre-amorphization
US6346732B1 (en) * 1999-05-14 2002-02-12 Kabushiki Kaisha Toshiba Semiconductor device with oxide mediated epitaxial layer
US6333217B1 (en) * 1999-05-14 2001-12-25 Matsushita Electric Industrial Co., Ltd. Method of forming MOSFET with channel, extension and pocket implants
US6475868B1 (en) * 1999-08-18 2002-11-05 Advanced Micro Devices, Inc. Oxygen implantation for reduction of junction capacitance in MOS transistors
JP2002124665A (ja) * 2000-10-12 2002-04-26 Mitsubishi Electric Corp 半導体装置およびその製造方法
US20020192914A1 (en) * 2001-06-15 2002-12-19 Kizilyalli Isik C. CMOS device fabrication utilizing selective laser anneal to form raised source/drain areas

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5950098A (en) * 1995-06-26 1999-09-07 Mitsubishi Denki Kabushiki Kaisha Manufacturing method of a semiconductor device with a silicide layer
US6008124A (en) * 1996-02-22 1999-12-28 Matsushita Electric Industrial Co., Ltd. Semiconductor device having improved lamination-structure reliability for buried layers, silicide films and metal films, and a method for forming the same
CN1214540A (zh) * 1997-10-15 1999-04-21 世界先进积体电路股份有限公司 具有p+多晶硅栅极的金属氧化物半导体晶体管的制作方法
JP2000323689A (ja) * 1999-05-14 2000-11-24 Toshiba Corp 半導体エピタキシャル基板及びその製造方法
JP2001189451A (ja) * 1999-12-28 2001-07-10 Toshiba Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
TW200405471A (en) 2004-04-01
CN1435896A (zh) 2003-08-13
US6891232B2 (en) 2005-05-10
CN1638065A (zh) 2005-07-13
JP2003224261A (ja) 2003-08-08
TWI284373B (en) 2007-07-21
US20050035413A1 (en) 2005-02-17
JP3657915B2 (ja) 2005-06-08
CN1237620C (zh) 2006-01-18
US20030141549A1 (en) 2003-07-31

Similar Documents

Publication Publication Date Title
CN100456439C (zh) 具有抬高的源极/漏极结构的mos晶体管及其制造方法
US6121100A (en) Method of fabricating a MOS transistor with a raised source/drain extension
US6500720B2 (en) Method of manufacturing semiconductor device
US20050082522A1 (en) Strained channel transistor formation
US6372589B1 (en) Method of forming ultra-shallow source/drain extension by impurity diffusion from doped dielectric spacer
US7611973B2 (en) Methods of selectively forming epitaxial semiconductor layer on single crystalline semiconductor and semiconductor devices fabricated using the same
CN1655332A (zh) 一种制造半导体器件的方法及其半导体器件
US6830980B2 (en) Semiconductor device fabrication methods for inhibiting carbon out-diffusion in wafers having carbon-containing regions
CN1327498C (zh) 半导体装置和半导体装置的制造方法
US7485516B2 (en) Method of ion implantation of nitrogen into semiconductor substrate prior to oxidation for offset spacer formation
KR100558011B1 (ko) 전체실리사이드 금속게이트전극을 갖는 모스 트랜지스터의제조방법
JPH07201892A (ja) 低濃度ドーピングドレインを有するｍｏｓ型電界効果トランジスタの製造方法
US7148130B2 (en) Semiconductor device and method of manufacturing the same
US20050136607A1 (en) Methods of fabricating semiconductor devices
JP2001189451A (ja) 半導体装置の製造方法
US6635522B2 (en) Method of forming a MOS transistor in a semiconductor device and a MOS transistor fabricated thereby
KR100938322B1 (ko) Ｍｏｓ 트랜지스터 형성 방법 및 ｍｏｓ 트랜지스터들을 구비한 집적 회로
US20240363434A1 (en) Raised source/drain transistor
KR100705233B1 (ko) 반도체 소자의 제조 방법
US20080070360A1 (en) Method and structure for forming silicide contacts on embedded silicon germanium regions of cmos devices
KR100765617B1 (ko) 반도체 소자의 살리사이드 형성 방법
KR100940438B1 (ko) 반도체 소자의 제조 방법
JPH05110082A (ja) 半導体装置
CN112309866A (zh) 一种半导体器件及其制备方法
KR19990010444A (ko) 금속 샐리사이드층을 갖는 트랜지스터 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20070718

Termination date: 20130129