CN1321060A - 薄膜电路材料的激光成象 - Google Patents
薄膜电路材料的激光成象Info
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- CN1321060A CN1321060A CN00128400A CN00128400A CN1321060A CN 1321060 A CN1321060 A CN 1321060A CN 00128400 A CN00128400 A CN 00128400A CN 00128400 A CN00128400 A CN 00128400A CN 1321060 A CN1321060 A CN 1321060A
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- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
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Abstract
形成薄膜电气组件的方法,包括将具有所需电气性能的薄膜沉积在异质基底上,用计算机导向激光器的热能除去该薄膜的选定部分。根据本发明的一个方面,该薄膜为导电材料,例如铂或掺杂铂,且该基底为金属箔,例如铜箔。激光产生的热能烧蚀掉部分薄膜。根据本发明的另一个方面,在介电材料基底上沉积零价金属层,该基底的熔点或分解温度比零价金属的明显高。用计算机导向激光器将该零价金属层形成图案以形成电路组件,该激光提供的热能足以汽化掉零价金属层上的选定部分。
Description
本发明涉及用于形成电路组件的图案化材料,该组件具体源自薄膜材料例如可通过燃烧化学气相沉积(CCVD)和受控气氛燃烧化学气相沉积(CACCVD)沉积的那些材料。
目前,大多数印刷电路由光成象法制造。在一般加工中,起始材料为含介电材料例如玻璃纤维/环氧复合材料的毛坯,在其上提供一层金属例如铜。用光刻胶覆盖该铜。该光刻胶通过照相原图于光化学射线下曝光。光刻胶的未曝光部分被显像出来(在负性光刻胶时)。然后,曝光的铜被刻蚀掉。最后,剥离剩余的光可成象组合物。
尽管一直在提高光成象法的图形分辨率,但仍有必要增加图形分辨率。同时,光成象技术有天生的分辨率限制。由于化学刻蚀通过铜层并从旁边进行,所以图形分辨率受毛坯上金属层厚度的限制。图形分辨率还受到光刻胶层厚度的限制,该厚度又受到物理参数的限制。因此,本发明的目的之一是提供印刷电路组件例如电路迹线、电阻和电容器板的图案化方法,该方法的分辨率和光成象法固有的分辨率限度相比更细微。
美国专利US5652021和1996年8月2日递交的美国专利申请第08/691853,它们各自的教导在此结合引用,描述了CCVD法,其用于许多金属和准金属氧化物例如二氧化硅,以及某些零价金属例如铂的沉积。为了以零价状态沉积更多反应性金属例如锌、镍、铜等,必须防止金属氧化。为此,美国专利第09/067975号,其教导在此结合引用,描述了受控气氛燃烧化学气相沉积(CACCVD),其中氧的用量在燃烧中被充分控制,可沉积各种零价金属例如锌。CCVD和CACCVD均可用于沉积各种材料的很薄的(即25纳米薄)连续的集成膜。虽然本发明并不要求在此描述沉积层是通过CCVD和/或CACCVD沉积的,但是,它们代表了本发明人所知的沉积这类薄层的最佳方式,在大规模生产例如要求批量生产时,尤其如此。
美国专利申请09/198954,其教导在此经结合引用,该文告知用CCVD沉积的薄膜制造薄膜电阻。
根据本发明的一个方面,提供介电材料基底和沉积于其上的导电材料薄层,该导电材料具有沸腾温度且该基底具有高于该导电材料沸点的熔点或分解温度。用计算机导向激光使该导电材料图案化,该激光给导电材料层的选定部分提供足够热能,汽化掉导电材料层的这些部分而不分解或熔化该基底。
根据本发明的一个优选方面,提供含金属箔层、薄介电材料层和导电材料层的三层结构。该导电材料层的沸点显著低于该介电材料的熔点或分解温度并低于该箔层的熔点。再次用计算机导向激光器使该导电材料图案化,该激光给导电材料层的选定部分提供足够热能,汽化掉导电材料层的这些部分而不分解或熔化该基底。用于这种基底的一种材料的组合包括镍箔层;金属或准金属氧化物层例如二氧化硅;和锌导电层。
根据本发明的另一方面,发现可用计算机导向激光器提供的热能按预定图案烧蚀掉异质材料基底上的约0.05-约3微米厚的材料层。特别是,可用计算机导向激光器使约0.05-约3微米厚的导电材料图案化。
这种烧蚀加工的一例应用是不同金属例如铜箔的基底上的铂薄层。如以上引用的美国专利申请09/198954中所述,可用介电材料例如二氧化硅掺杂铂,使铂层的补片(patch)图案化以提供电阻元件。当暴露于计算机导向激光器的热能中时,该铂层的一些部分从铜箔基底上被烧蚀掉。
图1是三层结构的横截面图,该三层结构包括两侧面沉积锌层的玻璃基底。
图2是已按照本发明图案化的图1三层结构。
图3是包括镍箔层、薄介电材料层如二氧化硅和薄锌层的三层结构。
图4是图3的三层结构,其中锌层已按本发明图案化。
图5是图4的三层结构,其中图4的图案化锌层已被埋入介电材料层。
图6是图5的结构,其中镍箔已被电路化(circuitized),并被埋入介电材料中。
图7是两层结构的横截面图,该两层结构包括铜箔和沉积于其上的二氧化硅掺杂铂薄层。
图8是图7结构,其中铂薄层已被计算机导向激光图案化,并且该图案化铂层镶嵌在介电材料中。
图9是图8结构,其中该铜箔层已用传统方法图案化。
本文术语“沸点”应包括“升华点”。本文沉积法将按优选的CCVD法和CACCVD法讨论,但是应当理解,可用其它方法沉积薄层,特别是在小规模时。
本发明一个方面的方法中的一个重要要求是导电材料的沸腾温度要足够低,比基底材料的沸腾温度优选低至少200℃。在这点上,熔点419℃且沸点907℃的锌是优选的导电材料层。许多金属和准金属氧化物的熔化温度显著上高于907℃;例如合宜地用于本发明的一种材料二氧化硅,其熔点为1600℃以上。含金属箔层、薄介电材料层和薄导电锌层的三层结构中,镍是一种合宜的箔,其熔点为1455℃。在镍、二氧化硅、锌复合材料中,可控制对锌层的热能,以致可汽化锌层的选定部分而不干扰二氧化硅和镍层。
图1举例说明的是三层结构10,其包括玻璃(熔凝二氧化硅)基底11,在其上已用CACCVD法将锌薄层12沉积于两侧。玻璃11优选仅具有满足结构整体性要求的厚度,即约250-约4000微米厚。锌层12优选各厚约0.05-约3微米,即厚得足以承载足够的电荷但又尽可能薄以便获得最大的分辨率(resolution)。因为和玻璃相比,锌的熔点较低,可向锌层12的选定部分提供热能,以便汽化这些部分的锌而不熔化玻璃基底11。可由激光器非常精确且可再现地提供该热能,该激光器由计算机导向定位器引导,例如Melles Griot功率定位器,其可提供纳米控制。另外,特别有用的是计算机定位的脉冲激光钻孔装置,例如Hitachi出售的那种。
图2表示图1的三层结构10,其中锌层已被计算机导向激光器图案化。激光除去锌而留下导电的电路迹线13。玻璃基底11两侧的电路迹线13可按常规方式以通孔互连。还可将该电路迹线嵌入介电材料(未示出)中,例如称作“预浸料坯”的环氧树脂,以使此电路迹线成为多层电路板的组件。还应注意到,该级两侧上的锌片构成了电容器的电通道(electrical pathway)。而且,因为薄锌比多层电路板中可能互连这些锌层的铜迹线导电性差,所以锌层的条带可构成电阻的电通道。
图3表示含镍箔层21、沉积介电材料层22和锌沉积层23的三层结构20。该介电材料层22在此以二氧化硅层为例进行讨论,但也可使用熔点显著高于锌沸点的金属氧化物。镍箔21厚度约2.5-约50微米;介电材料层22厚度约0.05-约3微米;并且锌层23厚度约0.05-约3微米。
图4表示图3的三层结构20,其中通过用计算机导向激光器提供的热能汽化掉该锌层的选定部分,该锌层已经形成图案。这就产生了电路迹线24。另外,应当注意到,锌片25和镍箔构成电容器的电通道。还有,因为薄锌层23比其它组件的导电性差,在激光图形化所确定的隔开锌条27的相对端26之间构成电阻的电通道。该图形化电子电路还可包括电感组件(未示出)。
在锌图案化后,可将该结构的这一侧嵌入介电材料28例如预浸料坯中,如图5所示。此时,可用常规方法例如用常规的光刻胶加工使该镍层图案化,如图6所示,以便提供电路迹线29。然后图案化镍层21也可被嵌入介电材料30中。再者,可将整个结构与相似的层结合以便形成多层印刷电路板。
图7表示两层结构50,该结构包括其上沉积约0.5-3微米厚铂层51的铜箔层52。该铂用0.5-约5重量%的介电材料例如二氧化硅掺杂,以致尽管该铂仍然是导电的,但有作为电阻元件的足够电阻。计算机导向激光器提供的热能例如上述Hitachi出售的脉冲激光钻孔装置将使铂层的曝光部分从该铜箔上烧蚀掉。虽然烧蚀的确切机理还不知晓,但该热能导致铂和铜层之间的粘附力基本丧失,造成了从铜上烧蚀铂。图8中,已经用激光器将铂层图案化为51a的补片(patch)。然后将这些补片嵌入介电材料例如预浸料坯的层54中,它在后续步骤中支承铂片51a。然后如图9所示,将铜层52图案化为电路迹线52a。在位于电阻补片51a相对末端上的迹线52a之间经过该电阻补片形成电阻通道。
按照本发明,用激光烧蚀可在不同基底上加工各种薄膜材料。例如,可用激光烧蚀玻璃上的铜薄膜,以便形成电路迹线。可按图7-9将电阻材料从铜箔基底上烧蚀掉的方式从铜箔上烧蚀掉CCVD-沉积的二氧化硅。
现将用具体实例更详细地描述本发明。
实施例1
在0.025毫米厚的玻璃基底上,先在一侧然后在另一侧沉积0.15微米的金属锌层。这些锌层均从0.0350M的二(2-乙基己酸)锌无水乙醚溶液沉积得到。将该溶液以1.00sccm喷雾到一管中,该管还馈入40lpm预热到500℃的10%H2/Ar气混合物。距该管出口约5cm进行注射。该基底垂直于该气流置于距该管出口约2毫米处。
用计算机导向激光器使每一锌层图案化成电路,激光从玻璃基底的选定部分熔化并蒸发掉锌。
实施例2
在15微米厚锌箔基底的一个表面上沉积0.15微米厚二氧化硅层。该沉积用CCVD法完成。前体溶液由0.873重量%的四甲氧基氧硅烷、7.7重量%异丙醇和91.4重量%丙烷组成。然后用接近超临界的雾化器将该溶液喷雾到火焰中。该火焰烧向镍箔并在10分钟内完成沉积。
用实施例1的方法在二氧化硅层上沉积0.15微米厚的一锌层。
通过输入计算机导向激光器的热能将该锌层图案化,以便形成电路组件,该激光从玻璃基底的选定部分上熔化并汽化掉锌。
将图案化的锌层嵌入预浸料坯中,并固化该预浸料坯。
以传统方式使镍箔电路化,方法是用负性光刻胶覆盖该镍箔,经过照相原图将该光刻胶暴露于图案化光化学照射下,除去该光刻胶的未曝光部分,并用氯化铜氨溶液刻蚀该镍。然后剥除剩余的光刻胶并接着将图案化的镍嵌入预浸料坯中,固化该预浸料坯。
实施例3
用CCVD法在15微米厚的铜箔上沉积0.15微米厚的Pt/SiO2电阻材料层,使用如下的沉积条件:溶液制备:
1.23克二苯基-(1,5-环辛二烯)铂(Ⅱ)
250毫升甲苯
0.43克四乙氧基硅烷(1.5重量%Si甲苯溶液)
150克丙烷沉积条件:
溶液流速:3毫升/分钟
沉积时间:~18分钟,对于5”×6”的基底
路径#:6
沉积温度:500℃
自耦调压变压器:3.0A
尖端氧流速(Tip Oxygen flow):~2900毫升/分钟
选择性地将Pt/SiO2侧面暴露于Hitachi激光钻的脉冲激光能下,以便形成Pt/SiO2的不连续补片。然后将该侧面嵌入预浸料坯中并固化该预浸料坯。接着将铜侧面用光刻胶覆盖,将其暴露于光化辐照下,并使光刻胶显影。用氯化铁溶液刻蚀铜,从而形成电路迹线,该迹线与Pt/SiO2补片连接,形成电阻通道。
Claims (23)
1.一种薄膜电路组件的制造方法,包括在不同材料的基底上沉积材料薄层,并将所述薄层的选定部分暴露在计算机导向激光器提供的热能中。
2.权利要求1的方法,其中所述薄层的厚度介于约0.05-约3微米之间。
3.权利要求1的方法,其中所述薄层为导电材料。
4.权利要求3的方法,其中将所述薄层沉积在金属箔上。
5.权利要求1的方法,其中所述薄层为铂或掺杂的铂且所述基底为金属箔。
6.权利要求5的方法,其中所述金属箔为铜。
7.一种电路的制造方法,该方法包括:
提供介电材料基底,
在所述基底上沉积导电材料层以便达到约0.05-约3微米的厚度,所述导电材料具有沸点,所述介电材料具有高于所述导电材料所述沸点的熔点或分解温度,并且
向所述导电材料层的选定部分提供热能,以便汽化所述导电材料的选定部分,在所述基底上留下电路组件。
8.权利要求7的方法,其中所述热能由计算机导向激光器提供。
9.权利要求7的方法,其中所述导电材料为零价金属。
10.权利要求7的方法,其中所述导电材料为零价锌。
11.权利要求7的方法,其中所述介电材料为金属或准金属氧化物。
12.权利要求7的方法,其中所述介电材料为二氧化硅。
13.权利要求7的方法,其中通过燃烧化学气相沉积或受控气氛化学气相沉积将所述导电材料沉积在所述基底上。
14.权利要求7的方法,其中所述介电材料的沸点或分解温度高于所述沸点至少约200℃。
15.权利要求7的方法,其中所述介电材料基底为约0.05-约3微米厚的层,其位于熔点高于所述导电材料层沸点的金属衬里层上。
16.权利要求15的方法,其中所述金属衬里层为约2.5-约50微米厚的金属箔。
17.权利要求15的方法,其中所述衬里层的所述金属为镍。
18.权利要求15的方法,其中所述导电材料层为金属锌。
19.权利要求15的方法,其中所述介电材料层为金属或准金属氧化物。
20.权利要求15的方法,其中所述介电材料层为二氧化硅。
21.权利要求15的方法,其中通过燃烧化学气相沉积法或受控气氛燃烧化学气相沉积法沉积所述介电材料层。
22.权利要求15的方法,进一步包括将由所述导电材料层形成的所述电路组件包埋在介电材料中并使所述金属衬里层电路化。
23.权利要求15的方法,其中所述衬里材料的所述金属的熔点比所述导电材料的所述沸点高至少约200℃。
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US5843363A (en) | 1995-03-31 | 1998-12-01 | Siemens Aktiengesellschaft | Ablation patterning of multi-layered structures |
JPH10513314A (ja) | 1995-11-24 | 1998-12-15 | フィリップス エレクトロニクス ネムローゼ フェンノートシャップ | 金属層を非金属基板から選択的に除去する方法 |
US5824374A (en) | 1996-07-22 | 1998-10-20 | Optical Coating Laboratory, Inc. | In-situ laser patterning of thin film layers during sequential depositing |
US5874369A (en) | 1996-12-05 | 1999-02-23 | International Business Machines Corporation | Method for forming vias in a dielectric film |
US5895581A (en) * | 1997-04-03 | 1999-04-20 | J.G. Systems Inc. | Laser imaging of printed circuit patterns without using phototools |
US5885436A (en) * | 1997-08-06 | 1999-03-23 | Gould Electronics Inc. | Adhesion enhancement for metal foil |
US6193911B1 (en) * | 1998-04-29 | 2001-02-27 | Morton International Incorporated | Precursor solution compositions for electronic devices using CCVD |
-
1999
- 1999-10-13 US US09/418,207 patent/US6388230B1/en not_active Expired - Fee Related
-
2000
- 2000-10-10 EP EP00308916A patent/EP1093328A3/en not_active Withdrawn
- 2000-10-12 KR KR1020000060075A patent/KR20010050994A/ko not_active Application Discontinuation
- 2000-10-12 SG SG200005848A patent/SG125884A1/en unknown
- 2000-10-13 JP JP2000313213A patent/JP2001297986A/ja not_active Withdrawn
- 2000-10-13 TW TW089121416A patent/TW499824B/zh not_active IP Right Cessation
- 2000-10-13 CN CNB001284002A patent/CN1203736C/zh not_active Expired - Fee Related
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100385329C (zh) * | 2002-08-24 | 2008-04-30 | 皇家飞利浦电子股份有限公司 | 包括薄膜电路元件的电子器件及其制造方法 |
CN103094126A (zh) * | 2013-01-16 | 2013-05-08 | 东莞市凯昶德电子科技股份有限公司 | 陶瓷元器件细微立体导电线路的制备方法 |
CN112235948A (zh) * | 2020-10-13 | 2021-01-15 | 廖斌 | 一种柔性线路板制备方法及其制备的柔性线路板和该柔性线路板的应用 |
Also Published As
Publication number | Publication date |
---|---|
TW499824B (en) | 2002-08-21 |
SG125884A1 (en) | 2006-10-30 |
US6388230B1 (en) | 2002-05-14 |
JP2001297986A (ja) | 2001-10-26 |
EP1093328A2 (en) | 2001-04-18 |
CN1203736C (zh) | 2005-05-25 |
EP1093328A3 (en) | 2003-08-13 |
KR20010050994A (ko) | 2001-06-25 |
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