CN1293624C - 半导体器件中电容器的形成方法 - Google Patents
半导体器件中电容器的形成方法 Download PDFInfo
- Publication number
- CN1293624C CN1293624C CNB031104746A CN03110474A CN1293624C CN 1293624 C CN1293624 C CN 1293624C CN B031104746 A CNB031104746 A CN B031104746A CN 03110474 A CN03110474 A CN 03110474A CN 1293624 C CN1293624 C CN 1293624C
- Authority
- CN
- China
- Prior art keywords
- capacitor
- insulating layer
- layer
- hard mask
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 72
- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 239000010410 layer Substances 0.000 claims abstract description 54
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 229920005591 polysilicon Polymers 0.000 claims abstract description 21
- 239000011229 interlayer Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 6
- 238000002360 preparation method Methods 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 abstract description 4
- 239000010409 thin film Substances 0.000 abstract 1
- 239000000463 material Substances 0.000 description 5
- 239000004020 conductor Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910052745 lead Inorganic materials 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 description 2
- 229910000510 noble metal Inorganic materials 0.000 description 2
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical compound O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- 229910019899 RuO Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
本发明公开了一种高度集成半导体器件中电容器的形成方法，该电容器在工艺可靠性方面得以提高。为实现此效果，本发明包括：形成层间绝缘层于衬底上；以构成电容器的高度形成电容器绝缘层于层间绝缘层上；以梯形形状形成作为硬掩模的多晶硅图案于电容器绝缘层上；通过将作为硬掩模的多晶硅图案用作蚀刻阻挡层，去除位于制备电容器的区域内的电容器绝缘层，以形成电容器孔；形成下层电极于电容器孔内；以及形成介电薄膜和上层电极于下层电极上。
Description
技术领域
本发明涉及半导体器件中集成电路的形成方法；尤其是半导体器件中电容器的形成方法。
背景技术
随着半导体器件，尤其是动态随机存取存储器(DRAM)的集成度提高，作为贮存信息的基本单元的存储器单元的面积正急速地减少。
减少存储器单元面积伴随着电容器单元面积的进一步减少。降低单元面积的结果，使感测范围和感测速度同时下降。因此，有一个因α-粒子所产生软误差(soft error)的容许度降低的问题。因此，发展出一种在限定的单元面积下获致足够容量的方法是必须的。
电容器的电容量定义如下：
C＝ε·As/d
其中，ε、As和d分别表示介电常数、电极有效表面积和电极间的距离。
于是，电容器可藉增加电极表面积，减少介电薄膜厚度或增加介电常数来增加电容的容量。
在这些因素中，增加电极的表面积是首要的考虑。如凹陷结构、圆柱结构、多层鳍状结构等的电容器三维结构被建议来在有限的布线面积内增加电极的有效表面积。然而，随着半导体器件的集成度变得非常高，此方法在增加电极的有效面积方面存在限制。
同时，藉减少介电薄膜的厚度来使两个电极间的距离(d)最小化的其它方法亦在随介电薄膜厚度减少而增加漏电流方面存在局限。
因此，现今主要重点是以增加介电常数来获得电容量。典型地，已主要使用具有所谓氮氧(NO)结构的电容器，该结构将氧化硅层或氮化硅层用作介电薄膜。然而，现在，如Ta2O5和(Ba，Sr)TiO3(BST)的具有高介电常数的材料，或如(Pb，Zr)TiO3(PZT)，(Pb，La)(Zr，Ti)O3(PLZT))，SrBi2Ta2O9(SBT)，Bi4-xLaxTi3O12(BLT)的铁电材料被用作介电薄膜。
当以高介电材料当作介电薄膜形成高介电电容器，或以铁电材料当作介电薄膜形成铁电电容器时，还需要控制介电体周围的这些材料和制造工艺，以实现高介电材料或铁电材料的独特介电特性。
一般而言，贵金属或贵金属混合物，如Pt、Ir、Ru、RuO2、IrO2等，被用于高介电或铁电电容器的上层和下层电极。
具有凹陷结构的电容器通常用以在有限的面积内维持一致的电容量。然而，因凹孔宽度变窄的同时，凹孔高度变大，所以在凹孔上稳定地形成下层电极和上层电极、以及介电薄膜存在困难。
图1A至图1D为显示依现有技术形成半导体器件中电容器的方法的剖面图。
参照图1A，一有源区域11形成于衬底10上，一层间绝缘层12形成于衬底10上。之后，形成一接触孔，其穿过层间绝缘层12而连接有源区11。然后，该接触孔填满导电材料，以形成接触插塞13，且在其上以构成电容器的尺寸形成电容器绝缘层14。
然后，形成多晶硅层15作硬掩模，并且用于提供凹面状电容器的电容器孔的光敏图案16接着形成于多晶硅层15上。
参照图1B，多晶硅层15藉使用光敏图案16来作选择性蚀刻和构图。
参照图1C，电容器绝缘层14藉使用图案化的多晶硅层15作为蚀刻阻挡层(barrier)来去除，电容器孔16于是形成。
在线宽小于0.12微米的超微工艺技术中，当考虑到用作介电薄膜的Ta2O5的介电常数时，电容器孔的高度应当高于约20000，以得到所需的电容量。然而，若使用典型的光敏图案当作蚀刻阻挡层，则不可能形成此接触孔。作为替代的是，形成一多晶硅层作为硬掩模，且将其用作形成电容器孔的蚀刻阻挡层。
随着制备电容器的电容器孔被进一步地以较窄且较长的形状形成，电容器外形无法垂直地形成，更确切地说，会产生变形。在不同形式的变形中，电器容的下层部分较上层部分薄。此变形例子在图1C中以′A′来表示。
此种变形的原因是，因为电容器孔16的上层部分未在其横向侧被蚀刻处理，而下层部分的横向侧被蚀刻电容器绝缘层14时所产生的散射离子所导致的蚀刻处理。结果，电容器孔16的此二部分具有不同厚度，且此差异导致后续在电容器孔16内形成上层和下层电极及介电薄膜的工艺中的空隙(void)现象。此情形在图1D中以′B′表示。
因空隙现象，不可能稳定地形成电容器，于是半导体器件运作的可靠性降低。
发明内容
因此，本发明的目的是提供一种高度集成半导体器件中电容器的形成方法，该电容器在工艺可靠性方面得以提高。
依本发明的一个方面，提供一种方法，该方法为：形成层间绝缘层于衬底上；以构成电容器的高度形成电容器绝缘层于层间绝缘层上；以梯形形状形成作为硬掩模的多晶硅图案于电容器绝缘层上；通过将作为硬掩模的多晶硅图案用作蚀刻阻挡层，去除位于制备电容器的区域内的电容器绝缘层，以形成具有相等厚度且具有垂直外形的电容器孔；形成下层电极于电容器孔内；及形成介电薄膜和上层电极于下层电极上。
附图说明
本发明的以上和其它目的和特征，将因以下结合附图作出的对优选实施例的叙述而变得清晰，其中：
图1A至1D为显示依现有技术形成半导体器件中电容器的方法的剖面图；以及
图2A至2D为显示依本发明的优选实施例形成半导体器件中的电容器的方法的剖面图。
附图中的附图标记说明如下：
10衬底 11有源区域
12层间绝缘层 13接触插塞
14绝缘层 15多晶硅层
16光敏图案 20衬底
21有源区域 22层间绝缘层
23接触插塞 24绝缘层
25多晶硅层 26光敏图案
具体实施方式
图2A至2D为显示依本发明优选实施例在半导体器件中形成电容器的方法的剖面图。
参照图2A，层间绝缘层22形成于提供有源区域21的衬底20上。其后形成穿过层间绝缘层22与有源区21相连的接触孔。接触孔填满导电材料以形成接触插塞23，接着电容器绝缘层24以构成电容器所需的高度形成于接触插塞23的顶部。在此，电容器绝缘层24可使用氧化层，如未掺杂硅酸盐玻璃(USG)，磷硅酸盐玻璃(PSG)，硼磷硅酸盐玻璃(BPSG)等。
然后，形成作为硬掩模的多晶硅层25，及形成光敏图案26于其上，使得形成用于形成凹面状电容器的电容器孔。
参照图2B，藉使用光敏图案26当作蚀刻阻挡层，多晶硅层25被蚀刻得具有斜度。此时，高偏压能量用来造成多晶硅层25的斜度，且N2、BCl3或HBr气体之一用作对多晶硅层25的横向侧为钝态的蚀刻气体。同时，蚀刻工艺在一区域内以约1毫乇(mTorr)至约10毫乇(mTorr)的低压来进行，其中蚀刻设备中电极温度低于约20℃。于此，硬掩模层可以是TiN层、Ti层或W层。
参照图2C，光敏图案26被去除，且电容器绝缘层24藉使用多晶硅层25当作蚀刻阻挡层而蚀刻，以形成电容器孔27。此时，多晶硅层25被构图成斜的。在此，如果在多晶硅层25处于形成倾斜外形而非垂直外形的状态前进行该蚀刻处理，则产生底部多晶硅层25的损失，进一步导致电容器绝缘层24的上部的过蚀刻。通过依照此蚀刻工艺的操作方案，可以形成具有相等厚度且具有垂直外形的电容器孔27。
参照图2D，下层电极28形成于电容器孔27内。然后，介电薄膜和上层电极依序形成于其上，完成电容器的成形工艺。
如优选实施例中所示，清楚地显示当使用倾斜的多晶硅层形成电容器孔时，电容器孔的上部和下部具有相同的厚度。
同时，可以稳定地形成具一致厚度(亦即宽度)的电容器孔。因此，还可以在电容器孔内形成上层和下层电极和介电薄膜而不会有任何空隙现象，从而在高度集成的半导体器件中增加工艺可靠性。
虽然本发明是以特定的优选实施例叙述，但对本领域技术人员明显的是，可在不偏离本发明权利要求的范畴的情况下，作各种变化或修正。
Claims (3)
1.一种半导体器件中电容器的形成方法，包括步骤：
形成一层间绝缘层于衬底上；
以构成电容器的高度形成一电容器绝缘层于层间绝缘层上；
以梯形的形状形成作为硬掩模的多晶硅图案于电容器绝缘层上；
通过将作为硬掩模的多晶硅图案用作蚀刻阻挡层，去除位于制备电容器的区域内的电容器绝缘层，以形成具有相等厚度且具有垂直外形的电容器孔；
形成下层电极于电容器孔内；以及
形成介电薄膜和上层电极于下层电极上。
2.如权利要求1所述的方法，其中，形成作为硬掩模的多晶硅图案的步骤还包括步骤：
形成作为硬掩模的多晶硅层于电容器绝缘层上；
形成用以构成电容器孔的光敏图案于多晶硅层上；以及
利用光敏图案选择性地去除多晶硅层，以形成作为硬掩模的多晶硅图案。
3.如权利要求1所述的方法，其中，以梯形形状形成作为硬掩模的多晶硅图案的步骤，采用选自N2、BCl3和HBr所组成的组中的一种蚀刻气体。
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR37261/02 | 2002-06-29 | ||
| KR1020020037261A KR100753122B1 (ko) | 2002-06-29 | 2002-06-29 | 반도체 장치의 캐패시터 제조방법 |
| KR37261/2002 | 2002-06-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1467826A CN1467826A (zh) | 2004-01-14 |
| CN1293624C true CN1293624C (zh) | 2007-01-03 |
Family
ID=29774983
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031104746A Expired - Fee Related CN1293624C (zh) | 2002-06-29 | 2003-04-16 | 半导体器件中电容器的形成方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US20040002189A1 (zh) |
| KR (1) | KR100753122B1 (zh) |
| CN (1) | CN1293624C (zh) |
| TW (1) | TW200400587A (zh) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100801306B1 (ko) * | 2002-06-29 | 2008-02-05 | 주식회사 하이닉스반도체 | 반도체 장치의 캐패시터 제조방법 |
| KR100559040B1 (ko) * | 2004-03-22 | 2006-03-10 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
| US7135346B2 (en) * | 2004-07-29 | 2006-11-14 | International Business Machines Corporation | Structure for monitoring semiconductor polysilicon gate profile |
| CN105429370B (zh) * | 2014-09-22 | 2017-09-29 | 亿腾科技（无锡）有限公司 | 跑限自复位式限位编码器 |
| US11929280B2 (en) | 2020-09-22 | 2024-03-12 | Changxin Memory Technologies, Inc. | Contact window structure and method for forming contact window structure |
| CN114256417A (zh) * | 2020-09-22 | 2022-03-29 | 长鑫存储技术有限公司 | 电容结构及其形成方法 |
| EP4002437B1 (en) | 2020-09-22 | 2023-08-02 | Changxin Memory Technologies, Inc. | Method of forming a contact window structure |
| CN113035836B (zh) * | 2021-03-01 | 2022-03-08 | 长鑫存储技术有限公司 | 半导体结构的制备方法及半导体结构 |
| CN113053899B (zh) * | 2021-03-12 | 2023-04-28 | 长鑫存储技术有限公司 | 半导体结构制作方法及半导体结构 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5346845A (en) * | 1991-10-12 | 1994-09-13 | Goldstar Electron Co., Ltd. | Process for forming a trench capacitor memory cell |
| US6027967A (en) * | 1997-07-03 | 2000-02-22 | Micron Technology Inc. | Method of making a fin-like stacked capacitor |
| US6066541A (en) * | 1998-01-20 | 2000-05-23 | Nanya Technology Corporation | Method for fabricating a cylindrical capacitor |
| US6232175B1 (en) * | 1999-10-08 | 2001-05-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing double-recess crown-shaped DRAM capacitor |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100265359B1 (ko) * | 1997-06-30 | 2000-10-02 | 김영환 | 반도체메모리소자의전하저장전극형성방법 |
| KR100280622B1 (ko) * | 1998-04-02 | 2001-03-02 | 윤종용 | 반도체 장치의 콘택 형성 방법 |
| KR100290835B1 (ko) * | 1998-06-23 | 2001-07-12 | 윤종용 | 반도체소자의제조방법 |
| KR100801306B1 (ko) * | 2002-06-29 | 2008-02-05 | 주식회사 하이닉스반도체 | 반도체 장치의 캐패시터 제조방법 |
-
2002
- 2002-06-29 KR KR1020020037261A patent/KR100753122B1/ko not_active IP Right Cessation
- 2002-12-09 US US10/314,296 patent/US20040002189A1/en not_active Abandoned
- 2002-12-20 TW TW091136872A patent/TW200400587A/zh unknown
-
2003
- 2003-04-16 CN CNB031104746A patent/CN1293624C/zh not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5346845A (en) * | 1991-10-12 | 1994-09-13 | Goldstar Electron Co., Ltd. | Process for forming a trench capacitor memory cell |
| US6027967A (en) * | 1997-07-03 | 2000-02-22 | Micron Technology Inc. | Method of making a fin-like stacked capacitor |
| US6066541A (en) * | 1998-01-20 | 2000-05-23 | Nanya Technology Corporation | Method for fabricating a cylindrical capacitor |
| US6232175B1 (en) * | 1999-10-08 | 2001-05-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing double-recess crown-shaped DRAM capacitor |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100753122B1 (ko) | 2007-08-29 |
| KR20040001927A (ko) | 2004-01-07 |
| CN1467826A (zh) | 2004-01-14 |
| US20040002189A1 (en) | 2004-01-01 |
| TW200400587A (en) | 2004-01-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1222029C (zh) | 制造用于半导体装置的圆柱型电容器的方法 | |
| CN1293624C (zh) | 半导体器件中电容器的形成方法 | |
| KR20040078828A (ko) | 반도체소자의 캐패시터 형성방법 | |
| CN1885503A (zh) | 用于在半导体器件中形成接触孔的方法 | |
| KR100446580B1 (ko) | 전극장치 | |
| CN1146017C (zh) | 半导体器件及其制造方法 | |
| KR19990073950A (ko) | 반도체 소자의 캐패시터 제조 방법 | |
| KR100798789B1 (ko) | 반도체 소자의 제조 방법 | |
| KR100744038B1 (ko) | 반도체 장치의 캐패시터 제조방법 | |
| KR100337926B1 (ko) | 반도체소자의저장전극형성방법 | |
| KR100476380B1 (ko) | 반도체 장치의 실린더형 캐패시터 제조방법 | |
| KR100801306B1 (ko) | 반도체 장치의 캐패시터 제조방법 | |
| KR100816688B1 (ko) | 반도체 소자의 캐패시터 제조 방법 | |
| KR100479606B1 (ko) | 반도체장치의 캐패시터 제조방법 | |
| KR100881751B1 (ko) | 반도체 장치의 캐패시터 제조방법 | |
| KR20030054310A (ko) | 반도체 소자의 캐패시터의 제조 방법 | |
| KR100326241B1 (ko) | 반도체소자의캐패시터형성방법 | |
| KR20030054029A (ko) | 반도체 소자의 캐패시터의 제조 방법 | |
| KR100781866B1 (ko) | 반도체 소자의 캐패시터 및 그의 제조 방법 | |
| KR0164080B1 (ko) | 반도체 소자의 저장전극 형성방법 | |
| KR20040008697A (ko) | 반도체 장치의 캐패시터 제조방법 | |
| KR20000045458A (ko) | 반도체소자의 저장전극 형성방법 | |
| KR20040008698A (ko) | 반도체 장치의 캐패시터 제조방법 | |
| KR20040059780A (ko) | 반도체장치의 캐패시터 제조방법 | |
| KR19990004599A (ko) | 반도체소자의 전하저장전극 형성방법 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070103 Termination date: 20100416 |