CN1280915C - 沟槽肖特基整流器 - Google Patents
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Abstract
提供一种肖特基整流器。肖特基整流器包括：(A)具有半导体区和漂移区的第一和第二相对表面的半导体区，该半导体区包括邻接第一表面(12A)的第一导电类型的阴极区(12C)和邻接第二表面的第一导电类型的漂移区(12D)，该漂移区具有比阴极区的掺杂浓度更低的净掺杂浓度；(B)从第二表面(12B)延伸进入半导体区并在半导体区中限定一个或多个台面的一个或多个沟槽；(C)绝缘区(16)，邻接沟槽下部中的半导体区；(D)以及阳极电极，其(I)邻接肖特基整流接触并与第二表面(12)处的半导体形成肖特基整流接触，(II)邻接肖特基整流接触并与沟槽上部之中的半导体区形成肖特基整流接触，并且(III)邻接沟槽下部之中的绝缘区(16)。
Description
发明领域
本发明涉及整流器，更具体地，本发明涉及肖特基势垒整流器件及其形成方法。
发明背景
整流器相对于正向流动的电流显示相对低的电阻并相对于反向流动的电流显示相对高的电阻。肖特基势垒整流器(Schottky barrierrectifiers)是已经发现的在开关模式的电源中并在其它高速电源开关应用例如电机驱动中用于整流器输出的一种整流器。这些器件能够承载大的正向电流并维持较高的反向阻断电压。
在此引入并参考其整个公开的Mehrotra等人的名称为“具有MOS沟槽的肖特基势垒整流器”的美国专利US5365102公开了肖特基势垒整流器，其比理论上获得的理想突变平面型P-N结的整流器具有更高的击穿电压。图1中说明了上述整流器的一个实施例的剖面图。在此图中，整流器10包含具有第一表面12a和第二相对表面12b的第一导电类型、典型为N-型导电类型的半导体衬底12。衬底12包括邻接第一表面12a的相对重掺杂的阴极区12c(示出为N+)。第一导电类型(示出为N+)的漂移区12d从阴极区12c延伸至第二表面12b。因此，阴极区12c的掺杂浓度大于漂移区12d的掺杂浓度。在漂移区12d中形成由相对侧面14a和14b限定的具有剖面宽度“Wm”的台面14。台面可以为条形、矩形、圆柱形或其它类似的几何图形。在台面侧面上还设置绝缘区16a和16b(描述为SiO2)。整流器还包含绝缘区16a、16b之上的阳极电极18。阳极电极18与第二表面12b处的台面14形成肖特基整流接触。在阳极电极/台面界面处形成的肖特基势垒层的高度由使用的电极金属和半导体(例如，Si、Ge、GaAs和SiC)的类型来决定并根据台面14中的掺杂浓度来决定。最后，邻接阴极区12c在第一表面12a处设置阴极电极20。阴极电极20欧姆接触阴极区12c。
当现代的电源电压为了适应减少功耗并提高能效的需要而持续降低时，在电源整流器上降低导通压降、且还维持高的正偏电流密度的水平就变得更加重要。本领域普通技术人员已公知，导通压降通常根据金属/半导体结上的正向电降和半导体区与阴极接触的串联电阻而决定。
对于降低功耗的需要还必须使反偏漏电流最小。反偏漏电流是在反偏阻断操作模式期间在整流器中的电流。为了维持高反偏阻断电压并使反偏漏电流最小，整流器的半导体部分典型为轻掺杂并制造得相对厚，以致在金属/半导体界面处的反偏电场不会变得过高。给定反偏电压下的反偏漏电流的值还与金属和半导体区之间的肖特基势垒层的高度(势垒层)成反比。因此，为了实现减少功耗，应当使反偏压降和反偏漏电流最小并且使反偏阻断电压最大。
由于在漂移区14的台面形部分和相对沟槽的绝缘侧壁16a、16b的金属阳极18的部分中的主电荷载流子之间产生的电荷耦合，根据美国专利US5612567，图1的器件就能获得所期望的效果。特别地，相对于理想的平面型整流器显著地降低了金属-半导体接触(肖特基接触)的中心处的电场。通过降低肖特基势垒高度，肖特基接触中心处的电场的降低就导致了反偏漏电流的显著减少。反偏漏电流是在反偏(阻断)操作模式期间的整流器中的电流。而且，电场分布轮廓的峰值就从金属-半导体接触漂移并进入漂移区。由于电场的峰值从肖特基接触向外移动，因此台面就能够维持更高电压，由此提供比理想的平面型整流器更高的击穿电压(反向阻断电压)。
图2说明图1中所示的肖特基整流器的击穿电压与沟槽氧化物厚度的关系图，它是前述专利的图12的再现。具体地，示出了随着氧化物厚度增加直到至少2200埃未变化的击穿电压。对于分别具有0.5微米的台面宽度和1微米的单元间距并且分别具有3微米的沟槽深度和4微米的漂移区厚度的肖特基整流器获得了图2的关系图。
如图2所示，高压应用中采用的肖特基整流器(Schottky rectifiers)需要相对厚的沟槽氧化层。典型地通过热技术来生长氧化层，因为它提供具有在氧化物-半导体界面处的降低缺陷密度的良好外延，所以优先采用热技术。遗憾的是，相对于热生长氧化层的低生长速度就难于获得具有2000埃以上厚度的沟槽氧化层。而且，具有更高淀积速度的可替换的生长技术例如化学气相淀积(CVD)将产生更多缺陷密度并由此在氧化物-半导体界面产生更多的电荷。
因此，在现有技术中就存在一种需要以提供沟槽肖特基整流器器件以便在高压下工作并相对容易制造。
发明概述
通过本发明就能满足上述和其它需要。具体地，提供一种肖特基整流器，包括：(a)具有半导体区和漂移区的第一和第二相对表面的半导体区，该半导体区包括邻接第一表面的第一导电类型的阴极区和邻接第二表面的第一导电类型的漂移区，该漂移区具有比阴极区的掺杂浓度更低的净掺杂浓度；(b)从第二表面延伸进入半导体区并在半导体区中限定一个或多个台面的一个或多个沟槽；(c)绝缘区，邻接沟槽下部中的半导体区；(d)以及阳极电极，其(i)邻接肖特基整流接触并与第二表面处的半导体形成肖特基整流接触，(ii)邻接肖特基整流接触并与沟槽上部之中的半导体区形成肖特基整流接触，并且(iii)邻接沟槽下部之中的绝缘区。
优选地，半导体是硅，第一导电类型是n-型导电类型，并且在第一表面上设置阴极电极。
沟槽的下部优选对应于沟槽的大约25-40％的深度。在一些实施例中，沟槽延伸进入具有绝缘的优选在阴极区和漂移区之间延伸的沟槽下部的阴极区。
绝缘区优选包括可以淀积或热生长的二氧化硅。
在一些实施例中，多晶硅区设置在绝缘区上并形成阳极电极的一部分。
本发明还提供一种形成沟槽肖特基整流器的方法。该方法包括：(a)形成具有半导体区和漂移区的第一和第二相对表面的半导体区，该半导体区包括邻接第一表面的第一导电类型的阴极区和邻接第二表面的第一导电类型的漂移区，该漂移区具有比阴极区的掺杂浓度更低的净掺杂浓度；(b)形成从第二表面延伸进入具有沟槽的半导体区并在半导体区中限定一个或多个台面的一个或多个沟槽；(c)形成邻接沟槽下部中的半导体区的绝缘区；(d)以及形成阳极电极，其(i)邻接肖特基整流接触并与第二表面处的半导体区形成肖特基整流接触，(ii)邻接肖特基整流接触并与沟槽上部之中的半导体区形成肖特基整流接触，并且(iii)邻接沟槽下部之中的绝缘区。
形成半导体区的步骤优选包括提供对应于阴极区的半导体衬底，并生长与衬底上的漂移区相对应的外延半导体层。
形成沟槽的步骤优选包括在半导体区的第二表面之上形成构图的掩膜层并通过掩膜层蚀刻沟槽。
形成绝缘区的步骤包括在沟槽中的第二表面之上设置氧化层，随后蚀刻氧化层的一部分。在一些实施例中，在氧化层(它可以为热生长)上设置光刻胶图形，并且部分氧化层没有被蚀刻的光刻胶覆盖，由此去除光刻胶。在一些实施例中，在氧化层(它可以为热生长)上设置多晶硅层，并蚀刻多晶硅层，以致暴露在第二表面之上并在沟槽上部之上的部分氧化层，随后通过蚀刻去除这些暴露的部分。
形成绝缘区的步骤还可以包括淀积氧化层。例如，可以在第二表面上并在沟槽之中淀积原硅酸四乙酯(tetraethylorthosilicate)层。然后蚀刻原硅酸四乙酯层直至从第二表面和沟槽上部去除它。随后，可以将原硅酸四乙酯层转换为高密度的二氧化硅层。
本发明的一个优点是提供一种新颖的具有低反偏压降、低反偏漏电流和高击穿电压的肖特基势垒整流器。
另一个优点是可以使用简单而且经济的制造技术来制造这种肖特基势垒整流器。
本领域技术人员通过审阅以下提出的详细的说明书、实施例和权利要求书，其它实施例和优点将变得更加明显。
附图的简要描述
图1说明根据现有技术的沟槽MOS势垒肖特基整流器的剖面图。
图2是例如图1中所示的肖特基整流器的击穿电压与沟槽氧化物厚度的关系图。
图3是根据本发明的一个实施例的沟槽肖特基整流器的剖面图。
图4是根据本发明的一个实施例的沟槽肖特基整流器的剖面图。
图5是根据本发明的一个实施例的沟槽肖特基整流器的剖面图。
图6是根据本发明的一个实施例的沟槽肖特基整流器的剖面图。
图7A-7B是说明形成根据本发明的一个实施例的图3的沟槽肖特基整流器的方法的剖面图。
本发明的一些优选实施例的详细描述
现在，将参照其中示出本发明的优选实施例的附图更加全面地描述本发明。然而，本发明以不同形式举例而不应当限于在此提出的实施例。
现在参照图3，图3示出了根据本发明的肖特基势垒整流器(Schottky barrier rectifier)的剖面图。整流器10包含具有第一表面12a和第二相对表面12b的第一导电类型、典型为N-型导电类型的半导体区12。衬底半导体区12优选包括邻接第一表面12a的相对重掺杂的阴极区12c(示出为N+)。如图所示，阴极区12c掺杂为第一导电类型、大约5×1019/cm-3的杂质浓度。第一导电类型(示出为N)的漂移区12d优选从阴极区延伸至第二表面12b。如图所示，对于30伏的器件，漂移区12d掺杂为第一导电类型、大约3.3×1016/cm-3的杂质浓度。漂移区12d和阴极区12c形成非整流N+/N结。
在漂移区12d中形成具有剖面宽度“Wm”的台面14。由相对的沟槽限定台面。绝缘区16(在此情况下，示出为热生长的氧化层)形成在沟槽之中并邻接半导体区12。每个绝缘区16包含第一和第二绝缘区16a和16b。绝缘区16a是热生长的层。在绝缘区16a之上通过淀积技术生长绝缘区16b。如下所述，热生长的区域优越地制造出具有相对低缺陷的氧化物-半导体界面而淀积的区域能够生长相对厚的沟槽氧化层。绝缘区16典型具有大约700-2000埃的总厚度。Wm典型为大约1微米。沟槽深度“d”典型为大约3微米。
台面14在三维方向上(未示出)延伸，并且可以为条形、矩形、圆柱形或其它类似的几何形状。因此，本领域技术人员应当理解，可以利用多种沟槽结构在半导体区12中形成台面14。
例如，可以在三维方向上延伸的相邻线形沟槽对之间形成台面14。作为另一个实施例，环形沟槽形成台面14。对于这些实施例，当以横向剖面方向观看时，沟槽就如图3中所示。
可以看出，阳极电极18同时沿第二表面邻接漏区12d。可以看出，阳极电极18同时还邻接绝缘区16。阳极电极18在它接触半导体漏区12d处即沿第二表面12b形成肖特基势垒整流结。
最后，邻接阴极区12c在第二表面12b处设置阴极电极(未示出)。阳极电极最好欧姆接触阴极区12c。
这种整流器具有高反偏击穿电压。不希望任何特殊的工作原理来支持，应当相信，这种设计提供在阳极电极18和台面14之间导致产生电荷耦合的绝缘区16、有利地影响台面结构之中的电压分布轮廓并提供高反偏击穿电压和低漏电流。本领域技术人员优化相对于第二绝缘层16b的厚度的第一绝缘层16a的厚度是显而易见的。
图4中提供了本发明的另一个实施例。除了沟槽延伸超出漂移区12d并延伸进入阴极区12c之外，本实施例类似于图3的实施例。
在图5和6中示出了本发明的其它实施例。在图5中，通过采用多层阳极电极，其包括钛层18a、钛钨层18b和钨层18c，改善了阳极电极和漂移区12d之间的接触的肖特基整流特性。在该具体的实例中，钛钨层18b包括50％的钛和50％的钨。通过形成器件之中的P+区就使正偏压降进一步改善。在该具体的实例中，P+区的掺杂浓度为1×1019/cm-3。
图7A-7B说明本发明用于提供图3中所示的沟槽肖特基整流器10的实施例。现在参照这些附图，在常规的N+掺杂的衬底上(对应于阴极区12c)生长N-掺杂的外延层(对应于漂移区12d)。外延层12d典型为大约7微米厚。接着，利用光刻胶掩膜工艺形成限定沟槽21的位置的掩膜部分(未示出)。优选通过反应离子腐蚀穿过掩膜部分之间的开口干法蚀刻沟槽21、典型为大约3微米的深度。去除掩膜部分并在整个表面之上分别通过热生长和淀积来形成绝缘层16a和16b。绝缘层16a和16b典型为氧化层例如二氧化硅(SiO2)。对于热氧化层16典型为大约700-2000埃范围的厚度。
通过热氧化的生长是常规技术，使用该技术以生长二氧化硅层16a。在所有的热方法中，都是由硅(Si)来形成二氧化硅。由于氧的出现，即使在室温下也户发生这种反应。然而，通常需要高温(典型为900和1200℃之间)以便在合理的工艺时间内获得高质量的氧化物。将利用氧气作为氧源的反应称作干法氧化。将利用水蒸汽作为氧源的反应称作蒸汽氧化或湿法氧化。与蒸汽氧化相关的生长速率大于与干法氧化的生长速率。可以采用包括空气生长技术、快速热氧化技术、高压氧化技术和阳极氧化的各种热氧化技术来生长二氧化硅层16a。热生长的优点是因为与此相关的低生长速率容易形成无缺陷层。
可以通过淀积技术例如化学气相淀积(CVD)来生长绝缘层16b。在CVD中，在晶片表面上完整地淀积有益的材料。适合的几种CVD技术包括大气压化学气相淀积(APCVD)、低压化学气相淀积(LPCVD)和增强等离子体CVD(PECVD)。再次假设绝缘层16b是二氧化硅，那么在实施例APCVD工艺中，在淀积室中、典型为大约450℃下混合并反应硅烷(SiH4)和氧气(O2)来形成SiO2。在典型的LPCVD工艺中，采用较高的温度例如大约900℃使二氯硅烷(SiCl2H2)与氧化氮(NO2)反应来形成SiO2。在公知的PECVD工艺中，采用较低的温度典型为大约400℃并在氧气氛下使用原硅酸四乙酯(TEOS)(Si(OC2H5)4)源来形成SiO2。如果需要，可以使淀积的CVD层致密，例如通过高温退火步骤。在致密之后，淀积的二氧化硅膜就紧靠结构并接近热生长的氧化物的特性。在热生长技术之上的淀积技术的主要优点是淀积技术提供较快的生长速率。结果，可以容易地制造相对较厚的沟槽氧化层。而且，由于在氧化物-半导体界面处设置热生长的层，因此在界面处就获得了没有产生非常高的缺陷密度的厚氧化层。
最后，如图7B所示，设置阳极电极18以完成该结构。例如，通过设置(a)Ti:W层、接着(b)Pt:Si层、接着(c)Al层来获得阳极电极。作为另一个实例，可以通过设置(a)Ti:N层、接着(b)Pt:Si层、接着(c)Al层来获得阳极电极。
尽管在图5中(见上述的讨论)出现了阳极电极18结构的另一个实例。在本实施例中，通过设置(a)Ti层、接着(b)Ti:W层、接着(c)W层来获得阳极电极。
在与即将制造图6结构类似的结构的情况下，除了在生长外延层12d之后在外延层12d的上部例如通过离子注入和扩散来形成P+层之外，随后进行上述步骤。
因此，本发明提供一种沟槽肖特基整流器及其制造方法。获得的肖特基整流器具有厚的沟槽氧化层并由此具有高击穿电压。虽然已经描述了关于几个具体的实施例的本发明，但本领域技术人员对上述实施例的许多其它变化将是明显的。应当理解，这些变化将不仅通过附加的权利要求书限定而且落入本发明的教导之内。
Claims (9)
1.一种肖特基整流器，其包括：
具有第一和第二相对表面的半导体区，所说半导体区包括邻接第一表面的第一导电类型的阴极区和邻接第二表面的所说第一导电类型的漂移区，所说漂移区具有比所说阴极区的掺杂浓度更低的净掺杂浓度；
一个或多个沟槽，从所说第二表面延伸进入所说半导体区、并在所说半导体区中限定出一个或多个台面；
绝缘区，邻接所说一个或多个沟槽中的所说半导体区，所说绝缘区包含接触所说半导体区的热生长的绝缘层和在所说热生长的绝缘层之上配置的淀积生长的绝缘层；以及
阳极电极，(a)其邻接肖特基整流接触并在所说第二表面处与所说半导体区形成肖特基整流接触，并且(b)其邻接所说沟槽中的所说绝缘区，
其中，所说沟槽延伸进入所说阴极区。
2.权利要求1的肖特基整流器，其中所说绝缘区包括氧化物。
3.权利要求2的肖特基整流器，其中所说绝缘区包括二氧化硅。
4.权利要求1的肖特基整流器，其中通过化学气相淀积生长所说淀积生长的绝缘层。
5.权利要求2的肖特基整流器，其中通过化学气相淀积生长所说淀积生长的绝缘层。
6.权利要求3的肖特基整流器，其中通过化学气相淀积生长所说淀积生长的绝缘层。
7.权利要求1的肖特基整流器，其中所说半导体是硅。
8.权利要求1的肖特基整流器，其中所说第一导电类型是n-型导电类型。
9.一种肖特基整流器，其包括：
具有第一和第二相对表面的半导体区，所说半导体区包括邻接第一表面的第一导电类型的阴极区和邻接第二表面的所说第一导电类型的漂移区，所说漂移区具有比所说阴极区的掺杂浓度更低的净掺杂浓度；
一个或多个沟槽，从所说第二表面延伸进入所说半导体区、并在所说半导体区中限定出一个或多个台面；
绝缘区，邻接所说一个或多个沟槽中的所说半导体区，所说绝缘区包含接触所说半导体区的热生长的绝缘层和在所说热生长的绝缘层之上配置的淀积生长的绝缘层，其中，所说热生长绝缘层具有比所说淀积生长层低的缺陷密度；以及
阳极电极，(a)其邻接肖特基整流接触并在所说第二表面处与所说半导体区形成肖特基整流接触，并且(b)其邻接所说沟槽中的所说绝缘区。
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| JPS4822390B1 (zh) * | 1969-03-18 | 1973-07-05 | ||
| JPS5294773A (en) * | 1976-02-05 | 1977-08-09 | Sumitomo Electric Ind Ltd | Semiconductor element and its manufacture |
| US4835580A (en) * | 1987-04-30 | 1989-05-30 | Texas Instruments Incorporated | Schottky barrier diode and method |
| US5365102A (en) * | 1993-07-06 | 1994-11-15 | North Carolina State University | Schottky barrier rectifier with MOS trench |
| US6078090A (en) * | 1997-04-02 | 2000-06-20 | Siliconix Incorporated | Trench-gated Schottky diode with integral clamping diode |
| US5612567A (en) * | 1996-05-13 | 1997-03-18 | North Carolina State University | Schottky barrier rectifiers and methods of forming same |
| US5883422A (en) * | 1996-06-28 | 1999-03-16 | The Whitaker Corporation | Reduced parasitic capacitance semiconductor devices |
| JP3502531B2 (ja) * | 1997-08-28 | 2004-03-02 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
| US6184563B1 (en) * | 1998-07-27 | 2001-02-06 | Ho-Yuan Yu | Device structure for providing improved Schottky barrier rectifier |
| US6252258B1 (en) * | 1999-08-10 | 2001-06-26 | Rockwell Science Center Llc | High power rectifier |
| JP2001085686A (ja) * | 1999-09-13 | 2001-03-30 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
| JP2001094094A (ja) * | 1999-09-21 | 2001-04-06 | Hitachi Ltd | 半導体装置およびその製造方法 |
-
2001
- 2001-06-01 US US09/872,926 patent/US6580141B2/en not_active Expired - Lifetime
-
2002
- 2002-05-31 WO PCT/US2002/017322 patent/WO2002099889A1/en active Application Filing
- 2002-05-31 EP EP02739587A patent/EP1393379B1/en not_active Expired - Lifetime
- 2002-05-31 TW TW091111744A patent/TW548855B/zh not_active IP Right Cessation
- 2002-05-31 CN CNB028111443A patent/CN1280915C/zh not_active Expired - Lifetime
- 2002-05-31 KR KR1020037015603A patent/KR100884077B1/ko active IP Right Grant
- 2002-05-31 JP JP2003502893A patent/JP4313190B2/ja not_active Expired - Lifetime
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2003
- 2003-05-05 US US10/429,817 patent/US6770548B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP1393379A1 (en) | 2004-03-03 |
| WO2002099889A1 (en) | 2002-12-12 |
| US6770548B2 (en) | 2004-08-03 |
| TW548855B (en) | 2003-08-21 |
| KR20040005998A (ko) | 2004-01-16 |
| US6580141B2 (en) | 2003-06-17 |
| JP4313190B2 (ja) | 2009-08-12 |
| US20020179993A1 (en) | 2002-12-05 |
| EP1393379A4 (en) | 2009-08-12 |
| KR100884077B1 (ko) | 2009-02-19 |
| US20030193074A1 (en) | 2003-10-16 |
| WO2002099889A9 (en) | 2004-04-08 |
| CN1520615A (zh) | 2004-08-11 |
| JP2004529506A (ja) | 2004-09-24 |
| EP1393379B1 (en) | 2011-12-21 |
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