CN1269203C - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
- Publication number
- CN1269203C CN1269203C CN200410005497.2A CN200410005497A CN1269203C CN 1269203 C CN1269203 C CN 1269203C CN 200410005497 A CN200410005497 A CN 200410005497A CN 1269203 C CN1269203 C CN 1269203C
- Authority
- CN
- China
- Prior art keywords
- mentioned
- illusory
- semiconductor device
- groove
- width dimensions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 238000000034 method Methods 0.000 title claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 238000002955 isolation Methods 0.000 claims abstract description 17
- 239000012212 insulator Substances 0.000 claims abstract description 5
- 238000004519 manufacturing process Methods 0.000 claims description 28
- 238000000926 separation method Methods 0.000 claims description 10
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical class O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 claims description 8
- 238000000151 deposition Methods 0.000 abstract description 3
- 238000003801 milling Methods 0.000 description 22
- 238000000227 grinding Methods 0.000 description 17
- 238000005530 etching Methods 0.000 description 8
- 150000004767 nitrides Chemical class 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000003628 erosive effect Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- RKTYLMNFRDHKIL-UHFFFAOYSA-N copper;5,10,15,20-tetraphenylporphyrin-22,24-diide Chemical compound [Cu+2].C1=CC(C(=C2C=CC([N-]2)=C(C=2C=CC=CC=2)C=2C=CC(N=2)=C(C=2C=CC=CC=2)C2=CC=C3[N-]2)C=2C=CC=CC=2)=NC1=C3C1=CC=CC=C1 RKTYLMNFRDHKIL-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000036962 time dependent Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
Claims (8)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003052844A JP2004265989A (ja) | 2003-02-28 | 2003-02-28 | 半導体装置の製造方法 |
JP2003052844 | 2003-02-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1525548A CN1525548A (zh) | 2004-09-01 |
CN1269203C true CN1269203C (zh) | 2006-08-09 |
Family
ID=32905750
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200410005497.2A Expired - Fee Related CN1269203C (zh) | 2003-02-28 | 2004-02-19 | 半导体装置及其制造方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US7034367B2 (zh) |
JP (1) | JP2004265989A (zh) |
CN (1) | CN1269203C (zh) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005153236A (ja) * | 2003-11-21 | 2005-06-16 | Teac Corp | レーベル印刷装置 |
JP4795667B2 (ja) * | 2004-11-05 | 2011-10-19 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US7759182B2 (en) * | 2006-11-08 | 2010-07-20 | Texas Instruments Incorporated | Dummy active area implementation |
US7435642B2 (en) * | 2006-11-14 | 2008-10-14 | Powerchip Semiconductor Corp. | Method of evaluating the uniformity of the thickness of the polysilicon gate layer |
WO2008111177A1 (ja) * | 2007-03-13 | 2008-09-18 | Fujitsu Microelectronics Limited | 半導体装置とその製造方法 |
US8633077B2 (en) * | 2012-02-15 | 2014-01-21 | International Business Machines Corporation | Transistors with uniaxial stress channels |
KR102424964B1 (ko) | 2015-09-23 | 2022-07-25 | 삼성전자주식회사 | 반도체 소자 및 그 제조방법 |
CN109461696B (zh) * | 2018-10-15 | 2021-01-01 | 上海华虹宏力半导体制造有限公司 | 一种浅沟槽隔离结构的制作方法 |
CN110739206B (zh) * | 2019-10-25 | 2022-03-11 | 中国科学院微电子研究所 | 一种基板及其制备方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1070187A (ja) * | 1996-08-28 | 1998-03-10 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
TW334614B (en) | 1997-03-04 | 1998-06-21 | Winbond Electronics Corp | The method of forming shallow trench isolation |
KR100475976B1 (ko) * | 1998-12-25 | 2005-03-15 | 히다치 가세고교 가부시끼가이샤 | Cmp 연마제, cmp 연마제용 첨가액 및 기판의 연마방법 |
JP2000349145A (ja) * | 1999-04-02 | 2000-12-15 | Oki Electric Ind Co Ltd | 半導体装置 |
JP4836304B2 (ja) | 1999-12-15 | 2011-12-14 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
-
2003
- 2003-02-28 JP JP2003052844A patent/JP2004265989A/ja active Pending
-
2004
- 2004-02-19 CN CN200410005497.2A patent/CN1269203C/zh not_active Expired - Fee Related
- 2004-02-20 US US10/781,809 patent/US7034367B2/en not_active Expired - Lifetime
-
2006
- 2006-03-06 US US11/367,556 patent/US20060145268A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US7034367B2 (en) | 2006-04-25 |
CN1525548A (zh) | 2004-09-01 |
US20040169252A1 (en) | 2004-09-02 |
US20060145268A1 (en) | 2006-07-06 |
JP2004265989A (ja) | 2004-09-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CP01 | Change in the name or title of a patent holder |
Address after: Osaka, Japan Patentee after: Panasonic Holding Co.,Ltd. Address before: Osaka, Japan Patentee before: Matsushita Electric Industrial Co.,Ltd. |
|
CP01 | Change in the name or title of a patent holder | ||
TR01 | Transfer of patent right |
Effective date of registration: 20230104 Address after: California, USA Patentee after: Pannovasemec Co.,Ltd. Address before: Osaka, Japan Patentee before: Panasonic Holding Co.,Ltd. |
|
TR01 | Transfer of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20060809 |
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CF01 | Termination of patent right due to non-payment of annual fee |