CN1235700A - 半导体封装用芯片支持基片、半导体装置及其制造方法 - Google Patents

半导体封装用芯片支持基片、半导体装置及其制造方法 Download PDF

Info

Publication number
CN1235700A
CN1235700A CN97199380A CN97199380A CN1235700A CN 1235700 A CN1235700 A CN 1235700A CN 97199380 A CN97199380 A CN 97199380A CN 97199380 A CN97199380 A CN 97199380A CN 1235700 A CN1235700 A CN 1235700A
Authority
CN
China
Prior art keywords
semiconductor chip
mentioned
insulating properties
adhesive member
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN97199380A
Other languages
English (en)
Other versions
CN1146984C (zh
Inventor
汤佐正己
加藤利彦
井上文男
市村茂树
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Showa Denko Materials Co ltd
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Publication of CN1235700A publication Critical patent/CN1235700A/zh
Application granted granted Critical
Publication of CN1146984C publication Critical patent/CN1146984C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01045—Rhodium [Rh]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Die Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Micromachines (AREA)

Abstract

在本发明的芯片支持基片中,把绝缘性膜状粘接构件帐篷状地贴到布线上边,设有与通气孔相连的空隙。若用该芯片支持基片,则由于不损害通气孔的功能,而且,在软化时从绝缘性膜状粘接构件中发生的气体和水蒸气,还可以确实地放出到封装外边,故可以防止封装产生裂缝,可以制造可靠性高的小型半导体封装。

Description

半导体封装用芯片支持基片、 半导体装置及其制造方法
技术领域
本发明涉及半导体封装用芯片支持基片、该基片的制造方法，使用该基片的半导体装置和该半导体装置的制造方法。
背景技术
随着半导体集成度的提高，输入输出端子数不断增加。因此，具有许多输入输出端子数的半导体封装就变得需要起来。一般说，输入输出端子有两种类型：一种其输入输出端子成列地配置在封装的周边，一种则不仅在周边，在内部也配置多列。
在前者中QFP(Quad Flat Package，方形扁平封装)是代表性的封装。在使它多端子化的情况下，就必须缩小端子节距。但是，在0.5mm以下的区域，与布线之间的连接就需要高级的技术。后者的阵列型，由于可以以比较大的节距配置端子，故适合于多端子化。作为阵列型，以往一般是具有连接引脚的PGA(Pin Grid Array，网格插针阵列)，它与布线板之间的连接是插入式，不适合于表面贴装。因此，开发出了可以进行表面贴装的被称之为BGA(Ball Grid Array,网格焊球阵列)的封装。
另一方面，随着电子机器的小型化，封装尺寸的进一步小型化的要求日益强烈。作为与这种小型化相对应的封装，人们提出了与半导体芯片大体上同等尺寸的所谓芯片尺寸封装(CSP；Chip SizePackage)。这是一种不仅在半导体芯片的周边部分，在装配区域内也有与外部布线基片之间的连接部分的封装。作为具体例子，有在把带凸点的聚酰亚胺膜粘接到半导体芯片的表面上，并用金引线与芯片电连后，铸封环氧树脂等进行密封的封装(NIKKEI MATERIALS&TECHNOLOGY 94.4,No.140,p18～19)或在临时基片上的相当于半导体芯片与外部布线基片之间的连接部分的位置上形成金属凸点，使半导体芯片面朝下地键合后，在临时基片上进行传输模铸的封装(Smallest Flip-Chip-Like Packaging Workshop of Japan,p46～50,1994)等。
但是，以往提出的半导体封装的大多数，并不能说是小型、可以应付高集成度，而且防止封装产生裂缝，可靠性好和生产性优良的封装。
发明的公开
本发明的目的是提供一种可以制造防止封装发生裂缝且可靠性优良的小型半导体封装的半导体封装用芯片支持基片、使用该基片的半导体装置和它们的制造方法。
本发明的半导体芯片用支持基片是这样一种半导体芯片用支持基片：
    A、在绝缘性支持基片的一个表面上，有2个以上的具有
半导体芯片装载部分的布线，
    在把半导体芯片装载到该布线的半导体芯片装载部分上
去时，配置并形成为使得上述半导体芯片的下表面部分和上
述布线的端面和上述绝缘性支持基片的上述表面之间形成空
隙，
    B、在面朝上述绝缘性支持基片的上述空隙的部位上，至
少形成一个贯通孔，
    C、包括上述布线的半导体芯片装载部分在内，在装载半
导体芯片的半导体芯片装载部分上形成了绝缘性膜状粘接构
件，
其特征是：
至少在半导体芯片通过上述绝缘性膜状粘接构件进行装载的阶段，上述绝缘性膜状粘接构件，是Tg(玻璃化转变温度)100℃以上，残存挥发量2.0％(重量/重量)以下的绝缘性膜状粘接构件。
在本发明中，既可以在半导体芯片装载区域部分形成Tg100℃以上，2.0％(重量/重量)以下的绝缘性膜状粘接构件，也可以在半导体芯片装载区域部分形成Tg80℃以上，残存挥发量15.0％(重量/重量)以下的绝缘性膜状粘接构件，并在通过上述绝缘性膜状粘接构件装载半导体芯片的阶段之前的阶段，对上述绝缘性膜状粘接构件施行加热处理，使上述绝缘性膜状粘接构件变成为Tg100℃以上，残存挥发量2.0％(重量/重量)以下的绝缘性膜状粘接构件。
本发明的半导体封装用芯片支持基片的理想的实施方案，是这样一种基片：
    A′、在绝缘性支持基片的一个表面上，至少已形成了2
条布线，该布线具有用于和半导体芯片电极进行连接的内部
连接部分和半导体芯片装载部分，
    上述布线，在把半导体芯片装载到该布线的半导体芯片
装载部分上去时，被配置为使绝缘性膜状粘接构件的绝缘性
支持基片相向面和上述布线的端面和上述绝缘性支持基片之
间形成空隙，
    B′、在上述绝缘性支持基片上，在既是形成上述绝缘性
支持基片的上述布线的部位又是设置与上述内部连接部分导
通的外部连接部分的部位上设有开口部分，
    C′、在上述绝缘性支持基片上，在面朝上述空隙的部位，
至少形成一个贯通孔，
    D′、包括上述布线的半导体芯片装载部分在内，在装载
半导体芯片的半导体芯片装载部分上形成了绝缘性膜状粘接
构件，
其特征是：
至少在半导体芯片通过上述绝缘性膜状粘接构件进行装载的阶段，上述绝缘性的膜状粘接构件，是Tg100℃以上，残存挥发量2.0％(重量/重量)以下的绝缘性膜状粘接构件。
此外，在本发明中，还提供具备下述(1)～(3)的各个工序的半导体芯片用芯片装载基片的制造方法。
(1)在绝缘性支持基片上形成贯通孔的工序；
(2)在上述绝缘性支持基片的一个表面上，在把半导体芯片装载到该布线的半导体芯片装载部分上时，把具有半导体芯片装载部分的2个以上的布线配置并形成为使得半导体芯片下表面部分和上述布线的端面和上述绝缘支持基片的上述表面之间，形成连接到至少一个上述贯通孔上的空隙的布线形成工序；
(3)包括上述布线的半导体芯片装载部分在内，在装载半导体芯片的半导体芯片装载部分上，形成具有上述特性的绝缘性膜状粘接构件的粘接层形成工序。
本发明中的粘接层(绝缘性膜状粘接构件)，也可以采用例如把具备上述特性(即玻璃化转变温度100℃以上，残存挥发量2.0％(重量/重量)以下)的绝缘性膜状粘接构件贴到半导体芯片装载部分上的办法形成，也可以采用先把玻璃化转变温度80℃以上，残存挥发量15.0％(重量/重量)以下的绝缘性膜状粘接构件预先形成(例如用粘贴膜的办法)在半导体芯片装载部分上，在半导体芯片装载前进行加热处理使该绝缘性膜状粘接构件具备上述特性的办法形成。
另外，在粘接层形成工序包含粘贴绝缘性膜状粘接构件的工序的情况下，从作业性的观点来看，希望要粘贴的绝缘性膜状粘接构件是自我支持性膜。
此外，在本发明中，可以提供具备本发明的芯片支持基片、已装载到该芯片支持基片的半导体芯片装载区域上的半导体芯片和密封该半导体芯片的密封构件的半导体装置，以及该半导体装置的制造方法。
作为在本发明中应用的绝缘性支持基片，可以举出由聚酰胺、环氧树脂或聚酰亚胺等的塑料构成的薄膜，或把聚酰胺、环氧树脂或聚酰亚胺等的塑料含浸于玻璃无纺布中使之硬化后的基片。
要想在绝缘性支持基片的一个表面上形成具有半导体芯片装载部分的布线，可以使用腐蚀铜箔法、在规定的部位镀铜的方法和同时使用二者的方法等。
要想在绝缘性支持基片上设置外部连接部分和贯通孔等的开口部分，可以用钻孔加工或冲孔等的机械加工，或者准分子激光或二氧化碳气体激光等的激光加工等方法进行。此外还可以用在有粘接性的绝缘基材上预先设置开口部分，再把它和铜箔等的布线形成用金属箔粘贴起来的方法、在带铜箔或者预先形成了布线的绝缘基材上设置开口的方法、或同时使用二者的方法等。与内部连接部分导通的外部连接部分，可以采用在绝缘性支持基片开口部分上，用焊料球或电镀等形成凸点的办法制作。外部连接部分连接到外部的基片上。
布线和半导体芯片电极的电连方法，可以用使半导体芯片面朝下地装载到半导体芯片装载部分上，用金属丝键合技术把半导体芯片电极和设于上述布线上的内部连接部分连接起来的方法，或使半导体芯片面朝下地装载到半导体芯片装载部分上，再把把半导体芯片电极和设于上述布线上的连接端子连接起来的方法等进行。
要想把绝缘性支持基片连接到外部，可以用下述方法进行：在绝缘性支持基片的已经形成了布线的部位设置开口，通过该开口，在与绝缘性支持基片的已经形成了布线的面相对的面上，设置与布线电连的外部端子等。
绝缘性膜状粘接构件上，可以使用单层的膜，或在由聚酰胺、环氧树脂或聚酰亚胺等构成的塑料薄膜上单面或两面涂上粘接剂的粘接构件。
作为绝缘性膜状粘接构件，例如，有使用下述通式(1)表示的4碳酸2无水物的含量为全4碳酸2无水物的70摩尔％以上的4碳酸2无水物与二(元)胺进行反应得到的聚酰亚胺树脂、或者由环氧树脂等的热硬化性树脂构成的膜状粘接构件。此外在该构件中还可以含有由二氧化硅、氧化铝等的无机物质构成填料。………(1)
(其中，n表示n=2～20的整数)
具备本发明的芯片支持基片的绝缘性膜状粘接构件，在半导体芯片通过上述绝缘性膜状粘接构件进行装载的阶段，是Tg在100℃以上，残存挥发量2.0％(重量/重量)以下的绝缘性膜状粘接构件。
由于在通过上述绝缘性膜状粘接构件装载半导体芯片的阶段，使Tg在100℃以上，残存挥发量2.0％(重量/重量)以下，故例如既可以粘贴Tg在100℃以上，残存挥发量2.0％(重量/重量)以下的绝缘性膜状粘接构件，也可以在形成Tg80℃以上，残存挥发量15.0％(重量/重量)以下的绝缘性膜状粘接构件，并把它粘贴到基片上之后，在通过上述绝缘性膜装载半导体芯片的阶段之前的阶段，对该绝缘性膜施行加热处理。
在绝缘性支持基片的将变成为面朝上述空隙的部位上，至少要形成一个以上的贯通孔。孔径并不特别重要，但理想的是0.05毫米以上1.000毫米以下。其位置也没什么特别限制，但理想的是尽量均等地配置多个，这些孔径和配置，可以根据布线图形进行选择。
使用本发明的半导体封装用芯片支持基片制造半导体封装，首先，把半导体芯片装载到本发明的半导体芯片封装用芯片支持基片的绝缘性膜状粘接构件面上。这时，也可以同时使用膏状的管芯粘接剂。其次，用金属丝键合技术把半导体芯片电极连接到支持基片的内部连接部分上。再对半导体芯片的至少是半导体芯片电极面进行树脂密封，再把焊料球装载到外部连接部分上，用这种办法可以制造半导体封装。
附图的简单说明
图1的剖面图示出了用来说明本发明的实施例的半导体封装的制造工序。
优选实施例
管芯粘接膜形成例
(1)聚酰亚胺的合成
向具备温度计、搅拌机、氮气导入管和干燥管的1000ml的4个烧瓶内，加入2,2(4-氨基苯氧基苯基)丙烷(以下，简称为BAPP)41g(0.1摩尔)和N-甲基-2-吡咯烷酮374g，使之溶解。
BAPP溶解后，在水浴中冷却全部烧瓶，边激烈地搅拌边每次少量地添加十亚甲基双三苯六甲酸酯二酸酣52.2g(0.1摩尔)。保持原状不变，在水浴中，在氮气气流下搅拌6小时使之反应，得到聚酰胺酸溶液。
向该聚酰胺酸溶液中加入二甲苯250g，在170～180℃下边吹氮气边与水一起共沸除去二甲苯，进行亚胺化。在反应结束后，向水中注入反应液，用过滤法得到沉淀后的聚合物，进行干燥后，得到聚酰亚胺A。
(2)环氧树脂溶液的调制
把环氧树脂、酚醛树脂和催化剂以表1所示的量进行混合，调制环氧树脂溶液1～3。
表1
Figure A9719938000101
R-170；双酚AD型环氧树脂
EXA-830：双酚F型环氧树脂
ESCN-195：甲酚酚醛型环氧树脂
EPPN-502：水杨基乙醛酚醛型环氧树脂
HP-850N：苯酚酚醛型树脂
TPPK：四苯基硼酸四苯基鏻盐
(3)管芯粘接膜的形成
在下述表2所示的配合和干燥条件下制作膜。
表2
 实施例    实施例    实施例    实施例     实施例    比较例   比较例1         2         3         4          5         6        7
 聚酰亚胺A   10g       10g       10g       10g        10g       10g      10g
 环氧树脂溶液   1         1         1         3          1         1        210g       10g       10g       10g        10g       10g      10g
 干燥条件   150℃     150℃     120℃     120℃      80℃      120℃    120℃30分      40分      40分      40分       30分      40分     40分
 贴膜后的处理                       150℃                150℃30分                 30分
 膜的Tg   106℃     106℃     104℃     107℃      105℃     97℃     107℃
 残存挥发成分   1.9％     1.2％     1.8％     1.9％      1.3％     2.2％    3.0％
 空隙状态   良好      良好      良好      良好       良好     不合格    不合格
 耐软化性   良好      良好      良好      良好       良好     不合格    不合格
实施例1～5、比较例1～2
用图1对本发明的实施例进行说明。
把聚酰亚胺粘接剂涂到聚酰亚胺膜的两面上。用钻孔加工法在厚度0.07mm的聚酰亚胺键合薄板1上形成将成为外部连接部分的开口部分3和贯通孔(通气孔)9。其次，在粘接厚度为0.018mm的铜箔(日本电解(株)生产，商品名：SLP-18)后，用通常的刻蚀法形成内部连接部分和展开布线2。
对已经露出来的布线，依次施行(未画出)无电解镀镍(膜厚：5微米)和无电解镀金(膜厚：0.8微米)。在这里虽然使用的是无电解电镀，但也可以使用电解电镀。
接着，用冲压模具冲压成膜状，准备已形成了多组的内部连接部分、展开布线、外部连接部分的支持基片(图1(a))。作为支持基片的制作方法，可以是用激光加工，在市售的2层(铜/聚酰亚胺)挠性基片的聚酰亚胺上，形成外部连接部分孔的方法。
其次，把如上述那样地形成的管芯粘接膜4粘接到支持基片的半导体芯片装载区域上(图1(b))。粘接的条件例如定为，温度：160℃，时间：5秒，压力：3kgf/cm2。这时，管芯粘接膜在布线等的金属部分进行粘接，要使得和键合薄板不粘接。
其次，在粘接后的管芯粘接膜上边，用无银膏10(日立化成工业株式会社生产，商品名：EN-4322)，把半导体芯片6粘接到支持基片的规定的位置上，进行180℃,1小时的后处理，使管芯粘接膜和无银膏硬化。这时，在无布线和金属图形的部分处，在管芯粘接膜和键合薄板之间形成与贯通孔连接的空隙10。
此外，用键合金丝5把半导体芯片电极和内部连接部分电连起来(图1(c))。把这样形成的中间产品装填到传输铸模模具中去，用半导体密封用环氧树脂7(日立化成工业(株)生产，商品名：CL-7700)逐个进行密封(图1(d))。然后，把焊料球8配置到将成为外部连接部分的开口部分上使之熔融(图1(e))，使用冲床使各个封装分离，得到半导体封装(图1(f)。
对所得到的封装中的空隙11进行观察的结果，和进行耐软化性试验的结果，示于上述表2。
另外，表2中的‘Tg’是用热机械分析(TMP)，在升温5℃/分、荷重5kg下测定的结果，‘残存挥发量’是对纵横5cm的膜进行200℃/2小时加热，由其前后的重量变化计算出来的。此外，‘耐软化性’是在30℃/75％HR/96小时的条件下吸湿后进行红外线(IR)软化试验，用目视观察外观的胀大，没有胀大的定为良好，有胀大的定为不合格。至于‘空隙’，已形成了空隙的定为良好，没形成空隙的，定为不合格。
工业上利用的可能性
如上所述，在本发明中，采用把绝缘性膜状粘接构件帐篷状地贴到布线上边的办法，不损害通气孔的功能，而且，在软化时从绝缘性膜状粘接构件中发生的气体和水蒸气，还可以确实地放出到封装外边。因此，倘采用本发明，就可以防止封装产生裂缝，就可以制造可靠性高的小型半导体封装。

Claims (6)

1．一种半导体封装用芯片支持基片，该基片具有：
(A)在绝缘性支持基片的一个表面上，有2个以上的具有半导体
芯片装载部分的布线，
在把半导体芯片装载到该布线的半导体芯片装载部分上去时，配置并形成为使得上述半导体芯片的下表面部分和上述布线的端面和上述绝缘性支持基片的上述表面之间形成空隙，
(B)在面朝上述绝缘性支持基片的上述空隙的部位至少形成一个贯通孔，
(C)包括上述布线的半导体芯片装载部分在内，在装载半导体芯片的半导体芯片装载部分上形成了绝缘性膜状粘接构件，
其特征是：
至少在半导体芯片通过上述绝缘性膜状粘接构件进行装载的阶段，上述绝缘性膜状粘接构件，是玻璃化转变温度100℃以上，残存挥发量2.0％(重量/重量)以下的绝缘性膜状粘接构件。
2．一种半导体封装用芯片支持基片的制造方法，具有下述工序：
(1)在绝缘性支持基片上形成贯通孔的工序；
(2)在上述绝缘性支持基片的一个表面上，在把半导体芯片装载到该布线的半导体芯片装载部分上时，把具有半导体芯片装载部分的2个以上的布线配置并形成为使得半导体芯片下表面部分和上述布线的端面和上述绝缘支持基片的上述表面之间，形成连接到至少一个上述贯通孔上的空隙的布线形成工序；
(3)包括上述布线的半导体芯片装载部分在内，在装载半导体芯片的半导体芯片装载部分上，形成绝缘性膜状粘接构件的粘接层形成工序，
上述绝缘性膜状粘接构件，
至少在半导体芯片通过上述绝缘性膜状粘接构件进行装载的阶段，是玻璃化转变温度100℃以上，残存挥发量2.0％(重量/重量)以下的绝缘性膜状粘接构件。
3．权利要求2所述的半导体封装用芯片支持基片制造方法，其特征是：含有把玻璃化转变温度100℃以上，残存挥发量2.0％(重量/重量)以下的绝缘性膜状粘接构件粘贴到上述半导体芯片装载区域部分上的工序。
4．权利要求2所述的半导体封装用芯片支持基片制造方法，其特征是含有下述工序：
在半导体芯片装载区域部分上，形成玻璃化转变温度80℃以上，残存挥发量15.0％(重量/重量)以下的绝缘性膜状粘接构件，
在通过上述绝缘性膜状粘接构件装载半导体芯片的阶段之前的阶段，对上述绝缘性膜状粘接构件施行加热处理。
5．一种半导体装置，其特征是具备：
权利要求1所述的芯片支持基片；
已经装载到上述芯片支持基片的半导体芯片装载区域上的半导体芯片；
密封上述半导体芯片的密封构件。
6．一种半导体装置的制造方法，其特征是顺序具备如下工序：
把半导体芯片装载到权利要求1所述的芯片支持基片的半导体芯片装载区域上的工序；
密封上述半导体芯片的工序。
CNB971993807A 1996-10-30 1997-10-29 半导体封装用芯片支持基片、半导体装置及其制造方法 Expired - Fee Related CN1146984C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP288606/96 1996-10-30
JP288606/1996 1996-10-30
JP28860696 1996-10-30

Publications (2)

Publication Number Publication Date
CN1235700A true CN1235700A (zh) 1999-11-17
CN1146984C CN1146984C (zh) 2004-04-21

Family

ID=17732407

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB971993807A Expired - Fee Related CN1146984C (zh) 1996-10-30 1997-10-29 半导体封装用芯片支持基片、半导体装置及其制造方法

Country Status (9)

Country Link
US (1) US6331729B1 (zh)
EP (1) EP0957518A4 (zh)
JP (1) JP3074187B2 (zh)
KR (1) KR100365050B1 (zh)
CN (1) CN1146984C (zh)
AU (1) AU4725197A (zh)
HK (1) HK1022784A1 (zh)
TW (1) TW398049B (zh)
WO (1) WO1998019338A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103151317A (zh) * 2013-02-21 2013-06-12 日月光半导体制造股份有限公司 半导体封装结构及其制造方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3866033B2 (ja) * 2000-12-14 2007-01-10 シャープ株式会社 半導体装置の製造方法
KR100774840B1 (ko) * 2001-02-02 2007-11-07 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
KR100905786B1 (ko) * 2006-06-29 2009-07-02 주식회사 하이닉스반도체 반도체 소자 및 이를 갖는 반도체 패키지
JP4431901B2 (ja) * 2007-01-19 2010-03-17 セイコーエプソン株式会社 半導体装置
KR100802393B1 (ko) * 2007-02-15 2008-02-13 삼성전기주식회사 패키지 기판 및 그 제조방법
KR101096548B1 (ko) * 2009-11-06 2011-12-20 주식회사 비에스이 멤스 마이크로폰 및 그 제조방법
US8420508B2 (en) * 2010-03-17 2013-04-16 Stats Chippac Ltd. Integrated circuit packaging system with bump contact on package leads and method of manufacture thereof

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4760440A (en) * 1983-10-31 1988-07-26 General Electric Company Package for solid state image sensors
US4835598A (en) * 1985-06-13 1989-05-30 Matsushita Electric Works, Ltd. Wiring board
US5159433A (en) * 1989-04-20 1992-10-27 Sanyo Electric Co., Ltd. Hybrid integrated circuit device having a particular casing structure
US5311059A (en) * 1992-01-24 1994-05-10 Motorola, Inc. Backplane grounding for flip-chip integrated circuit
JPH06188328A (ja) * 1992-12-21 1994-07-08 Matsushita Electric Ind Co Ltd 半導体装置及び半導体装置の組立方法
US5414299A (en) * 1993-09-24 1995-05-09 Vlsi Technology, Inc. Semi-conductor device interconnect package assembly for improved package performance
JPH08250890A (ja) 1995-03-09 1996-09-27 Nec Corp 混成集積回路装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103151317A (zh) * 2013-02-21 2013-06-12 日月光半导体制造股份有限公司 半导体封装结构及其制造方法

Also Published As

Publication number Publication date
EP0957518A4 (en) 2004-06-09
CN1146984C (zh) 2004-04-21
TW398049B (en) 2000-07-11
KR20000052864A (ko) 2000-08-25
WO1998019338A1 (fr) 1998-05-07
AU4725197A (en) 1998-05-22
EP0957518A1 (en) 1999-11-17
JP3074187B2 (ja) 2000-08-07
KR100365050B1 (ko) 2003-02-07
US6331729B1 (en) 2001-12-18
HK1022784A1 (en) 2000-08-18

Similar Documents

Publication Publication Date Title
US11984545B2 (en) Method of manufacturing a light emitting device
CN1298034C (zh) 半导体封装及其制造方法
CN1146985C (zh) 半导体装置和用于半导体装置的布线带
CN1041254C (zh) 三维结构的半导体器件
US9397068B2 (en) Package in package (PiP) electronic device and manufacturing method thereof
CN1272837C (zh) 半导体器件和电路基板
CN1337738A (zh) 用于半导体封装处理的具有可注入导电区的带及其制造方法
CN1416593A (zh) 电子器件封装
CN1238458C (zh) 半导体用粘接膜、带有半导体用粘接膜的导线框及使用了该导线框的半导体装置
JP2000036552A (ja) 半導体装置、及び半導体装置で用いる封止材中の金属分の分取方法
CN109075088A (zh) 半导体装置的制造方法
CN1945805A (zh) 半导体封装方法以及用于半导体封装的载体
CN1146984C (zh) 半导体封装用芯片支持基片、半导体装置及其制造方法
JPH088354A (ja) 半導体装置およびその製法
JP2673764B2 (ja) 樹脂封止型半導体装置
JP3314142B2 (ja) 半導体パッケージの製造方法
JP3259968B2 (ja) 半導体装置の製法
JP3247638B2 (ja) 半導体パッケ−ジ用チップ支持基板、半導体装置及び半導体装置の製造法
JP2922672B2 (ja) 半導体装置の製法
JP3448010B2 (ja) 半導体パッケージ用チップ支持基板
CN2829091Y (zh) 倒装芯片封装体结构
CN1719588A (zh) Bga封装及其制造方法
JP3445895B2 (ja) 半導体パッケ−ジ用チップ支持基板
JP2000114414A (ja) 半導体パッケージおよびその製造方法
CN1722397A (zh) 减少或消除半导体器件布线偏移的方法及用其制造的器件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
REG Reference to a national code

Ref country code: HK

Ref legal event code: GR

Ref document number: 1022784

Country of ref document: HK

C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20040421

Termination date: 20091130