CN1227724C - 图样化的埋入绝缘体 - Google Patents

图样化的埋入绝缘体 Download PDF

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CN1227724C
CN1227724C CNB018202128A CN01820212A CN1227724C CN 1227724 C CN1227724 C CN 1227724C CN B018202128 A CNB018202128 A CN B018202128A CN 01820212 A CN01820212 A CN 01820212A CN 1227724 C CN1227724 C CN 1227724C
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transistor
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CN1479943A (zh
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B·A·陈
A·赫希
S·K·艾耶
N·罗维多
H·－J·沃恩
张英
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Infineon Technologies AG
International Business Machines Corp
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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Abstract

一种图样化的埋入绝缘体在源极及漏极之下形成，其方式为在本体面积上形成一掩模及注入n或p型离子于源极及漏极之形成面积中，之后蚀刻STI及蚀刻掉注入面积。随后，在STI及在蚀刻面积中以共形氧化沉积实施光氧化，因此仅在所希望之处构成埋入之氧化物。

Description

图样化的埋入绝缘体
技术领域
本发明范围为以埋入绝缘体，例如氧化物在选择区域形成而构成集成电路。
背景技术
具有埋入氧化物之电路优点甚为知名，与具有晶体管本体与基板隔离相关之问题，及与所需之长时间以实施注入相关之额外成本均为知名之问题。
在本体接点构成上已作不同计划上之广泛努力，以图缓和此等问题，但问题仍然存在，通常为硅面积之过度消耗。
曾有建议以图样化方式注入氧离子及使晶片受到高温退火，但此举仍然具有与高剂量注入及缺失隔离，及自装置面积之氧气沉淀有关之额外成本问题。
发明内容
本发明关于具有绝缘体仅在晶体管之源极及漏极之下构成之埋入绝缘体之集成电路。
本发明之一特性为以较氧注入所需为少之二级强度之剂量实施掺杂剂种类之注入。
本发明另一特性为在浅沟道蚀刻之后或在浅沟道蚀刻期间之注入面积选择性蚀刻。
本发明另一特性为沉积氧化物于埋入之蚀刻空腔中。
附图说明
图1-5显示新颖方法之各级；
图6-8显示另一方法之各级；
图9显示又一方法之一级。
具体实施方式
参考图1，显示一集成电路之剖面图，其中之P型基板10有一沉积之垫氮/氧化物层15，该电路以抗蚀剂18在将成为晶体管本体之面积上形成图样化，之后以掺杂剂注入，如硼或磷以便在晶体管20下面晶体管之源极/漏极区形成面积32。注入之深度由晶体管设计者按需要设定。如需要较厚之埋入层，而不需注入剂之自然离散结果，注入电压将为可变的以产生理想厚度。掺杂剂之型式不重要，只要其能使硅容易蚀刻。硼可用以构成一P+区，磷可构成n+区。
图2显示在剥去抗蚀剂后之同一面积，图样化抗蚀剂之一新层以限定浅沟道隔离(STI)，及以传统之方向反应离子蚀刻(RIE)方法蚀刻STI。掺杂面积32之边缘现在曝露在STI孔隙之壁中并准备蚀刻。精于此技艺者可了解STI系在晶体管面积上构成，在图式之前及后平面延伸。该STI因而在硅基板中限定一组岛，晶体管即在其中构成。
图3显示选择性等向蚀刻之结果，说明HF(49％)∶HNO3(30％)∶CH3COOH(100％)(体积1∶3∶8)。该(易蚀刻)注入面积34已被蚀刻掉，而硅壁仅部分被蚀刻。
图4显示光热氧化之结果，此为钝化STI壁所必需(标称为5nm厚)，随后以保形LPCVD氧化物沉积(即500nm)以氧化物112共形填充蚀刻区36及STI，及以化学-机械(CMP)光以将垫氮化物或硅顶部表面之氧化物平面化。优异的，在STI壁上形成之光氧化多少会施加最小应力于晶体管本体中之硅上。氧化物沉积不会造成任何应力，因为无与其相关之容积扩张。在小空腔中可能形成空白，但其仅能在一般制造容差之内改变少量之电容。无论如何，空白可降低至基板之电容耦合。
图5显示在本体20上构成具有栅极42之最后晶体管。侧壁隔片44，源极-漏极46，第一内层电介质60及接点52已在传统方法下构成。在一具有120nm基本规则说明性方法中，注入面积之水平尺寸为＞200nm，注入之深度为250nm，及面积之厚度为70nm。注入剂量为1×1016/cm2之硼，与1×1018/cm2之氧之说明剂量以构成注入之氧化物。以降低剂量因子100，在晶体管装置层中将较少损害。
传统步骤如覆盖门限调整注入，阱之构成，及退火等均可实施如此技艺中所熟知，在权利要求中将称为”准备该基板”。该电路以额外之晶体管，传统之背端互联，铝或铜以构成理想电路而完成，该电路将被称为“完成该电路”。
继续参考图6-8，其中显示另一实施例之选择步骤。在此情行下，图6对应图2显示与图1相似方法中以硼离子注入该注入面积32’。该示例性剂量为1×1016/cm2，晶片有覆盖注入H，示例性为1×1013/cm2使其构成n-型。
图6亦显示在HF槽中电解之结果。此一方法构成多孔硅区域，其对应注入区域32’，如”SOI结构之多孔硅技术”中所述，该文由SylviaS.Tsao所着，刊于1987，11之IEEE电路及装置月刊之第三页。将STI壁氧化之氧化步骤亦将面积36’共形填充以构成一氧化物区域111。优异的，在电解期间在溶液中之该电解电流及HF浓度需加以选择，使多孔硅区域32’有一密度为45％之整体硅。在此情况下，在氧化物上之扩展将空腔共形填充，导致对附近区域不施加应力之最后埋入氧化物。如必要时，多孔性可设定较高或较低，使埋入之氧化物施加应力或应变于S/D及本体上，以改进隧道中之电子迁移率。
参考图9，其中显示本发明另一实施例，其将图2及3中步骤结合为具有蚀刻方案顺序之单一步骤。在此实施例中，利用卤素化学干蚀刻首先垂直蚀刻该沟道，之后横向蚀刻高度剂量注入区域。掺杂之(n-型)硅可较未掺杂或p-型硅之掺杂快1.3及30倍之间，视掺杂剂种类及浓度与等离子体参数而定。例如，最初垂直蚀刻可利用CL2，HBR，O2及/或He以低处理压力(5-20mTorr)，高RF源功率(250W-600W)及约50W-200W之高RF偏压功率。在垂直蚀刻后，掺杂之n-型区域可用相同之化学及RF源功率蚀刻，但以较高处理压力(20-60mTorr)及低RF偏压功率(0W-20W)用来在水平方向蚀刻(此处称为”无方向”)。其具有对硅基板较佳之蚀刻注入区域之效益，因此，可消除图3所示之分别之等向蚀刻。
本发明以上以三个实施例予以说明，精于此技艺人士应了解本发明可在以下之权利要求精神及范畴内以不同版式实施。例如，绝缘体基板上之SiGe或硅可以使用以取代整体硅；注入亦可在二极管，电容器或第一级互连之下构成；及/或顺序可以改变，注入可在STI蚀刻后成。

Claims (11)

1.一种方法用以构成一集成电路，包含下列步骤：
准备一具有基板表面之半导体基板；
以掺杂剂种类在该基板中注入一组源极/漏极面积以形成一组埋入之掺杂区域；
在该埋入掺杂区域蚀刻STI孔隙，因而限定晶体管区域及曝露在该STI孔隙之壁中之该埋入掺杂区域之一表面；
在等向蚀刻中蚀刻该组埋入掺杂区域以构成埋入之空腔；
以一STI绝缘体共形填充该STI孔隙及该埋入空腔；
构成具有配置在该埋入空腔上方之源极和漏极之晶体管；及
连接该晶体管以构成该集成电路。
2.如权利要求第1项之方法，其中：
该STI绝缘体为LPCVD氧化物。
3.如权利要求第2项之方法，其中：
该掺杂剂种类为硼。
4.如权利要求第2项之方法，其中：
该掺杂剂种类为磷。
5.一种方法用以构成一集成电路，包含下列步骤：
准备一具有基板表面之半导体基板；
以掺杂剂种类注入一组源极/漏极面积于该基板内，以构成一组埋入之掺杂区域；
在埋入之掺杂区域中蚀刻STI孔隙，因而限定晶体管区域及曝露该埋入之掺杂区域之一表面于该STI孔隙之壁中；
用电解在该埋入掺杂区域中构成多孔硅区域；
氧化该STI孔隙之壁及该多孔材料以构成埋入之氧化物区域；
以一STI绝缘体共形填充STI孔隙；
构成具有配置在该埋入空腔上之源极及漏极之晶体管，及配置在源极及漏极间之晶体管本体；
连接该晶体管以形成该集成电路。
6.如权利要求第5项之方法，其中：
该多孔硅区之多孔性为45％，因此该埋入空腔中之埋入氧化物区域实际上未施加应力在该源极、漏极及该晶体管本体。
7.如权利要求第5项之方法，其中：
该多孔硅区域之多孔性小于45％，因此，该埋入空腔中之埋入氧化物区域施加应力在源极、漏极及晶体管本体。
8.如权利要求第5项之方法，其中：
该多孔硅区域有一大于45％之多孔性，因此在该埋入空腔中之该埋入氧化物区域施加应变于该源极、漏极与晶体管本体。
9.如权利要求第1项之方法，其中该蚀刻STI孔隙步骤及蚀刻该埋入掺杂区步骤是以相同蚀刻化学实施。
10.如权利要求第9项之方法，该蚀刻STI孔隙之步骤是以卤基化学、低处理压力及高RF偏压功率实施；及蚀刻该埋入掺杂区之非方向性步骤是以该卤基蚀刻化学、高处理功率及低RF偏压功率实施。
11.如权利要求第10项之方法，其中该蚀刻STI孔隙步骤是以氯基化学，5mTorr至20mTorr范围之处理压力，及50W至200W范围之RF偏压功率实施；及
蚀刻该埋入掺杂区之非方向性步骤是以卤基蚀刻化学，自20mTorr至60mTorr之较高处理压力范围及0W至20W之低RF偏压功率范围实施。
CNB018202128A 2000-12-08 2001-11-29 图样化的埋入绝缘体 Expired - Fee Related CN1227724C (zh)

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US09/733,324 US6429091B1 (en) 2000-12-08 2000-12-08 Patterned buried insulator
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