CN1224235A - 各向异性干腐蚀方法 - Google Patents

各向异性干腐蚀方法 Download PDF

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CN1224235A
CN1224235A CN99100230A CN99100230A CN1224235A CN 1224235 A CN1224235 A CN 1224235A CN 99100230 A CN99100230 A CN 99100230A CN 99100230 A CN99100230 A CN 99100230A CN 1224235 A CN1224235 A CN 1224235A
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原岛启一
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
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    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures

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Abstract

在相对于氧化硅膜、多晶硅膜和硅膜有选择地各向异性地干腐蚀氮化硅膜的方法中,衬底温度被设置在10℃或更低,并且包含氟、碳和氢的复合气体与一氧化碳(CO)相混合的气体被用做反应气体。借助于这种方法,有可能相对于氧化硅膜、多晶硅膜和硅膜的任意一种有选择地各向异性地干腐蚀氮化硅膜。

Description

各向异性干腐蚀方法
本发明涉及各向异性干腐蚀方法,用于相对于氧化硅膜、多晶硅膜和硅膜有选择地各向异性地干腐蚀氮化硅膜。
在干腐蚀氮化硅膜的常规方法中,使用SF6气体,如例如在日本专利申请特许公开No.8-321484中所述那样,以及使用NF3和Cl2等,如例如在日本专利申请特许公开No.6-181190中所述那样。按照这些常规技术,可以相对于氧化硅膜有选择地腐蚀氮化硅膜。但是,由于硅腐蚀速率快,不可能相对于硅膜有选择地腐蚀氮化硅膜。当使用例如CHF3或CF4与H2的混合气体时,可以降低硅的腐蚀速率,并相对于硅有选择地腐蚀氮化硅膜。但是这种混合气体的使用还会导致氧化硅膜的腐蚀速率的增加。因此,相对于硅膜和氧化硅膜二者腐蚀具有高腐蚀选择性的氮化硅膜是困难的。
利用上述背景技术,日本专利申请特许公开No.59-222933和60-115232披露了使用诸如CH2F2和CH3F这样F与H复合比例为2或更小的气体的技术,作为用于相对于硅膜和氧化硅膜有选择地腐蚀氮化硅膜的方法。即,这些参考文献指出,通过使用F与H复合比例为2或更小的气体,可以相对于硅膜和氧化硅膜二者有选择地腐蚀氮化硅膜。
但是具有2或更小F与H复合比例的气体属于爆炸范围,因此有难于控制的缺点。
本发明的目的是提供相对于氧化硅膜、多晶硅膜和硅膜都能有选择地、各向异性地干腐蚀氮化硅膜的各向异性干腐蚀方法。
根据本发明的各向异性干腐蚀方法是用于相对于氧化硅膜、多晶硅膜和硅膜有选择地各向异性地干腐蚀氮化硅膜的方法。根据本发明的各向异性干腐蚀方法的特征在于,衬底温度被设置在10℃或更低,包含氟、碳和氢的复合气体与一氧化碳的混合气体被用做反应气体。
在该各向异性干腐蚀方法中,最好包含氟、碳和氢的复合气体是从CHF3、CF4和C2F6构成的组中选择的至少一种气体与氢气的混合气体,或者是CHF3气体。而且,最好CO气体与反应气体的总气体流量的混合比例的体积百分比是70到95。
根据本发明,不需要特别地将诸如CH2F2和CH3F这样的具有F与H复合比例为2或更小的简单气体作为包含氟、碳和氢的复合气体来使用。因此,本发明不受F与H复合比例的限制。
图1是示出衬底温度和各膜的腐蚀速率之间关系的曲线图,用以说明本发明的原理;
图2是按步骤的顺序示出将本发明用于接触孔腐蚀的实施例的剖视图;以及
图3是按步骤的顺序示出将本发明用于沟槽腐蚀的实施例的剖视图。
现在将参照附图详细描述本发明的实施例。首先将说明氮化硅膜以及氮化硅膜相对于其它氧化硅膜及硅膜的腐蚀选择性。图1是示出衬底温度和各膜的腐蚀速率之间关系的曲线图,横轴表示衬底温度,纵轴表示膜腐蚀速率。使用平行板干腐蚀系统(parallel plate dry etching system)测量腐蚀速率。将CHF3用作含有气态氟、碳和氢的复合气体。将CHF3和CO气体的混合气体用作反应气体,在改变衬底温度的同时对氮化硅膜、多晶硅膜和氧化硅膜的腐蚀速率进行测量。在按照惯例已经进行了腐蚀的50℃到100℃的衬底温度下,氮化硅膜的腐蚀速率慢,不可能相对于特别是氧化硅膜来有选择地腐蚀氮化硅膜。随着衬底温度的下降,氮化硅膜的腐蚀速率迅速增大。多晶硅膜和氧化硅膜的腐蚀速率稍有增加,而且远慢于氮化硅膜的腐蚀速率。在50℃或更低的衬底温度下,氮化硅膜的腐蚀速率惊人地增加。在10℃或更低的衬底温度下,氮化硅膜相对于氧化硅膜的腐蚀选择性是5或更大。另外,由于多晶硅膜的腐蚀速率要慢得多,因此有可能以10或更大的腐蚀选择性相对于多晶硅膜来腐蚀氮化硅膜。
氮化硅膜的腐蚀速率随衬底温度的降低而增大的原因被认为是更低的衬底温度使得反应生成物容易产生。换句话说,当加入CO时,氟被以COF的形式除去,并且出现缺少氟的等离子体。此外,随着衬底温度的降低,由附着在衬底上的碳氟化合物气体如CHF2分解或产生的CxHy的量增加。如果是这样,则作为反应生成物的HCN数量增加并被排出,随之而产生的结果是氮化硅膜的腐蚀速率增加。另一方面,当加入CO时,氧化硅膜上F的量变得不足。结果,氧化硅膜的腐蚀速率下降。当加入CO时,多晶硅膜或硅膜上高耐离子轰击性的富碳聚合膜的淀积被加速。由于该淀积的膜保护硅表面,因此多晶硅膜以及硅膜的腐蚀速率被认为较慢。
关于CHF3与CO的混合比例,发现需要以总气体流量的70%或更大的比例加入CO气体,以便产生缺少氟的等离子体,并将氧化硅膜的腐蚀速率抑制到低水平。
下面,将描述根据上述原理而应用本发明的各向异性干腐蚀方法。图2A到2E是按步骤的顺序示出第一实施例的剖视图。在第一实施例中,在将氮化物膜用做停止层的情况下,使用采用本发明的各向异性干腐蚀方法,以便将自对准接触的该氮化物膜去除。
首先,如图2A中所示,在硅衬底1上依次淀积了氧化硅膜2、多晶硅膜3和氧化硅膜4。在形成抗蚀剂(未示出)后,对抗蚀剂进行图形化。通过将抗蚀剂用做掩模,使氧化硅膜2、多晶硅膜3和氧化硅膜4经受各向异性干腐蚀,由此形成电极布线。
接着,如图2B中所示,在整个表面上淀积氧化硅膜5。使氧化硅膜5经受各向异性干腐蚀,由此在导线的侧表面上形成侧壁。
之后,如图2C所示,在整个表面上淀积用做腐蚀停止层的氮化硅膜6,并形成层间绝缘膜7,如BPSG膜。随后,借助于抗蚀剂8形成接触孔图形。
随后,如图2D所示,通过将抗蚀剂8用做掩模,使层间绝缘膜7经受各向异性干腐蚀,并使形成的接触孔9达到这样的程度,即使之到达用做停止层的氮化硅膜6。
然后,如图2E中所示,将暴露于接触孔9内部的氮化硅膜6除去,并在硅衬底1中形成孔。本发明的实施例被用于去除氮化硅膜6。即,同时相对于氧化硅膜5和硅衬底1有选择地腐蚀氮化硅膜6。
换句话说,在10sccm的CHF3气体、90sccm的CO气体、40毫乇的压强、150W的高频(RF)功率和10℃的衬底温度下,腐蚀例如进行90秒。作为腐蚀工艺的结果,接触孔9内的氮化硅膜6被有选择地除去。此时,由于根据本发明可以相对于氧化硅膜5和硅衬底1有选择地腐蚀氮化硅膜,因此氧化硅膜5和硅衬底1被削减的量较少。随后,将导电材料埋入接触孔9中,以便在衬底和上部布线层之间提供延续性。在本例中,利用自对准接触,可以以稳定的方式形成接触孔,而不使电极布线与导电材料短路,并且不需要对硅衬底进行深凿。
图3A到3C是按照步骤的顺序示出本发明第二实施例的剖视图。在本实施例中,本发明被用于在多晶硅接触栓塞上形成沟槽布线的沟槽形成步骤。
首先,如图3A所示,在淀积在硅衬底10上的氧化物膜12中形成多晶硅接触栓塞11。之后,依次淀积用做腐蚀停止层的氮化硅膜13和用做层间膜的氧化硅膜14,并进一步借助于抗蚀剂15形成沟槽布线图形。
然后,如图3B中所示,通过将抗蚀剂15用做掩模,对氧化硅膜14进行各向异性干腐蚀,并使形成的沟槽达到这样的程度,即使之到达用作停止层的氮化硅膜13。
之后,如图3C所示,通过将抗蚀剂15用做掩模,由此去除氮化硅膜13,以便露出多晶硅栓塞11。将本实施例用于氮化硅膜13的去除。即,同时相对于氧化硅膜12和多晶硅栓塞11有选择地腐蚀氮化硅膜13。采用与第一实施例中相同的腐蚀条件。这样,使氮化硅膜13被去除。这里,由于可以相对于氧化硅膜12和多晶硅栓塞11有选择地腐蚀氮化硅膜13,因此氧化硅膜12和多晶硅栓塞11被削减的量较少,并且因此有可能使沟槽的底部平坦化。因此,可以以稳定的方式进行后面的布线形成。
显然,本发明不应局限于上述实施例。在这些实施例中,使用含碳、氢和氟的复合气体与CO的混合气体。可以向混合气体中加入较少量的氧气、稀有气体或氮气,以便提高腐蚀的可除去性。
如至此为止所述的,根据本发明,通过将衬底温度设定在10℃或更低,以及通过将含氟、碳和氢的复合气体与一氧化碳(CO)的混合气体用做反应气体,可以相对于氧化硅膜、多晶硅膜和硅膜的全部对氮化硅膜进行有选择地各向异性干腐蚀。因此,本发明可以实现按惯例难于实现的半导体器件结构。

Claims (8)

1.各向异性干腐蚀方法,包括相对于氧化硅膜、多晶硅膜和硅膜有选择地各向异性地干腐蚀氮化硅膜的步骤,所述腐蚀是在这样的条件下进行的,即衬底温度是10℃或更低,并且包含氟、碳和氢的复合气体与一氧化碳相混合的气体被用做反应气体。
2.如权利要求1的各向异性干腐蚀方法,其特征在于,包含氟、碳和氢的所述复合气体是氢气与由CHF3、CF4和C2F6构成的一组气体中的选择的至少一种气体的混合气体,或者是CHF3气体。
3.如权利要求1的各向异性干腐蚀方法,其特征在于,CO气体与反应气体总气体流量混合的体积百分比是70到95。
4.如权利要求2的各向异性干腐蚀方法,其特征在于,CO气体与反应气体总气体流量混合的体积百分比是70到95。
5.如权利要求1的各向异性干腐蚀方法,其特征在于,从氧气、稀有气体和氮气构成的组中选择的气体被加入到含氟、碳和氢的所述复合气体中。
6.如权利要求2的各向异性干腐蚀方法,其特征在于,从氧气、稀有气体和氮气构成的组中选择的气体被加入到含氟、碳和氢的所述复合气体中。
7.如权利要求3的各向异性干腐蚀方法,其特征在于,从氧气、稀有气体和氮气构成的组中选择的气体被加入到含氟、碳和氢的所述复合气体中。
8.如权利要求4的各向异性干腐蚀方法,其特征在于,从氧气、稀有气体和氮气构成的组的气体被加入到含氟、碳和氢的所述复合气体中。
CN99100230A 1998-01-20 1999-01-19 各向异性干腐蚀方法 Expired - Fee Related CN1113396C (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103779203A (zh) * 2012-10-17 2014-05-07 株式会社日立高新技术 等离子蚀刻方法
CN103779203B (zh) * 2012-10-17 2016-11-02 株式会社日立高新技术 等离子蚀刻方法

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CN1113396C (zh) 2003-07-02
TW440942B (en) 2001-06-16
KR19990067997A (ko) 1999-08-25

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