CN1205667C - 一种无突出物形成的双镶嵌制程的湿式清洗方法 - Google Patents
一种无突出物形成的双镶嵌制程的湿式清洗方法 Download PDFInfo
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Abstract
一种无突出物形成的双镶嵌制程的湿式清洗方法,特指一种两阶段湿式清洗方法,结合一突起物抑制手段,改良的两阶段湿式铜制程清洗方法,包含有几个主要步骤:(1)氧化步骤;(2)铜氧化物蚀刻步骤及(3)突起物抑制手段。利用突起物抑制手段来抑制解离的铜离子经由还原反应累积在第一铜金属导线表面,有效防止铜突起物的发生,又能够干净清洗蚀刻后的双镶嵌结构,具有提高产品的可靠度的功效。
Description
技术领域
本发明是关于一种改良的湿式铜制程的清洗方法,特指一种无突出物形成的双镶嵌制程的湿式清洗方法,即一种两阶段(two-step)湿式清洗方法,结合一突起物抑制手段(extrusion inhibition step),尤其针对铜-低介电常数(low-k)介电层的制程系统。此两阶段湿式清洗方法包含有一温和的氧化步骤,以及随后的氧化物蚀刻步骤,能够有效抑制由于清洗溶剂中存在有大量铜离子而产生的突起物现象。
背景技术
在积体电路发展的初期,铝金属配合二氧化硅介电材料一直是业界在进行金属内连结(interconnect)设计时所采用的标准材料。这样的材料组合,由于具有成熟的蚀刻技术支持,因此一直受到欢迎。其主要缺陷在于:
近年来随着制程线宽的缩小,积体电路技术进化到深次微米(deepsub-micron)时代,加上产品的速度要求等现实因素,传统的铝/二氧化硅内连结系统(Al/SiO2 interconnect system)已显然不再符合新的制程要求与产品规范。取而代之的,是近几年蓬勃发展的铜制程技术配合低介电常数材料作为金属之间的绝缘层。
由于铜金属具有较铝金属低约40%的电阻率,而低介电常数材料则可降低金属导线之间的电容效应,总的说来,即可以降低电子讯号传递时所产生的RC延迟(RC delay),并增加产品运作效能(performance)。常见的低介电常数材料例如FLARETM,SiLKTM以及BCB(一种多孔介电材料)。虽然铜制程配合低介电常数材料具有许多电性上的优势,然而,也存在有许多制程问题需待解决。
首先,蚀刻出双镶嵌结构的过程中会伴随产生一些复杂的有机金属高分子(organometallic polymers)附着于双镶嵌结构的沟渠以及接触窗壁上。这些未知有机金属高分子成分并不容易利用干蚀刻方法去除。
此外,在蚀刻双镶嵌结构的过程中,由于铜不具有如铝金属一般可以形成氧化保护膜来避免受到外界环境的侵蚀,因此接触窗的铜污染问题也一直是亟待改良之处。
传统在完成双镶嵌结构的蚀刻之后,需进行双镶嵌结构的清洗,以有效去除蚀刻过程中的残留物。其中一种方法是利用稀释的含氢氟酸溶液处理;另一种是由联华电子(United Microelectronics Corp.,UMC)以及马特森科技(Mattson Technology Wet Process Division(Exton,Pa.)所研发的方法,利用两阶段湿式清洗处理蚀刻过程中的残留物。此两阶段湿式清洗的第一步是利用一温和的36∶1(v/v)的稀释过氧化氢溶液接触完成蚀刻的双镶嵌结构,同时配合超音波震荡(megasonics irradiation)技术。此稀释过氧化氢溶液中可以另包含有一界面活性剂(surfactant),或者不包含有任何型式的界面活性剂亦可。此第一步骤是用来轻微氧化铜导线表面,并且移除部份的高分子残留物,以及去除溅镀到接触窗壁上的铜原子。此两阶段湿式清洗的第二步是利用一温和的铜氧化物蚀刻步骤,将铜导线表面的薄氧化层(其成分为CuOx以及Cu(OH)2)完全剥离去除,同时去除所有的高分子残留物。在此第二步骤中所使用的蚀刻液一般包含有HF、NH4F或NH2OH存在于一酸性环境中。
参阅图1所示,图1显示制作于一硅基底10上的蚀刻后双镶嵌结构(post-etch dual damascene structure)30在完成清洗之后的剖面示意图。现以前述的两阶段清洗制程为例,图1中的镶嵌结构30暴露出一部份面积的第一层铜金属导线22及24,其中第一层金属导线22是通过一钨插塞16与形成于硅基底10中的P+掺杂区域12电连接,第一层金属导线24是通过一钨插塞18与形成于硅基底10中的N+掺杂区域14电连接。如此一来,由于硅基底10中的P-N电位差异,造成在含有离子的清洗溶液中,第一层金属导线24扮演了阴极的角色,而第一层金属导线22则扮演了一个阳极的角色。结果是铜氧化物,如Cu(OH)2,在酸性环境中氧化,并且解离出大量的铜离子在清洗溶液中,反应方程式(1)如下:
形成铜导线凹陷13,接着此铜离子又在扮演阴极的第一层金属导线24表面发生还原反应,反应方程式(2)如下:
并且沉积于第一层金属导线24表面,形成铜突起物(copperextrusion)15。
由此可知,虽然传统的两阶段铜制程清洗方法能够有效去除残留物,然而却又产生另一问题,即是铜突起物现象。这个现象是由于在两阶段清洗制程中的第二步骤中,溶液中发生氧化还原反应,而与硅基底10电连结的第一层金属导线24则在此氧化还原反应中扮演了阴极(cathode)的角色。
发明内容
本发明的主要目的是提供一种无突出物形成的双镶嵌制程的湿式清洗方法,通过改良的双镶嵌结构蚀刻后的清洗方法,达到铜导线上无突起物现象的目的。
本发明的目的是这样实现的:一种无突出物形成的双镶嵌制程的湿式清洗方法,包含有下列几个主要步骤:
(1).提供一半导体芯片,其包含有一硅基底以及一蚀刻后(post-etch)双镶嵌结构,该蚀刻后双镶嵌结构包含有一接触窗(via)构造以及一沟渠(trench)构造形成于该接触窗构造之上,其中该接触窗构造暴露出一部份面积的第一层铜金属导线,且该第一层铜金属导线与一形成于该硅基底的N+掺杂区域电连接;
(2).利用一稀释过氧化氢溶液清洗该半导体芯片,以轻微氧化该暴露出来的该第一层铜金属表面;
(3).利用一铜氧化物清洗溶剂洗去形成于该第一层铜金属导线表面上的铜氧化物,其中该铜氧化物清洗溶剂包含有HF、NH4F或NH2OH;
(4).提供一突起物抑制手段,以抑制发生在该第一层铜金属导线表面上的铜还原反应。
该突起物抑制手段是利用一惰性气体吹除(purging)方式,将惰性气体传送至该半导体芯片表面,使利用该稀释过氧化氢溶液清洗该半导体芯片的过程中,能够处于一氧化力较低的环境中。
该突起物抑制手段是利用在该稀释过氧化氢溶液加入一铜腐蚀抑制剂(Cu corrosion inhibitor),例如苯并三唑(benzotriazole;BTA),以达到抑制发生在该第一层铜金属导线表面上的铜突起物形成的功效。
该突起物抑制手段是利用降低稀释过氧化氢溶液的过氧化氢浓度至100∶1(v/v),以达到抑制发生在该第一层铜金属导线表面上的铜突起物形成的功效。
该突起物抑制手段是利用降低稀释过氧化氢溶液的温度至低于15℃,以达到抑制发生在该第一层铜金属导线表面上的铜突起物形成的功效。
该突起物抑制手段是利用提高该铜氧化物清洗溶剂的pH值至7以上,,以达到抑制发生在该第一层铜金属导线表面上的铜突起物形成的功效。
下面结合较佳实施例和附图进一步说明。
附图说明
图1为传统方法清洗的双镶嵌结构的剖面示意图。
图2为本发明方法的双镶嵌结构的剖面示意图。
图3为本发明方法的突起物抑制手段的流程示意图。
具体实施方式
参阅图2-图3所示,图2显示本发明的一种改良的蚀刻后湿式清洗效果的双镶嵌结构90示意图。此双镶嵌结构90是由一般的双镶嵌制程形成,配合低介电常数材料层72,用来连结第一层铜金属导线层92及94。此处所谓低介电常数一般是指介电常数(k)小于3的介电材料,其涵盖范围包含有机介电材料及无机介电材料,可以利用旋涂法(spin-on)或化学气相沉积(chemical vapor deposition,CVD)技术形成。
其中无机类低介电常数材料包括有掺杂硅氧物(doped oxide):氟原子掺杂(F-doped)称为氟硅玻璃(fluorinated silicon glass,FSG);氢原子掺杂(H doped)称为HSQ;碳氢掺杂(C and H doped)称为MSQ(methylsilsesquioxane)、黑钻石(black diamond)材料、Coral以及多孔硅玻璃(porous silica)等等。
有机低介电常数材料则包含有不定形氟碳高分子(amorphousfluorocarbon polymers)、聚酰亚胺是高分子(fluorinated polyimide)、铁氟龙(PTFE)、poly(arylene ether)、benzocyclobutene、SilkTM以及FLARETM等等。
如图2所示,双镶嵌结构90的特征在于氮化硅蚀刻停止层82的应用,以及用来定义低介电常数材料层72图案的氧化硅屏蔽84。每一双镶嵌结构包括有一沟渠以及一接触窗形成于沟渠之下。接触窗暴露出一部份面积的第一铜金属导线92以及94。在完成双镶嵌结构的蚀刻之后,接触窗以及沟渠侧壁会残留可能含有C、O、Si、Cu或N元素成分的金属高分子残留物,需以湿式方式清洗。如前所述,以传统方法清洗的问题在于与硅基底60中的N+掺杂区域64经由钨插塞68电连接的第一铜金属导线94,会在清洗制程后发现铜导线突起现象。另一方面,第一铜金属导线92则由于经由钨插塞66电连接硅基底60中的P+掺杂区域62,而在清洗制程中扮演类似阳极的角色。
此外,在蚀刻接触窗的过程中,需要使用含有CH2F2/Ar/O2的干蚀刻气体,以移除接触窗底部(via bottom)的氮化硅蚀刻停止层82。如此一来,造成电荷(charge)容易累积(accumulate)在经过蚀刻后的接触窗底部位置,使后续进行的湿式清洗程序,在一酸性环境下,加速铜导线的氧化还原反应,形成一导线凹陷一突起现象。
为了解决由于还原反应造成的铜导线突起问题,本发明方法提供一突起物抑制手段,以抑制可能发生在第一层铜金属导线94表面上的铜还原反应。改良的两阶段湿式铜制程清洗方法包含有下列几个主要步骤:
(1)氧化步骤;
(2)铜氧化物蚀刻步骤;
(3)突起物抑制手段。
其中,氧化步骤是利用一温和的稀释过氧化氢溶液清洗完成蚀刻的双镶嵌结构,可以同时配合超音波震荡(megasonics irradiation)技术。此稀释过氧化氢溶液中可以另包含有一界面活性剂(surfactant),或者不包含有任何型式的界面活性剂亦可。
铜氧化物蚀刻步骤是利用一温和的铜氧化物蚀刻步骤将铜导线表面的薄氧化层(其成分为CuOx以及Cu(OH)2)完全剥离去除,同时去除所有的高分子残留物。在此步骤中所使用的蚀刻液一般包含有HF、NH4F、NH2OH或稀释的HF/HCl。
本发明方法的突起物抑制手段可针对氧化步骤进行,或者可针对铜氧化物蚀刻步骤进行,或者同时针对氧化步骤以及铜氧化物蚀刻步骤进行。突起物抑制手段的主要目的在于防止铜金属经由还原反应累积在第一铜金属导线94表面。
参阅图3所示,图3为流程示意图显示本发明方法的突起物抑制手段。如图3所示,在本发明的较佳实施例中,针对氧化步骤进行的突起物抑制手段有四种选择,这四种选择可以单独使用,或者亦可以合并使用。针对铜氧化物蚀刻步骤进行的突起物抑制手段有一种,可以搭配针对氧化步骤进行的四种突起物抑制手段同时进行。其中针对氧化步骤进行的四种突起物抑制手段包括有:
(1)利用一惰性气体吹除(purging)方式,将惰性气体传送至该半导体芯片表面,使利用该稀释过氧化氢溶液清洗该半导体芯片的过程中,能够处于一氧化力较低的环境中;
(2)在稀释过氧化氢溶液加入一铜腐蚀抑制剂(Cu corrosioninhibitor),例如苯并三唑(benzotriazole;BTA);
(3)降低稀释过氧化氢溶液的过氧化氢浓度至100∶1(v/v)以下;
(4)降低稀释过氧化氢溶液的温度至低于15℃。针对铜氧化物蚀刻步骤进行的突起物抑制手段则是利用提高该铜氧化物清洗溶剂的pH值至7以上,以达到抑制发生在该第一层铜金属导线表面上的铜还原反应的功效。
相较于传统铜制程的湿式清洗技术,本发明方法利用一突起物抑制手段来抑制解离的铜离子经由还原反应累积在第一铜金属导线94表面,因此能够有效防止铜突起物的发生,同时又能够干净清洗蚀刻后双镶嵌结构,提高产品的可靠度。
以上所述仅为本发明的较佳实施例,凡依本发明所做的均等变化与修饰,皆应属于本发明的保护范围之内。
Claims (5)
1、一种无突出物形成的双镶嵌制程的湿式清洗方法,其特征是:它依次包含有下列步骤:
(1)提供一半导体芯片,其包含有一硅基底以及一蚀刻后双镶嵌结构,该蚀刻后双镶嵌结构包含有一接触窗构造及一沟渠构造形成于该接触窗构造之上,其中该接触窗构造暴露出一部份面积的第一层铜金属导线,且该第一层铜金属导线与一形成于该硅基底的N+掺杂区域电连接;
(2)利用一稀释过氧化氢溶液清洗该半导体芯片,以氧化暴露出来的该第一层铜金属导线的表面;
(3)利用一铜氧化物清洗溶剂洗去形成于该第一层铜金属导线表面上的铜氧化物,其中该铜氧化物清洗溶剂包含有HF、NH4F或NH2OH;
(4)提供一突起物抑制手段,以抑制发生在该第一层铜金属导线表面上的铜还原反应;
其中所述突起物抑制手段包括:在以该稀释过氧化氢溶液清洗该半导体芯片的过程中,利用惰性气体吹除该半导体芯片表面的稀释过氧化氢溶液,以降低该稀释过氧化氢溶液的氧化力;
或者利用一铜腐蚀抑制剂苯并三唑添加于该稀释过氧化氢溶液中;
或者降低稀释过氧化氢溶液的温度至低于15℃。
2、根据权利要求1所述的一种无突出物形成的双镶嵌制程的湿式清洗方法,其特征是:该第一层铜金属导线与该硅基底的一N+掺杂区域电连接,在铜氧化物清洗溶剂中具有阴极的作用。
3、一种用于铜制程的湿式清洗方法,其特征是:它包含有如下步骤:
(1)氧化步骤,该氧化步骤是用来氧化第一层铜金属导线表面,且该氧化步骤包含有一稀释过氧化氢溶液的使用;
(2)铜氧化物蚀刻步骤,利用一铜氧化物清洗溶液将该氧化步骤中产生的铜氧化物洗去,该铜氧化物清洗溶液包含有HF、NH4F、NH2OH或稀释的HF/HCl;
(3)至少一突起物的抑制手段,以抑制发生在第一层铜金属导线表面上的铜还原反应;
其中所述突起物抑制手段包括:在该氧化步骤中,利用惰性气体吹除,以降低该稀释过氧化氢溶液的氧化力;
或者利用一铜腐蚀抑制剂笨并三唑添加于该稀释过氧化氢溶液中;
或者降低稀释过氧化氢溶液的温度至低于15℃。
4、根据权利要求3所述的一种用于铜制程的湿式清洗方法,其特征是:该铜氧化物是CuOX。
5、根据权利要求3所述的一种用于铜制程的湿式清洗方法,其特征是:该第一层铜金属导线是电连接一硅基底中的N+掺杂区域。
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TW480619B (en) * | 2001-04-17 | 2002-03-21 | United Microelectronics Corp | Cleaning method for dual damascene manufacture process |
US6794292B2 (en) * | 2001-07-16 | 2004-09-21 | United Microelectronics Corp. | Extrusion-free wet cleaning process for copper-dual damascene structures |
CN1294640C (zh) * | 2003-09-03 | 2007-01-10 | 联华电子股份有限公司 | 介层洞优先双镶嵌制程 |
US20050064701A1 (en) * | 2003-09-19 | 2005-03-24 | International Business Machines Corporation | Formation of low resistance via contacts in interconnect structures |
US20060011224A1 (en) * | 2004-07-18 | 2006-01-19 | Chung-Chih Chen | Extrusion free wet cleaning process |
DE102004037089A1 (de) * | 2004-07-30 | 2006-03-16 | Advanced Micro Devices, Inc., Sunnyvale | Technik zur Herstellung einer Passivierungsschicht vor dem Abscheiden einer Barrierenschicht in einer Kupfermetallisierungsschicht |
US20060046465A1 (en) * | 2004-08-27 | 2006-03-02 | Dongbuanam Semiconductor Inc. | Method for manufacturing a semiconductor device |
CN101235507A (zh) * | 2007-02-02 | 2008-08-06 | 深圳富泰宏精密工业有限公司 | 铍铜合金清洗工艺 |
US8968583B2 (en) * | 2007-07-25 | 2015-03-03 | International Business Machines Corporation | Cleaning process for microelectronic dielectric and metal structures |
CN201219685Y (zh) * | 2008-04-16 | 2009-04-15 | 韩广民 | 组装结构产品及庭院椅 |
CA2740027A1 (en) | 2008-10-09 | 2010-04-15 | Avantor Performance Materials, Inc. | Aqueous acidic formulations for copper oxide etch residue removal and prevention of copper electrodeposition |
JP2010219406A (ja) * | 2009-03-18 | 2010-09-30 | Tokyo Electron Ltd | 化学的機械研磨方法 |
US9679844B2 (en) * | 2015-06-18 | 2017-06-13 | Microchip Technology Incorporated | Manufacturing a damascene thin-film resistor |
US11094527B2 (en) | 2018-10-10 | 2021-08-17 | International Business Machines Corporation | Wet clean solutions to prevent pattern collapse |
US10886166B2 (en) | 2019-03-08 | 2021-01-05 | International Business Machines Corporation | Dielectric surface modification in sub-40nm pitch interconnect patterning |
CN110571134B (zh) * | 2019-08-06 | 2021-10-22 | 成都拓维高科光电科技有限公司 | 一种挡板上钼及其氧化物的清洗工艺 |
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US5213622A (en) * | 1991-10-11 | 1993-05-25 | Air Products And Chemicals, Inc. | Cleaning agents for fabricating integrated circuits and a process for using the same |
US6054061A (en) * | 1997-12-11 | 2000-04-25 | Shipley Company, L.L.C. | Composition for circuit board manufacture |
US6143657A (en) * | 1999-01-04 | 2000-11-07 | Taiwan Semiconductor Manufacturing Company | Method of increasing the stability of a copper to copper interconnection process and structure manufactured thereby |
US6037258A (en) * | 1999-05-07 | 2000-03-14 | Taiwan Semiconductor Manufacturing Company | Method of forming a smooth copper seed layer for a copper damascene structure |
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