CN1221975A - 用于在抛磨后提供改进的平面表面的方法 - Google Patents
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Abstract
公开一种器件的制造工艺,能减小由抛磨引起的凹陷。凹陷减小是由于部分覆盖复杂表面形貌的第一层与覆盖表面形貌的第二层造成的。第二层比第一层更耐抛磨以致在复杂形貌的宽空隙中减小凹陷。
Description
本发明的领域一般涉及到半导体制造以及更具体地涉及到减少在平面化时发生的凹陷。
在器件制造中，在基片上形成绝缘层、半导体层以及导体层。各层被构图，以形成图形(feature)与空隙。图形与空隙的特征尺寸(feature size)(F)或最小尺寸取决于光刻系统的分辨能力。图形与空隙被构图，以形成例如晶体管、电容器、以及电阻器等元器件。这些元器件然后互连，以达到所要求的电气功能，形成集成电路(IC)。
当由于F越来越小而使图形与空隙也减小时，用例如介质材料来填充图形之间的更小的间隙变得越来越困难。为了增强间隙充填，采用了例如硼磷硅酸盐玻璃(BPSG)一类掺杂硅酸盐玻璃。由于掺杂硅酸盐玻璃的相当低的熔点，当其沉积后可以再流动，所以它可以有效地填充间隙。
传统上，BPSG都是由各种化学气相沉积技术(CVD)来形成的。BPSG是在约400℃的相对低的温度下沉积的。沉积之后，基片再被加热到足够高的温度，使玻璃软化并流动。例如，BPSG退火到800℃时就引起玻璃流动并填充图形之间的间隙。
通常，集成电路不同区域具有不同的图案因子(pattem factor)，从而在元器件层的基片表面上建立复杂的形貌图，图案因子定义为构图的面积与未构图的面积之比。例如，在动态随机存取存储器(DRAM)集成电路的阵列区域中的构图密度比在支持或逻辑区域中的构图密度高。正因为如此，在阵列区域中图形之间的间隙比在支持或逻辑区域中的间隙更窄。掺杂硅酸盐玻璃，虽然填充了间隙，但仍是相对保形的。也就是说，下层的基片或元器件层的形貌保留在沉积的掺杂硅酸盐玻璃的形貌中。
沉积后，掺杂硅酸盐玻璃例如用化学机械抛磨(CMP)以提供平面化的表面。高度平面化表面形貌是需要的，因为其允许进行附加集成电路元件的沉积和容许更大的元器件密度。然而，复杂的形貌使得用CMP来取得平面化的表面产生困难。特别是，在宽的空隙中会发生掺杂硅酸盐玻璃的碟化凹陷。这种碟化凹陷反过来又影响到表面平整度，减小了下一道光刻操作的聚焦深度。
从以上讨论可知，就人们需要取得元器件结构的间隙填充，并在CMP时具有减小的碟化凹陷。
本发明涉及器件的制造，特别是，本发明提供了抛磨后改进的表面平整度。在一个实施例中，一第一层敷盖在具有复杂形貌的基片上。第一层的沉积厚度足以填充至少窄的间隙。在第一层介电层上再形成第二层，以填充宽的间隙，第二层比第一层更耐受抛磨。通过提供更抗抛磨层的第二层，在抛磨后表面平整度得以改进。
图1介绍一种说明性的DRAM单元；
图2a-b显示用掺杂硅酸盐玻璃在元器件层中填充间隙的传统操作，其在抛磨后会导致凹陷；以及
图3a-3c显示了根据本发明的实施例减小抛磨后造成凹陷的说明性操作过程。
本发明减小了在半导体制造过程中由于抛磨造成的碟化凹陷(dishing)。为便于本发明的讨论，以DRAM集成电路的形成为内容来予以介绍。但是本发明是有广泛意义的，也可以用于一般的涉及凹陷问题的半导体制造过程中。在讨论本发明前先对DRAM单元以及采用掺杂硅酸盐玻璃作为间隙填充的传统操作过程进行介绍。
参阅图1，显示的是常用的沟槽电容器DRAM单元。这类常用沟槽电容器DRAM单元例如在Nesbit等人“具有自调准隐埋带(BEST)的0.6微米225兆位沟槽DRAM单元”IEDM93-627中已有介绍，在本专利的说明中全都引用。特别是，单元的阵列由字线与位线来互连以形成DRAM芯片。
DRAM单元100包括在基片101中形成的沟槽电容器160。沟槽很典型地是用浓n型掺杂剂掺杂的多晶硅(Poly)来填充的。多晶硅作为电容器的一个极板，称之为“存储节点”。在沟槽的下部四周是由n型掺杂剂掺杂的隐埋极板165。在沟槽的上部是用以减小寄生漏泄的颈部168，节点介质163把电容器的两个极板相隔开。含有n型掺杂剂的隐埋井170用以连接在阵列中DRAM单元的隐埋极板。在隐埋井的上面是p井173，它用来减小垂直漏泄。
DRAM单元还包括晶体管110。晶体管包括有含有n型掺杂剂的栅极112、源极113和漏极114扩散区。晶体管与电容器的连接是通过称之为“节点扩散”的扩散区125来达到的。栅极堆栈(叠层)也称作“字线”，典型地包括多晶硅层366与氮化物层368。可替代的方式是，层357为多晶硅-硅化物层，它包括一层覆于一层多晶硅层之上的硅化物层，例如硅化钼(MoSix)、硅化钽(TaSix)，硅化钨(WSix)，硅化钛(TiSix)或硅化钴(CoSix)，以利于减小字线电阻。在一个实施例中，多晶硅-硅化物层包括覆于多晶硅层上部的WSix。氮化物衬层369覆盖在栅极堆栈与基片上。氮化物368与氮化物衬层369用作下一道操作时蚀刻或抛磨的停止层。
用一个浅沟槽隔离(STI)180来把DRAM单元与其它单元或装置相隔离。如图所示，字线120形成在沟槽之上，并用STI与之隔离。字线120也称之为“通过字线”。这类结构也称之为折叠位线结构。
在字线上方形成一层层间介质层189。在层间介质层之上再形成一层代表位线的导电层。在层间介质层中设有位线接触口186，将源113与位线190接触。
图2a-b显示了具有减小凹陷的填充间隙的常用操作过程。参阅图2a，图示了已部分完成的IC结构100的剖面图。结构100是在半导体基片101上形成的，该基片例如包块一块硅晶片。基片本身就是由结构层一层一层互相堆栈(层叠)而成的。为了讨论，这种结构通常在这里就称之为基片。
为了说明起见，基片表面包括由空隙215与230分开的台面210与212。台面例如在图1所介绍的，代表晶体管的栅极堆栈。栅极堆栈例如又是由在基片上形成的栅极堆栈层并用常用的光刻和腐蚀技术来构图形成的。
IC的元件的尺寸大小一般是变化的。通常，台面或有源区的尺寸大小也会变化。如图所示，台面210是一种窄的图样，台面212是一种宽的图样。此外，在台面之间的空隙也会随尺寸而变化。如图所示，空隙215是相对为窄的，而空隙230则是相对为宽的。但是有源台面与空隙的实际尺寸不是严格的。当需要制造具有高元件密度的IC结构时，窄的台面与空隙典型地相应在大约特征尺寸F左右，而宽的图样则相应地大于特征尺寸F。
掺杂硅酸盐玻璃层250例如BPSG就在基片表面上沉积，用以填充空隙。由于BPSG的保形性，在下层基片上的形貌也同时反映在BPSG层中。
参阅图2b，掺杂硅酸盐玻璃层例如由CMP平面化。CMP抛磨硅酸盐玻璃层，并用台面顶部作为抛磨停止层。结果掺杂硅酸盐玻璃与台面顶部共平面。但是在宽的空隙230中可能发生的掺杂硅酸盐玻璃的过度腐蚀或凹陷，就会在其上形成凹洼261。
根据本发明，提供了一种具有改进抗凹性的间隙填充层。图3a-c显示了本发明的实施例。参阅图3a，显示了部分完成的IC结构300的剖面图。IC结构例如是随机存取存储器(RAM)IC，它包括动态随机存取存储器(DRAM)，同步DRAM(SDRAM)，以及只读存储器(ROM)。其它的IC还可以包括可编程逻辑阵列(PALs)，场可编程门阵列(FPGAs)，专用集成电路(ASICs)，合并DRAM-逻辑IC或其它类型的IC。典型地都是把一组IC并列地形成在晶片上。完成操作处理以后，再把晶片切成小片，把所有IC分成单个的芯片。芯片再进行封装，成为最后的产品，例如可用于诸如计算机系统，蜂窝式电话，个人数字型辅助器(PDA)以及其它电子产品这一类的普通产品。为了便于理解，本发明是以形成IC的内容来进行介绍的。此IC可以处于工艺处理的任何阶段。
结构300是在半导体基片101上形成的。在实施例中，基片包括硅晶片。也可以采用例如砷化镓、锗、绝缘体上的硅(SOI)，玻璃，或其它材料的其它基片。基片例如可以是用预定导电率的掺杂剂轻度或重度掺杂的，以得到需要的电特性。
如图所示，基片包括由窄的和宽的空隙315和330相隔开的窄的和宽的台面310与312。在基片表面上沉淀了第一介质材料层。第一介质层的厚度足以填充窄的间隙315。由于窄的间隙典型地等于特征尺寸F，在一个实施例中的第一介质层的厚度至少是1/2F。第一介质层的厚度应该使得在宽的空隙330中，它应小于台面的高度H。
第一介质层包括掺杂硅酸盐玻璃，例如是BPSG，用以提供充分填充的窄的结构。也可以用例如BSG等具有良好间隙填充特性的掺杂硅酸盐玻璃。掺杂硅酸盐玻璃比不掺杂硅酸盐的优点是具有低的熔点，它可以比不掺杂硅酸盐玻璃所能达到的更低的热估值(thermal budget)来填充窄的间隙。采用大家知道的不同的CVD工艺来沉积不同型式的掺杂硅酸盐玻璃。典型地用CVD沉淀掺杂硅酸盐玻璃并在某温度下退火充分使其流动以填充台面之间的间隙。
掺杂硅酸盐玻璃的掺杂剂浓度影响到它的熔化温度。掺杂剂浓度越高，玻璃的熔化温度越低，反之亦然。典型地，掺杂硅酸盐玻璃的掺杂剂浓度选择在某一给定热估值时能充分地填充窄的间隙。但是，在过高的掺杂剂浓度时掺杂剂也会沉淀出来并形成大的酸晶体(acid crystal)。
在一个实施例中，第一掺杂硅酸盐玻璃层包括BPSG。BPSG的掺杂剂浓度最好低于导致形成表面结晶的浓度。在一个实施例中，B与P的掺杂剂浓度大约小于11％(重量)。
在第一介质层上再沉积第二介质层。第二介质层厚度能充分地完全填充宽的空隙，以使在下一道抛磨程序后在介质层与台面顶面之间形成平整表面。
第二介质层选择比第一介质层具有更低的CMP速率。第二介质层比第一介质层具有更充分抗CMP能力以减小凹陷的发生。第一和第二介质层之间的抛磨选择率在大于1∶1时对于减小凹陷是非常有效的。最好选择率大约是3∶1。如果选择率太高，在宽的空隙中也会发生相反的凹陷效果(也就是宽的空隙变高)。在一个实施例中，第二介质层包括例如TEOS的不掺杂硅酸盐玻璃。
大家知道，CMP速率取决于掺杂硅酸盐玻璃层的掺杂剂浓度。降低掺杂硅酸盐玻璃的浓度就减小了它的CMP速率。在另一个实施例中，第二介质层包括具有比第一介质层为小的掺杂剂浓度的掺杂硅酸盐玻璃。例如，如果第一介质层包含BPSG，而PSG则用作第二介质层。只要第二介质层比第一介质层更抗凹的话，就可能改进抗凹性。
参阅图3b，晶片表面例如用CMP抛磨。CMP对台面的顶部表面具有选择性。作为例示，台面顶部例如可盖以氮化物。这时，CMP对氮化物具有选择性，用它作为抛磨停止层。由于由台面形成的形貌，第二介质层的提高部分370首先被CMP所侵蚀。结果，在留下覆盖在宽的空隙330的第二介质层的同时，CMP首先在区域370中暴露第一介质层。如图所示，CMP在此操作过程中用第一和第二介质层351和352的顶部表面形成相对平面的表面。
参阅图3c，继续CMP。由于第二介质层比第一介质层具有较低的CMP速率，第一介质层就比第二介质层更快地被除去。可以明白，当介质层被抛磨到低于蚀刻停止层(台面顶部)时，更耐CMP的第二介质层就用以减小或防止在宽空隙330中产生凹陷。
我们参照了各种实施例来对本发明进行了专门的显示与介绍，但本领域的技术人员应该认识到对本发明的任何修改或变动都不会超出本发明的范围。本发明范围不仅包含了上述介绍中所有的内容而且也由权利要求以及它的全部等效的内容所覆盖。
Claims (1)
1．一种用于在抛磨后提供改进的平面的表面的方法，包括：
提供具有复杂形貌的基片，其中此形貌包括由窄的空隙与宽的空隙所隔开的图形；
在基片上方形成第一层，第一层充分地填充窄的空隙，而不充分地填充宽的空隙；
在基片上方形成第二层，第二层充分填充宽的空隙，并在抛磨后与图形的顶部提供平面的表面，第二层比第一层更耐抛磨；
抛磨基片表面以与图形顶部形成平面的表面，其中第二层减小了在宽的空隙中的碟化凹陷。
Applications Claiming Priority (2)
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| US08/940,808 US5928959A (en) | 1997-09-30 | 1997-09-30 | Dishing resistance |
| US940808 | 1997-09-30 |
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| Publication Number | Publication Date |
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| CN1221975A true CN1221975A (zh) | 1999-07-07 |
| CN1210765C CN1210765C (zh) | 2005-07-13 |
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| CNB981207251A Expired - Lifetime CN1210765C (zh) | 1997-09-30 | 1998-09-25 | 用于在抛磨后提供改进的平面表面的方法 |
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| US (1) | US5928959A (zh) |
| EP (1) | EP0905755B1 (zh) |
| JP (1) | JPH11162988A (zh) |
| KR (1) | KR100513257B1 (zh) |
| CN (1) | CN1210765C (zh) |
| TW (1) | TW426907B (zh) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103972048A (zh) * | 2014-04-22 | 2014-08-06 | 上海华力微电子有限公司 | 改善层间介质层研磨返工工艺的方法 |
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| US6200896B1 (en) | 1998-01-22 | 2001-03-13 | Cypress Semiconductor Corporation | Employing an acidic liquid and an abrasive surface to polish a semiconductor topography |
| US6271123B1 (en) * | 1998-05-29 | 2001-08-07 | Taiwan Semiconductor Manufacturing Company | Chemical-mechanical polish method using an undoped silicon glass stop layer for polishing BPSG |
| US6232231B1 (en) | 1998-08-31 | 2001-05-15 | Cypress Semiconductor Corporation | Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect |
| US5972124A (en) | 1998-08-31 | 1999-10-26 | Advanced Micro Devices, Inc. | Method for cleaning a surface of a dielectric material |
| US6566249B1 (en) | 1998-11-09 | 2003-05-20 | Cypress Semiconductor Corp. | Planarized semiconductor interconnect topography and method for polishing a metal layer to form wide interconnect structures |
| US6211050B1 (en) * | 1999-03-03 | 2001-04-03 | Chartered Semiconductor Manufacturing Ltd. | Fill pattern in kerf areas to prevent localized non-uniformities of insulating layers at die corners on semiconductor substrates |
| KR100587038B1 (ko) * | 1999-11-04 | 2006-06-07 | 주식회사 하이닉스반도체 | 이중막 실리콘 기판의 제조 방법 |
| US20020072237A1 (en) * | 1999-12-22 | 2002-06-13 | Bowles Christopher Mark | Method for unpatterned resist etch back of shallow trench isolation refill insulator |
| JP2001196559A (ja) * | 2000-01-13 | 2001-07-19 | Seiko Epson Corp | 半導体装置及びその製造方法 |
| JP2001196558A (ja) | 2000-01-13 | 2001-07-19 | Seiko Epson Corp | 半導体装置の製造方法およびその半導体装置 |
| JP2001196560A (ja) | 2000-01-14 | 2001-07-19 | Seiko Epson Corp | 半導体装置及びその製造方法 |
| JP2001196561A (ja) * | 2000-01-14 | 2001-07-19 | Seiko Epson Corp | 半導体装置及びその製造方法 |
| US6319836B1 (en) * | 2000-09-26 | 2001-11-20 | Lsi Logic Corporation | Planarization system |
| US6969684B1 (en) | 2001-04-30 | 2005-11-29 | Cypress Semiconductor Corp. | Method of making a planarized semiconductor structure |
| US6884724B2 (en) * | 2001-08-24 | 2005-04-26 | Applied Materials, Inc. | Method for dishing reduction and feature passivation in polishing processes |
| US6551922B1 (en) | 2002-03-06 | 2003-04-22 | Motorola, Inc. | Method for making a semiconductor device by variable chemical mechanical polish downforce |
| US6828678B1 (en) | 2002-03-29 | 2004-12-07 | Silicon Magnetic Systems | Semiconductor topography with a fill material arranged within a plurality of valleys associated with the surface roughness of the metal layer |
| KR100518233B1 (ko) * | 2003-10-31 | 2005-10-04 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
| US7196012B2 (en) * | 2004-04-13 | 2007-03-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods for planarization of dielectric layer around metal patterns for optical efficiency enhancement |
| US7316976B2 (en) * | 2004-05-19 | 2008-01-08 | Dupont Air Products Nanomaterials Llc | Polishing method to reduce dishing of tungsten on a dielectric |
| JP4819491B2 (ja) * | 2005-11-29 | 2011-11-24 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| KR100731090B1 (ko) * | 2005-12-28 | 2007-06-25 | 동부일렉트로닉스 주식회사 | 반도체 소자의 소자 분리막 형성 방법 |
| KR100784106B1 (ko) * | 2006-09-08 | 2007-12-10 | 주식회사 하이닉스반도체 | 반도체 소자의 금속 배선 형성 방법 |
| US7750470B2 (en) * | 2007-02-08 | 2010-07-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods for planarization of dielectric layer around metal patterns for optical efficiency enhancement |
| US7955964B2 (en) * | 2008-05-14 | 2011-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dishing-free gap-filling with multiple CMPs |
| US8191237B1 (en) | 2009-05-21 | 2012-06-05 | Western Digital (Fremont), Llc | Method for providing a structure in a magnetic transducer |
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|---|---|---|---|---|
| US5356513A (en) * | 1993-04-22 | 1994-10-18 | International Business Machines Corporation | Polishstop planarization method and structure |
| US5362669A (en) * | 1993-06-24 | 1994-11-08 | Northern Telecom Limited | Method of making integrated circuits |
| US5516729A (en) * | 1994-06-03 | 1996-05-14 | Advanced Micro Devices, Inc. | Method for planarizing a semiconductor topography using a spin-on glass material with a variable chemical-mechanical polish rate |
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1997
- 1997-09-30 US US08/940,808 patent/US5928959A/en not_active Expired - Lifetime
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- 1998-09-25 EP EP98118245A patent/EP0905755B1/en not_active Expired - Lifetime
- 1998-09-25 CN CNB981207251A patent/CN1210765C/zh not_active Expired - Lifetime
- 1998-09-28 KR KR10-1998-0040202A patent/KR100513257B1/ko not_active IP Right Cessation
- 1998-09-30 JP JP10278462A patent/JPH11162988A/ja active Pending
- 1998-12-08 TW TW087116259A patent/TW426907B/zh not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103972048A (zh) * | 2014-04-22 | 2014-08-06 | 上海华力微电子有限公司 | 改善层间介质层研磨返工工艺的方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US5928959A (en) | 1999-07-27 |
| EP0905755B1 (en) | 2011-11-02 |
| EP0905755A2 (en) | 1999-03-31 |
| KR100513257B1 (ko) | 2005-10-25 |
| KR19990030190A (ko) | 1999-04-26 |
| EP0905755A3 (en) | 1999-08-18 |
| JPH11162988A (ja) | 1999-06-18 |
| TW426907B (en) | 2001-03-21 |
| CN1210765C (zh) | 2005-07-13 |
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