CN1221029C - 高频半导体装置 - Google Patents
高频半导体装置 Download PDFInfo
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Abstract
一种高频半导体装置,包括:陶瓷基片,包含装于所述陶瓷基片下部的半导体元件与无源元件的元件群,以及为将所述元件群埋没而在所述陶瓷基片下部形成的复合树脂材料层。所述复合树脂材料层由包含环氧树脂与无机充填物的复合树脂材料形成,所述复合树脂材料层的下面呈平坦状,且有外部连接电极形成。采用如射频模块那样的具有接收与发送系统一体化结构的封装,在小型化、高安装密度及散热性等方面性能优良。
Description
技术领域
本发明涉及装有高频半导体元件、控制用集成电路元件及其外围电路的高频半导体装置的结构,具体涉及封装结构。
背景技术
人们越来越希望采用将接收系统与发送系统形成一体的全合一式结构,将主要用于便携式电话等的移动通信设备的高频半导体装置作为射频模块实现模块化。同时,通过装载高频半导体元件、控制用集成电路元件及其外围电路,并纳入将接收系统与发送系统形成一体的系统,在实际被装载的半导体元件与片状元件数量增加的过程中,力求封装件的更加小型化。
文中,参照图10对传统的高频半导体装置作了说明。图10中:1是晶体管等半导体元件;2是陶瓷多层基片;3是片状电阻、片状电容、片状电感等片状元件;4是下部电极;5是金属线;6是粘接树脂;7是金属罩。
用丝网印刷法或金属薄膜刻蚀等方法,在陶瓷多层基片2的表面形成用以装载半导体元件1和片状元件3的元件贴装用焊盘与电极布线图案(未作图示)。半导体芯片1被模片键合(die bonding)在陶瓷多层基片2的元件贴装焊盘上,通过形成于陶瓷多层基片2表面的电极布线图案与金属线5连接。半导体芯片1与金属线5,由粘接树脂6覆盖。另外,片状元件3用焊锡贴装在规定位置上。用以形成封装件的金属罩7装配在陶瓷多层基片2上。陶瓷多层基片2上的表面电极布线图案(未作图示),经由贯穿陶瓷多层基片2的通孔跟下部电极4电气连接。
但是,在如上述的传统高频半导体装置那样,只将半导体元件与片状元件装载于陶瓷多层基片2的结构中,在被实际贴装的元件数量日益增加的过程中,难以充分适应封装件小型化的要求。
并且,为了将作为功率放大器等发热元件的半导体芯片装载在陶瓷多层基片上,采用这样的结构,即半导体芯片产生的热量全部通过陶瓷多层基片传导至下部,通过下部电极来散热。存在的问题是,由于陶瓷多层基片的热阻大,致使大功率半导体芯片不能得到充分散热而处于高温状态。
发明内容
本发明旨在提供更小型化且散热特性改善的高频半导体装置,该装置通过在层叠的基片内一体化地设置包含功率放大器、开关等半导体元件或控制用半导体元件等有源元件,以及电阻、电容、电感、过滤器等无源元件的接收与发送系统,从而因减少布线长度而使其具有低阻抗、低杂散电容、抗噪声等良好的电气特性。
本发明的一种高频半导体装置,包括:陶瓷基片,包含装于所述陶瓷基片下表面的半导体元件与无源元件的元件群,以及为将所述元件群向内部掩埋而在所述陶瓷基片下表面形成的复合树脂材料层;其特征在于:所述复合树脂材料层由包含环氧树脂与无机充填物的复合树脂材料形成;所述复合树脂材料层为对应于所述陶瓷基片形状的平板状,其下面呈涉及所述陶瓷基片整个区域的平坦状,且形成有外部连接用电极;所述外部连接用电极与导电性树脂连接,所述导电性树脂被埋入在所述复合树脂材料层中形成的层间连接构造通孔中。
依据这种结构,在陶瓷基片下部贴装半导体元件与无源元件,可以将基片的下面作为贴装区域使用,从而使贴装密度得到提高。并且,通过用复合树脂材料层埋没元件群,可以提高耐机械震动性与耐湿性等可靠性指标。另外,由于将复合树脂材料层的下面设为平坦表面,其上有外部连接用电极形成,使制品易于搬动、使用,也使高频半导体装置作为模块具有更佳的贴装性能。
所述半导体元件,最好用倒装片接合的方式进行贴装。通过这种贴装方式,因布线长度减少可以实现低阻抗、低杂散电容、高贴装密度以及封装件的扁平化。
上述高频半导体装置可以采用这样的结构:在所述复合树脂材料层中形成由导热系数高于环氧树脂的高热传导树脂材料埋没的层间连接构造,所述外部连接用电极包括充当散热电极的接地电极,所述半导体元件的表面经由所述层间连接构造与所述接地电极连接。这样,半导体元件这种通过倒装片接合贴装的功率放大器等发热元件所产生的热量,可以通过设于一处或多处的层间连接构造经由外部连接用电极而充分散发。
本发明另一结构的高频半导体装置包括:设有电路图案的第一陶瓷基片;装有半导体元件的第二陶瓷基片;以及设置于所述第一陶瓷基片与所述第二陶瓷基片之间将所述半导体元件埋没的复合树脂材料层。所述复合树脂材料层由包含环氧树脂与无机充填剂的复合树脂材料形成;所述第一陶瓷基片的电路图案与所述第二陶瓷基片的电路图案通过所述层间连接构造电气连接。
依据该结构,可将第一陶瓷基片与第二陶瓷基片按照要求的电气特性、热特性、机械特性等分别使用,上述基片隔着复合树脂层相层叠,构成小型的基片封装。即使在第一陶瓷基片与第二陶瓷基片的线膨胀系数相异的情况下,由于基片之间的复合树脂层可以吸收这种差异,仍可提供高可靠性的封装件。并且,除了在第一陶瓷基片与第二陶瓷基片之间可以贴装半导体元件与无源元件之外,还可在第一陶瓷基片的上面贴装元件,这样就提高了制品的整体贴装密度。另外,用复合树脂将半导体元件埋没,可以改善制品的耐机械震动特性、耐湿性等可靠性指标。
这种结构中,所述半导体元件最好采用倒装片连接方式贴装在所述第二陶瓷基片上。这样,就可减少第一陶瓷基片与第二陶瓷基片之间的复合树脂材料层的厚度。并且,因布线长度减少可以实现低阻抗、低杂散电容、高贴装密度以及封装件的扁平化。
并且,所述第二陶瓷基片上贴装的所述半导体元件的一部分,可以用金属线联结。采用这样的结构,第二陶瓷基片上贴装的半导体元件中需要散热的元件用高热传导粘结剂加以固定,通过用金属线与基片联结,半导体元件可以向第二陶瓷基片直接散热。这种结构特别适用于半导体元件发热量大的情况。
在这种结构中,可以用液态环氧树脂将装于所述第二陶瓷基片的、由所述金属线联结的所述半导体元件的周围密封。这样,用复合树脂材料将第一陶瓷基片与第二陶瓷基片粘结时,可以减缓作用于半导体元件与金属线的应力,使金属线的塌陷、断裂等不良现象减少,从而提高装配的合格率。另外,利用将半导体元件密封的环氧树脂充当第一陶瓷基片与第二陶瓷基片之间的隔片,可以对基片之间的间隙进行调整。
本发明又一结构的高频半导体装置包括:下部带凹陷部分的陶瓷基片;包含装于所述凹陷部分底部的半导体元件与无源元件的元件群;为将所述元件群埋没所述凹陷部分而形成的复合树脂材料层;以及在所述陶瓷基片下部所述凹陷部分以外的部分形成的外部连接用电极。所述复合树脂材料层由包含环氧树脂与无机充填剂的复合树脂材料形成,所述复合树脂材料层下部为平坦面。
依据这种结构,跟上述的结构相同,可以提高贴装密度,改善制品的耐机械震动特性、耐湿性等可靠性指标,取得提高贴装性能的效果;同时,可以在凹陷部分充填复合树脂材料,使复合树脂材料层的形成更为容易。
附图说明
【图1】本发明第一实施例中的高频半导体装置的截面图;
【图2】从背面观看的图1的高频半导体装置的透视图;
【图3】本发明第二实施例中的高频半导体装置的截面图;
【图4】本发明第三实施例中的高频半导体装置的截面图;
【图5】从背面观看的图4的高频半导体装置的透视图;
【图6】本发明第四实施例中的高频半导体装置的截面图;
【图7】本发明第五实施例中的高频半导体装置的截面图;
【图8】本发明第六实施例中的高频半导体装置的截面图;
【图9】本发明第七实施例中的高频半导体装置的截面图;
【图10】传统的高频半导体装置的截面图。
具体实施方式
(第一实施例)
图1是本发明第一实施例中的高频半导体装置的截面图;图2是从背面观看的图1的高频半导体装置的透视图。
图1中:1a是作为功率放大器的砷化镓功率半导体元件,1b是作为开关元件的砷化镓半导体元件,1c是电路控制用的硅半导体元件。2是无收缩陶瓷多层基片,其内层设有低温烧结而成的由含金属的糊状材料印制的印刷电阻8和印刷电容9。3是片状元件,它可以是用以微调整高频电路常数的片状电容等元件。5是金属线,10是由环氧树脂与硅等的无机充填剂形成的复合树脂材料层。4是在复合树脂材料层10下部表面形成的导体构成的外部连接用电极。11是在复合树脂材料层10中形成的多个通孔,12是在各通孔11中埋入的导电性树脂。
用以在陶瓷多层基片2的下面装载半导体元件1a、1b、1c的芯片或片状元件的元件贴装用焊盘与电极布线图案(未作图示),用丝网印刷法或金属薄膜刻蚀等方法形成。砷化镓功率半导体元件1a、砷化镓半导体元件1b和硅半导体元件1c,用焊锡等模片键合在陶瓷多层基片2的下表面的元件贴装焊盘部分,用金属线5跟在陶瓷多层基片2的下表面形成的电极布线图案连接。另外,片状电阻、片状电容和片状电感等多个无源元件(未作图示),用焊锡等固定并连接在陶瓷多层基片2下面形成的电路图案上。
半导体元件1a、1b、1c的芯片尺寸一般是这样,功率放大器元件:1.6mm×0.6mm,厚100μm;开关元件:0.8mm×0.6mm,厚150μm;控制用元件:1.0mm×0.7mm,厚300μm。
半导体元件1a、1b、1c与无源元件,由复合树脂材料层10埋没。如图2所示,复合树脂材料层10的下部平坦,电极面也呈平坦状。再如图1所示,有多个层间连接构造通孔11形成于复合树脂材料层10,孔内填入导电性树脂12。层间连接构造通孔11形成位置跟外部连接用电极4的位置相一致。
层间连接构造通孔11的作用在于,将陶瓷多层基片2的下面形成的电路图案引出至外部连接用电极4,以及将半导体元件1a、1b、1c所产生的热量通过陶瓷多层基片2散发。通孔的直径为200μmφ,内部充填含铜糊状材料作为导电性树脂12。片状电阻、片状电容、片状电感等多个片状元件3等用焊锡固定连接在形成于陶瓷多层基片2上面的电极图案上。
高频电路常数由在陶瓷多层基片2的层间形成的印刷电阻8、印刷电容9和埋入复合树脂材料层10的无源元件确定,每个高频半导体装置的高频电路常数可以通过陶瓷多层基片2上面连接的片状元件3进行微调。并且,在陶瓷多层基片2的上面形成的电极图案、印刷电阻8、印刷电容9、在层间形成的电极图案以及下面的电极图案,经由贯通陶瓷多层基片2的通孔实现适当的相互间的电气连接(未作图示)。
复合树脂材料层10的厚度,由实际贴装的半导体元件与无源元件的高度确定。如为半导体元件1a、1b、1c,以金属线5的线环高+300μm的树脂厚度,如为无源元件,以元件高+300μm的树脂厚度;以此为基准再稍作增减加以确定。
陶瓷多层基片2可以由氧化铝基片(高温烧结陶瓷基片:HTCC(High Temperature Cofired Ceramics))和低温烧结陶瓷基片:LTCC(Low Temperature Cofired Ceramics)等形成。氧化铝基片一般指高温烧结陶瓷基片。二者的主要成分均为氧化铝,只是HTCC的氧化铝含量高于LTCC。至于烧结温度,HTCC为1300℃~1500℃,LTCC为800℃~900℃。
复合树脂材料层10,例如可以采用在环氧树脂中添加无机充填材料(主要为二氧化硅,重量的70~80%)以及偶合材料(カップリング材)、颜料与溶剂等,经过混匀后加工成厚度一致的片状材料。偶合材料的作用在于,附着在无机充填材料表面,使它跟环氧树脂的润湿性得到改善。如图1、图2所示,为了将复合树脂材料层10和陶瓷多层基片2接合,将它重叠在贴装了芯片的陶瓷多层基片2上,热压成形。
再有,如为不加溶剂的无溶剂片材,则采用在液态环氧树脂上添加无机充填材料(主要为二氧化硅)的构造。
导电性树脂12一般采用Ag糊剂(在粘结剂中充填银而制成)。在复合树脂材料层10的片材上预先冲孔,然后以印刷方式充填Ag糊剂。复合树脂材料层10的片材重叠在贴装了芯片的陶瓷多层基片2上热压成形后,跟复合树脂材料层10一起硬化。也有采用Cu糊剂的,但是它比Ag糊剂容易氧化。
以上说明的示例中,用硅材料作为复合树脂材料层10的无机充填剂;但是,也可以选用符合要求特性的其他充填材料。例如,在要求高散热性的场合,就有可能采用氧化铝作为充填剂。这样,可以获得充分的散热特性。
形成于复合树脂材料层10背面的外部连接用电极4,由于背面平坦,使这种高频半导体装置模块在工序中易于搬动、使用,也可方便用户的实际贴装。
(第二实施例)
现参照图3所示的高频半导体装置的截面图,对本发明的第二
实施例进行说明。
图3中的装置跟图1所示的第一实施例的不同点在于:砷化镓功率半导体元件1a、砷化镓半导体元件1b以及硅半导体元件1c,经由其芯部为金属的凸块13跟陶瓷多层基片2的下面上的电路图案以倒装片方式连接。
凸块13上,采用金线的SBB(柱球连接(スタッドボ-ルボンディング))方法,半导体元件1a、1b、1c与陶瓷多层基片2的间隙约40μm。设置凸块13的其他方法有:以铜芯材为芯部在四周进行电镀,再用导电性树脂连接的方法;采用ACF(各向异性导电膜)的方法;以及采用焊锡的方法等;它们均可取得相同的效果。跟将半导体元件1a、1b、1c固定在基片上用金属线联结的场合相比,其贴装高度可以低约1/2。本实施例中,密封后的复合树脂材料层10的厚度以芯片高度+300μm为目标。
并且,这样将半导体元件以倒装片方式贴装在陶瓷基片下面,跟用金属线与基片连接相比,可以将半导体元件更接近地设置,且由于基片上面也可贴装元件,可以提高制品的整体贴装密度。
另外,还可以取得因布线减少从而降低阻抗与杂散电容量等方面电气特性的效果。
(第三实施例)
现参照图4所示的高频半导体装置的截面图以及图5所示的从背面观看的图4的高频半导体装置的透视图,对本发明的第三实施例进行说明。
图4中的装置跟图3所示的第二实施例的不同点在于:在作为功率放大器的砷化镓功率半导体元件1a的正下方,形成层间连接构造通孔21;在复合树脂材料层10的下部表面,形成散热用电极14,其位置跟层间连接构造通孔21相一致。如图5所示,复合树脂材料层10的下部表面处,形成多个外部连接用电极4和其面积大于外部连接用电极4的散热用电极14。这样,通过层间连接构造通孔21可有效地进行电极砷化镓功率半导体元件1a的散热。将散热用电极14兼作接地电极,可以适当地实现高频半导体装置的接地电位连接。
层间连接构造通孔21的直径,可以在150μm至500μm的范围内适当选择。所形成的孔数可为一个或多个,其尺寸跟砷化镓功率半导体元件1a的芯片一致。孔内充填(例如)高热传导树脂22。采用跟层间连接构造通孔11用的导电性树脂充填,也可取得同样的效果。
高热传导树脂22,可以采用例如在环氧树脂中充填80~90%重量的二氧化硅而形成的材料。它的导热系数高于环氧树脂,其热传导率为3W/m·K以上。在复合树脂材料层10上形成的通孔(ビァ)21,用印刷方式进行充填。
依据本实施例,在采用以倒装片连接的发热量大的功率半导体元件的场合,可以使半导体元件充分散热。
(第四实施例)
现参照图6所示的高频半导体装置的截面图,对本发明的第四实施例进行说明。本实施例中的高频半导体装置具有一体化结构:陶瓷多层基片2(第一基片)与氧化铝基片32(第二基片),通过它们之间的复合树脂材料层10粘结成一体。
陶瓷多层基片2是一种无收缩基片,其内层装入用含金属糊状材料印刷形成的印刷电阻8与印刷电容9,然后经低温烧结而成。氧化铝基片32上,以倒装片方式贴装了功率放大器、开关等砷化镓半导体元件1a、1b,以及电路控制用硅半导体元件1c。
复合树脂材料层10中,形成用以电气连接陶瓷多层基片2和氧化铝基片32的通孔11,孔内充填导电性树脂12。通孔11的直径为200μm,孔内充填含铜糊状材料。氧化铝基片32内(未作图示),对于氧化铝基片32的表面电极图案,设置用以连接外部连接用电极4与散热用电极14的贯穿孔。
这样,用复合树脂材料层10将多个基片2、32粘结,可以解决因线膨胀系数差异而导致剥离的问题,且由于半导体元件1a、1b、1c装在该粘结层内,可以提高元件贴装密度并改善其机抗械震动特性与耐湿性。
(第五实施例)
现参照图7所示的高频半导体装置的截面图,对本发明的第五
实施例进行说明。
图7中的装置跟图6所示的第四实施例的不同点在于:将氧化铝基片32上贴装的半导体元件中功率放大器等需要散热的砷化镓功率半导体元件1a,用高热传导粘结剂(未作图示)加以固定,并用金属线5跟氧化铝基片32联结。这样,砷化镓功率半导体元件1a就可直接散热到氧化铝基片32上。在氧化铝基片32上直接固定元件可以取得好的散热效果,但是通过金属线5的散热作用也得到了重视。本实施例尤其适合元件发热量大的场合。
(第六实施例)
现参照图8所示的高频半导体装置的截面图,对本发明的第六实施例进行说明。图8中的装置跟图7所示的第五实施例的不同点在于:在用复合树脂材料层10粘结陶瓷多层基片2和氧化铝基片32之前,在氧化铝基片32上贴装的砷化镓功率半导体元件1a和联结用金属线5的周围,用液态环氧树脂6密封。
可以用环氧树脂6将功率半导体元件1a和金属线5全部覆盖,考虑到环氧树脂6硬化时树脂会胀开,以选用触变性高的树脂为宜。采用在这种结构中,可以用液态环氧树脂将装于所述第二陶瓷基片的、由所述金属线联结的所述半导体元件的周围密封。这样,用复合树脂材料将第一陶瓷基片与第二陶瓷基片粘结时,可以减缓作用于半导体元件与金属线的应力,使金属线的塌陷、断裂等不良现象减少,从而提高装配的合格率。另外,利用将半导体元件密封的环氧树脂充当第一陶瓷基片与第二陶瓷基片之间的隔片,可以对基片之间的间隙进行调整。
(第七实施例)
现参照图9所示的高频半导体装置的截面图,对本发明的第七实施例进行说明。图9中的装置跟图3所示的第二实施例的不同点在于:陶瓷多层基片2的下部表面带有凹陷部分2a,半导体元件1a、1b、1c与无源元件装于凹陷部分2a;在陶瓷多层基片2上凹陷部分2a的周围形成外部连接用电极4。在凹陷部分2a上形成复合树脂材料层10,将半导体元件1a、1b、1c与无源元件埋入。
再有,也可用金属线连接半导体元件和陶瓷多层基片2的电极图案。并且,也可采用没有散热用电极14和层间连接构造通孔21的结构。由于用凹陷部分2a作为半导体元件与无源元件的安装部分,使复合树脂材料层10容易形成。
Claims (7)
1.一种高频半导体装置,包括:陶瓷基片,包含装于所述陶瓷基片下表面的半导体元件与无源元件的元件群,以及为将所述元件群向内部掩埋而在所述陶瓷基片下表面形成的复合树脂材料层;
其特征在于:所述复合树脂材料层由包含环氧树脂与无机充填物的复合树脂材料形成;所述复合树脂材料层为对应于所述陶瓷基片形状的平板状,其下面呈涉及所述陶瓷基片整个区域的平坦状,且形成有外部连接用电极;所述外部连接用电极与导电性树脂连接,所述导电性树脂被埋入在所述复合树脂材料层中形成的层间连接构造通孔中。
2.如权利要求1所述的高频半导体装置,其特征在于:所述半导体元件用倒装片连接方式安装。
3.如权利要求2所述的高频半导体装置,其特征在于:在所述复合树脂材料层中形成由导热系数高于环氧树脂的高热传导树脂材料埋没的层间连接构造,所述外部连接用电极包括充当散热用电极的接地电极,所述半导体元件的表面经由所述层间连接构造与所述接地电极连接。
4.一种高频半导体装置,包括:有电路图案的第一陶瓷基片,装有半导体元件的第二陶瓷基片,以及设置于所述第一陶瓷基片与所述第二陶瓷基片之间将所述半导体元件向内部埋入的复合树脂材料层;
其特征在于:所述复合树脂材料层由包含环氧树脂与无机充填物的复合树脂材料形成,所述复合树脂材料层中形成将导电性树脂材料埋入的层间连接构造,所述第一陶瓷基片的电路图案与所述第二陶瓷基片的电路图案通过所述层间连接构造实现电气连接。
5.如权利要求4所述的高频半导体装置,其特征在于:所述第二陶瓷基片上装载的所述半导体元件用倒装片连接方式安装。
6.如权利要求5所述的高频半导体装置,其特征在于:所述第二陶瓷基片上装载的所述半导体元件中的一部分用金属线联结。
7.如权利要求6所述的高频半导体装置,其特征在于:所述第二陶瓷基片上装载并用金属线联结的所述半导体元件的周围,用液体环氧树脂密封。
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Also Published As
Publication number | Publication date |
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US20040026780A1 (en) | 2004-02-12 |
US20050040522A1 (en) | 2005-02-24 |
EP1304909A1 (en) | 2003-04-23 |
EP1304909B1 (en) | 2004-12-29 |
JP2003124435A (ja) | 2003-04-25 |
US6818979B2 (en) | 2004-11-16 |
US20030071350A1 (en) | 2003-04-17 |
DE60202425T2 (de) | 2005-06-02 |
US6815810B2 (en) | 2004-11-09 |
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