CN1207779C - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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Abstract
本发明主要是关于在把用于高频的半导体元件收容于空心密封插件的半导体装置中,作为密封空心插件的盖,使用玻璃板的半导体装置及其制造方法。在本发明中,底板21a的正面一侧具有第1主面22a。在第1主面22a上形成岛状部件26,并粘附半导体芯片29等。半导体芯片29等借助柱状部件23及透明玻璃板36被密封在空心中。而且,柱状部件23和玻璃板36用由环氧系列树脂组成的遮光性粘着树脂粘接,因此,可以防止光线直接照射半导体芯片29,进而能够抑制半导体芯片29的特性恶化,提供上述的半导体装置及其制造方法。
Description
技术领域
本发明主要涉及的是把用于高频的半导体元件及过载电流保护功能收容于空心密封插件的半导体装置及其制造方法。
背景技术
图9表示使用现有的空心插件的半导体装置的一个例子。该电子部件是由陶瓷等组成的主底板1、外部连接引线2和同样由陶瓷等组成的间隙3构成,在引线2的元件装载部件4表面上粘附着半导体芯片5,接合线6把半导体芯片5和引线2连接起来,半导体芯片5封于间隙3构成的密封空间7内部(例如,特开平10-173117号)。
制造这种部件时,要经过如下的工序:在引线框架状态下供给引线2,对于该引线框架将半导体芯片5小片接合、线接合,并在引线框架下面贴上主底板1,然后将间隙3贴在主底板1上夹住引线2,并切断、整形引线2。
发明内容
然而,在现有的半导体装置中存在如下的问题:对于引线框架,要对应每个元件贴上主底板1和间隙3,所以制造工序复杂,难以进行大批量生产。
而且,由于把半导体芯片5封在由陶瓷等构成的间隙3所构成的密封空间7内部,所以,在外观检查时无法确认粘接部件的状态,难以去除发生粘接不良的半导体装置。
鉴于上述的各种问题,本发明的半导体装置的特征是具有如下内容:由绝缘体构成的支撑底板;设在该支撑底板正面的导电模型以及与该导电模型电连接的设在背面的外部连接端子;设在上述支撑底板的上述导电模型上的电路元件;覆盖上述电路元件,在与上述支撑底板之间形成密封空心部分并粘接的玻璃板;涂满上述玻璃板的全部粘接面的粘着树脂。
本发明的半导体装置的特征理想的是具有如下的结构:为空心密封上述电路元件所使用的上述玻璃板,由于在其粘接面上全部涂满遮光性粘着树脂,所以,在外观检查时可以确认粘接部件的状态,而且,可以防止光线直接照射到上述电路元件,从而避免上述电路元件的特性发生变化。
为了解决上述问题,本发明的半导体装置的制造方法的特征是具有以下工序:准备正面设有形成了多个装载部件的导电模型,背面设有外部连接端子的支撑底板的工序;在上述各装载部件上粘附电路元件的工序;覆盖上述电路元件,在与上述支撑底板之间,对上述每个装载部件形成密封空心部分的玻璃板的粘接面上全部涂满粘着树脂的工序;粘接上述玻璃板和上述支撑底板,对上述每个装载部件形成密封空心部分的工序;切割上述支撑底板和上述玻璃板的粘接部件,并按上述每个装载部件进行分离的工序。
本发明的半导体装置的制造方法理想的是其特征为:在形成密封空心的工序中,在形成密封空心的上述玻璃板的粘接面上预先全部涂满遮光性粘着树脂,由于可以一次形成多个半导体元件,因此制造工序简洁,可以进行大批量生产。
附图说明
图1是说明本发明的(A)断面图、(B)平面图。
图2是说明本发明的(A)断面图、(B)平面图。
图3是说明本发明的(A)侧视图、(B)侧视图。
图4是说明本发明的(A)断面图、(B)侧视图、(C)侧视图。
图5是说明本发明的侧视图。
图6是说明本发明的(A)侧视图、(B)侧视图。
图7是说明本发明的(A)侧视图、(B)断面图、(C)侧视图。
图8是说明本发明的(A)侧视图、(B)侧视图。
图9是说明现有例子的(A)断面图、(B)平面图。
具体实施方式
以下参照图面,对本发明的实施方式进行详细的说明。
图1是表示本发明的半导体装置的1实施例的断面图(A)、平面图(B)。从大块底板21分割的底板21a,是由陶瓷或环氧玻璃钢板等绝缘材料构成的,具有100~300微米的板厚和俯视(如图1(B)那样观测)长边×短边为2.5mm×1.9mm左右的长方形形状。而且,底板21a分别在正面具有第1主面22a,在背面具有第2主面22b,这些表面互相平行延伸。柱状部件23是环绕底板21a外围附近的高0.4mm、宽0.5mm左右的环形柱状部件,借助柱状部件23形成使底板21a中央部分凹下去的凹部件24。底板21a和柱状部件23是用粘着剂37把各个分别形成的部件材料粘接起来的部件。当然,底板21a和柱状部件23也可以是预先已一体化的部件。
底板21a的第1主面22a的表面平坦,借助镀金等导电模型在该表面上形成岛状部件26和电极部件27、28。而且,在底板21a的岛状部件26中,例如,小片接合着肖托基势垒型二极管、MOSFET元件等半导体芯片29。在半导体芯片29的表面形成的电极垫和电极部件27、28由接合线30连接起来。
在底板21a的第2主面22b的表面上,借助镀金等导电模型形成外部连接端子32、33、34。而且,在电极部件32、33、34中设有从底板21a的第1主面22a贯通到第2主面22b的通路孔35。在通路孔35内部埋置着钨、银、铜等导电材料,岛状部件26、电极部件27、电极部件28分别与外部连接端子32、33、34电连接。外部连接端子32、33、34的端部从底板21的端部后退0.01~0.1mm左右。此外,由于电极部件27、28的通路孔35上并不平坦,所以,接合线30最好避开各个电极部件27、28的通路孔35进行连接。外部连接端子32、33、34预先在大块底板21上形成。
为了把凹部件24变成密封空间,使用板厚为0.1~0.3mm左右的透明玻璃板36作为盖。为使玻璃板36遮盖大块底板21上形成的多个凹部件24,要在玻璃板36粘接面上预先全部涂满遮光性粘着材料37。并且,因为形成凹部件24的柱状部件23上部和玻璃板36的粘接面粘接着,所以半导体芯片29和金属细线30完全被收容在密封空间里。
这里,由于遮光性粘着树脂37全部涂满玻璃板36的粘接面,所以透过玻璃板36的光被遮光性粘着树脂37遮断,从而使光线无法直接照射到凹部件24内的半导体芯片29等。
用切割切断的柱状部件23包围在半导体芯片29周围,而且上部被用切断的玻璃板36密闭着。柱状部件23和底板21a的第1主面22a,以及柱状部件23和玻璃板36均用粘着剂37粘接起来。这样,半导体芯片29和金属细线30被收容在凹部件24构成的密封空间内。底板21a、柱状部件23及玻璃板36的外围端面成为被切割切断的平坦的切断端面。
上述半导体装置,对于安装底板上的电极模型,是将外部连接电极32、33、34对向粘接安装的。
这里,对用树脂遮盖底板,并用共同的树脂层遮盖粘附在各装载部件上的各个半导体芯片情形的实施例,进行简单的说明。
制造工序中,准备在能维持机械强度的板厚为200~350微米的底板上,将多个的装载部件,例如,将100个横竖配置为10行10列的大块底板。底板是由陶瓷或环氧玻璃钢板等构成的绝缘底板。而且,对每个装载部件将半导体芯片小片接合,滴下(potting)一定量的环氧系列液体树脂,用共同的树脂层遮盖所有的半导体芯片。将滴下的树脂层在100~200度进行数小时的热处理(cure)使其硬化后,通过研削弯曲面把树脂层的表面加工成平坦面。研削要用切割装置,借助切割片磨削树脂层表面使得树脂层表面以底板为基准达到一定的高度。此工序把树脂层的膜厚变成0.3~1.0mm。上述切片中已准备好各种板厚的部件,使用较厚的切片,经过反复多次切削,全部形成平坦面。
接着,图2是表示使用保险丝的过载电流保护装置的实施例的断面图(A)、平面图(B)。底板51由陶瓷或环氧玻璃钢板等绝缘材料构成。具有100~300微米的板厚和俯视(如图2(B)那样观测)长边×短边为2.5mm×1.9mm左右的长方形形状。而且,底板51分别在正面具有第1主面52a,在背面具有第2主面52b。柱状部件53是环绕底板51外围附近的高0.4mm、宽0.5mm左右的环形侧面部件,借助柱状部件53形成使底板51中央部分凹下去的凹部件54。底板51和柱状部件53是用粘着剂61把各个分别形成的部件材料粘接起来的部件。当然,底板51和柱状部件53也可以是预先已一体化的部件。
底板51的第1主面52a的表面平坦,借助镀金等导电模型在该表面上形成电极部件55、56。例如,用线接合把直径为30微米的金属细线57贴在电极部件55、56之间。金属细线57由纯度为99.99%的金线和焊接的细线等构成,在电极部件55上打入第1接合点,用不超过凹部件54高度的线环在电极部件56上打入第2接合点。
在底板51的第2主面52b的表面上,借助镀金等导电模型形成外部连接端子58、59。而且,在电极部件55、56的下部设有贯通底板51的通路孔60。通路孔60的内部埋置钨等导电材料,电极部件55和电极部件56分别与外部连接端子58和59电连接。外部连接端子58、59的端部从底板51的端部后退0.01~0.1mm左右。此外,由于电极部件27、28的通路孔35上并不平坦,所以,接合线30最好避开各个电极部件27、28的通路孔35进行连接。
为了把凹部件54内部变成密封空间,使用板厚为0.1~0.3mm左右的透明玻璃板62作为盖。为使玻璃板62遮盖大块底板21上形成的多个凹部件54,要在玻璃板62粘接面上预先全部涂满遮光性粘着材料61。并且,因为形成凹部件54的柱状部件53上部和玻璃板62的粘接面粘接着,所以金属细线57完全被收容在密封空间里。
这里,由于遮光性粘着树脂61全部涂满玻璃板62的粘接面,所以透过玻璃板62的光被遮光性粘着树脂61遮断,使光线无法直接照射到凹部件54内的金属细线57等。
上述过载电流保护装置,对于安装底板上的电极模型,是把外部连接电极58、59对向连接安装的。外部连接端子58、59之间通过额定以上的过载电流时,该过载电流流过金属细线57,由于金属细线57的固有电阻,使温度急剧上升。因为发热熔断金属细线57,从而起到了对过载电流的保护作用。如果是上述直径为30微米的金(Au)线,则当线长约为0.7mm时,熔断电流约为4A(1~5秒)。在多数情况下,根据散热性和电阻的关系,熔断与发生在电极部件55、56附近相比,更多发生在金属细线57的正中附近。此时,由于熔断处没有连接树脂等其它素材,所以,在外观上可以得到不着火,不冒烟,不变色,不变形的装置。而且,由于金属细线27熔断,所以过载电流发生时端子间可以变成完全开放的元件。
当然,作为保险丝元件,除金属细线之外,通过粘着把形成电极部件55、56的导电模型的一部分作成楔形状的窄带并使其连续的物体,或多晶硅电阻等也可以形成。要点是将熔断处收容在凹部件54内即可。而且,凹部件54内部在大气中是密封的,例如,也可以填充氮气等不可燃气体。
如上所述,本发明的半导体装置,为了空心密封半导体芯片29、接合线30等而使用了透明玻璃板36,由此,在外观检查时可以确认玻璃板36和柱状部件23的粘接部件的状态。而且,因为在玻璃板36粘接面上全部涂满了遮光性粘着树脂37,所以可以抑制透过玻璃板36的光线射入凹部件24内,直接照射半导体芯片29等,使半导体芯片29等的特性恶化。
而且,本发明的半导体装置,由于使用了柱状部件23及玻璃板36而可以形成空心结构,底板21a上小片接合的半导体芯片29等,被收容在由空心部件凹部件24构成的密封空间里。由此,与用树脂层遮盖在底板21a上,用树脂层遮盖粘附在装载部件上的半导体芯片29的情形相比,可以大大降低材料成本。
而且,本发明的半导体装置,由于使用了柱状部件23及玻璃板36而可以形成空心结构,作为空心结构的盖使用了玻璃板36,所以不需要将半导体元件的表面进行平坦化的工序,与用树脂层遮盖在底板21a上,用树脂层遮盖粘附在装载部件上的半导体芯片29的情形相比,可以大大降低制造成本。
而且,底板21a上设有从第1主面22a贯通到第2主面22b的通路孔35。并且,在通路孔35内部埋置着钨、银、铜等导电材料,把岛状部件26、电极部件27、电极部件28分别与外部连接端子32、33、34电连接,并可以将内部元件和上述外部连接端子电连接,因不必从底板21a向外部引出引线,所以往印刷底板上安装时,可以大大减少安装面积。
以下详细说明图1所示的本发明的第1个实际例。
第1工序:参照图3(A)
首先,准备大块底板21。大块底板21由陶瓷或环氧玻璃钢板等绝缘材料构成,具有100~300微米的板厚。而且,大块底板21分别在正面具有第1主面22a,在背面具有第2主面22b。符号23是按高0.1~0.5mm,宽0.25~0.5mm左右的一定幅度设置的格子状的柱状部件,借助柱状部件23形成使底板21的中央部分凹下去的凹部件24。底板21和柱状部件23预先形成一体化,连同柱状部件23成为上述的板厚。当然,也可以分别形成底板21和柱状部件23再粘着固定。
凹部件24,例如一个的大小约有0.8mm×0.6mm,被横竖等间距配置在底板21上。在凹部件24的第1主面22a上,借助镀金等导电模型描绘着多组岛状部件26和电极部件27、28。各凹部件24和包围其周围的第2底板21b的柱状部件23的一部分构成元件装载部件41。
第2工序:参照图3(B)
准备好这种底板21后,对每个凹部件24,在岛状部件26上小片接合半导体芯片29,线接合接合线30。而且,在半导体芯片29上线接合的接合线30的一端,连接着电极部件27、28。此时,接合线30的线环高度控制在柱状部件23的高度以下。
第3工序:参照图4(A)、(B)
准备板厚为0.1~0.3mm左右的透明玻璃板36,在玻璃板36的粘接面上全部涂满遮光性粘着树脂37。并且,玻璃板36,例如,在包含用大块底板21和柱状部件23所形成的多个凹部件24的装载部件41上,作为构成密封空心结构的盖被粘接起来。因此,半导体芯片29和接合线30被完全收容在密封空间内。此时,如上所述,因为玻璃板36上被全部涂满遮光性粘着树脂37,所以一次可以形成大量的半导体元件。
这里,对于大块底板21和柱状部件23,可以后粘接柱状部件23,也可以预先就形成一个整体。而且,也可以掘削大块底板21,来形成凹部件24。
然后,通过目测检查柱状部件23和玻璃板36是否发生粘接不良。
第4工序:参照图4(C)
而且,以底板21表面形成的对准标记为基准,按每个装载部件41进行分割,如图5所示,得到各个单独的装置。分割时使用切割片42,在底板21的背面一侧贴上切割图,沿着切割线43把底板21和玻璃板36横竖一起切断。当然,切割线43位于柱状部件23的中心。而且,也可以把切割图贴在玻璃板36一侧,从第2主面22b一侧切割。
以下对图1所示的本发明的第2实际例进行说明。这是柱状部件23作为个别部品构成的情形。
第1工序:参照图6(A)
首先,准备平板状的大块底板21。大块底板21由陶瓷和环氧玻璃钢板等绝缘材料构成,具有100~300微米的板厚。而且,大块底板21分别在正面具有第1主面22a,在背面具有第2主面22b。在第1主面22a的表面上,借助镀金等导电模型描绘着多组岛状部件26和电极部件27、28。包围岛状26和电极部件27、28周围的领域构成元件装载部件41,多个该元件装载部件41被等间距横竖配置。
第2工序:参照图6(B)
准备好这种底板21后,对每个元件装载部件41,在岛状部件26上小片接合半导体芯片29,线接合接合线30。而且,在半导体芯片29上线接合的接合线30的一端,连接在电极部件27、28。此时,接合线30的线环高度控制在柱状部件24的深度以下的高度。
第3工序:参照图7(A)
对于完成了小片接合、线接合的底板21,在对应元件装载部件41的地方,把具有凹部件24(贯通穴)的第2底板21a粘接固定在第1主面22a表面上。粘接使用环氧系列等的粘着剂。
凹部件24,例如一个的大小约有0.8mm×0.6mm,被等间距横竖配置在第2底板21b上。凹部件24和凹部件24之间,柱状部件23以高0.1~0.2mm、宽0.2~0.5mm左右的一定幅度围成格子状。于是在凹部件24上露出岛状26、半导体芯片29、电极垫27、28等,这样和图3(B)的状态等价。如果是这种方法,可以对平板形底板21进行小片接合、线接合,所以吸附夹头和接合工具与柱状部件23不接触,可以缩小凹部件24的尺寸。
第4工序:参照图7(B)、(C)
准备板厚为0.1~0.3mm左右的透明玻璃板36,在玻璃板36的粘接面上全部涂满遮光性粘着树脂37。并且,玻璃板36,例如,在包含用大块底板21和柱状部件23所形成的多个凹部件24的装载部件41上,被作为构成密封空心结构的盖粘接起来。因此,半导体芯片29和接合线30被完全收容在密封空间内。此时,如上所述,因为玻璃板36上被全部涂满遮光性粘着树脂37,所以一次可以形成大量的半导体元件。
然后,通过目测检查柱状部件23和玻璃板36是否发生粘接不良。
第5工序:参照图8(A)
而且,以底板21表面形成的对准标记为基准,分割每个装载部件41,如图8(B)所示,得到单个的装置。分割时使用切割片42,在底板21的第2主面22b一侧贴上切割图,沿着切割线43把底板21、第2底板21b及玻璃板36横竖一起切断。当然,切割线43位于柱状部件23的中心。而且,也可以从第2主面22b一侧切割。
如上所述,根据本发明的半导体装置,因为对空心密封半导体芯片、接合线等使用透明玻璃板,所以,在外观检查时可以确认玻璃板和柱状部件的粘接部件的状态。而且,因为在玻璃板粘接面上全部涂满遮光性粘着树脂,所以可以抑制透过玻璃板的光线射入凹部件内,直接照射半导体芯片等,使半导体芯片等的特性恶化。
而且,根据本发明的半导体装置的制造方法,由于预先在形成密封空心结构的玻璃板的粘接面上全部涂满遮光性粘着树脂,所以可以一次粘接由底板和柱状部件形成的多个凹部件,进而可以大大降低制造成本,并进行大批量生产。
Claims (5)
1.一种半导体装置,其特征在于:包括
由绝缘体构成的支撑底板;
设在该支撑底板正面的导电模型以及与该导电模型电连接的设在背面的外部连接端子;
设在上述支撑底板的上述导电模型上的电路元件;
覆盖上述电路元件,与上述支撑底板之间形成密封空心部分并粘接的玻璃板;
涂在上述密封空心部分一侧的上述玻璃板整面的遮光性粘着树脂。
2.权利要求1记载的半导体装置,其特征还在于:
上述电路元件是半导体元件或保险丝元件。
3.权利要求2记载的半导体装置,其特征还在于:
上述保险丝元件由在上述密封空心部分内的上述导电模型间电连接的金属细线构成。
4.一种半导体装置的制造方法,其特征在于包括以下工序:
准备正面设有形成了多个装载部件的导电模型,背面设有外部连接端子的支撑底板的工序;
在上述各装载部件上粘附电路元件的工序;
覆盖上述电路元件,在与上述支撑底板之间,对上述每个装载部件形成密封空心部分的玻璃板的、上述密封空心部分一侧的整面涂满遮光性粘着树脂的工序;
粘接上述玻璃板和上述支撑底板,对上述每个装载部件形成密封空心部分的工序;
切割上述支撑底板和上述玻璃板的粘接部件,并按上述每个装载部件进行分离的工序。
5.权利要求4记载的半导体装置的制造方法,其特征还在于:
在上述支撑底板粘贴切割图后,切割上述支撑底板及上述玻璃板。
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-
2000
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2001
- 2001-09-26 US US09/963,267 patent/US6815808B2/en not_active Expired - Lifetime
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- 2001-10-08 DE DE2001625888 patent/DE60125888T2/de not_active Expired - Fee Related
- 2001-10-10 CN CNB011354089A patent/CN1207779C/zh not_active Expired - Fee Related
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US6815808B2 (en) | 2004-11-09 |
EP1202350B1 (en) | 2007-01-10 |
DE60125888T2 (de) | 2007-11-15 |
EP1202350A3 (en) | 2004-03-31 |
US20020041016A1 (en) | 2002-04-11 |
DE60125888D1 (de) | 2007-02-22 |
EP1202350A2 (en) | 2002-05-02 |
CN1347153A (zh) | 2002-05-01 |
JP4565727B2 (ja) | 2010-10-20 |
JP2002118192A (ja) | 2002-04-19 |
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