CN1195191A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
CN1195191A
CN1195191A CN97114113A CN97114113A CN1195191A CN 1195191 A CN1195191 A CN 1195191A CN 97114113 A CN97114113 A CN 97114113A CN 97114113 A CN97114113 A CN 97114113A CN 1195191 A CN1195191 A CN 1195191A
Authority
CN
China
Prior art keywords
layer
adherent zone
ground floor
electrode pad
adhesion layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN97114113A
Other languages
English (en)
Other versions
CN1147931C (zh
Inventor
内田康文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lapis Semiconductor Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Publication of CN1195191A publication Critical patent/CN1195191A/zh
Application granted granted Critical
Publication of CN1147931C publication Critical patent/CN1147931C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48699Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01021Scandium [Sc]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

根据本发明的半导体器件包括半导体元件1上提供的众多电极压焊点,通过键合线W与电极压焊点连接的引脚L以及半导体元件1上提供的使得众多电极压焊点中处理公共信号的电极压焊点电连接的公用线2a和2b。至少在公用线2a和2b的表面覆盖着一层绝缘部分,例如,第二层绝缘粘附带。这样,键合线的弯曲高度就可以降低,从而得到较薄的封装。

Description

半导体器件及其制造方法
本发明涉及半导体器件和制造该半导体器件的方法。具体地说,本发明与具有为半导体元件上众多电极压焊点中那些处理公共信号的电极压焊点提供电连接的公用线的半导体器件及制造该半导体器件的方法相关。
图6是表示现有技术的一个例子的简图。这个半导体器件由一个LOC(片上引脚)结构组成,并配有一个片上半导体元件1,众多引线L及通过半导体元件1上绝缘带T连接的公用线2a′和2b′。
另外,在这些众多的电极压焊点中,接电源的电极压焊点P1通过键合线W与公用线2a′相连,而接地的电极压焊点P2,则通过键合线W与公用线2b′相连。通过这些连接,公用线2a′形成一条电源线而公用线2b′形成一条地线。
此外,电极压焊点Pa和Pb与通过键合线W形成电源线的公用线2a′相连,而电极压焊点Pc,Pd,Pe和Pf与通过键合线W形成地线的公用线2b′相连。要注意的是其它电极压焊点通过键合线W与引脚L直接连接。
在新近的半导体器件中,半导体元件1的小型化,已使得内部线条极其细。因为这一点,如果提供电源的电极压焊点P1和接地的电极压焊点P2的连接要在半导体元件1的内部完成的话,那么由于电压的减少将会发生性能特性的衰减。因此,它们可利用公用线2a′和2b′来进行电连接。
然而,这样一个半导体器件会出现以下问题。即,当电极压焊点P和引脚L通过键合线W连接时,如图7(a)所示,就必须将键合线弯曲,跨过公用线2a′和2b′。为避免与它们接触,还要留有足够的间隙。
通常情况下,公用线2a′和2b′是作为与引脚L相集成的引线框构成的,它们的厚度大约150微米。这样,为了保证键合线W与公用线2a′和2b′不接触,就需使它的弯曲高度大约为400微米或更高。
然而,如果在这种情形下,弯曲高度太高,那么,当组装一个如图7(b)所示的薄封装PC时,就会出现键合线不能包在封装PC里而是曝露出来的问题。
本发明的提出已通过对上面讨论的现有技术中半导体器件和它的制造方法中问题的阐述得以完成。它的第一个目的是提供一种新的和改进的,即使当键合线横跨公用线连接时也不需要考虑公用线和键合线间电接触可能性的半导体器件,以及制造这样一种半导体器件的方法。
本发明另一个目的是提供一种新的和改进的,即使当键合线横跨公用线连接时也可能降低键合线的弯曲度以得到更薄半导体器件封装的半导体器件,以及制造这样一种半导体器件的方法。
此外,另一个目的是提供一种新的和改进的,产品的可靠性通过防止键合线被压扁或变形而得以提高的半导体器件,以及制造这样一种半导体器件的方法。
为了达到上述目的,本发明的第一方面是该半导体器件包括半导体元件上众多电极压焊点,通过键合线与电极压焊点相连接的引脚,以及为位于半导体元件上众多的电极压焊点中处理公共信号的电极压焊点提供一种电连接的公用线,至少在它们的表面覆盖着一层绝缘部分。
对于这种结构,因为有一层绝缘部分完全覆盖住为半导体元件上众多电极压焊点中处理公共信号的电极压焊点提供电连接的公用线表面,所以即使跨接在公用线两边的键合线与它们接触,也会因该绝缘部分而不会发生电连接。换句话说,不需要考虑键合线和公用线间的电接触的可能性,这就使得可能减少键合线的弯曲高度。
另外,为达到上述目的,本发明的第二方面是制造半导体器件的方法,包括第一层绝缘粘附带被做在半导体元件上,以避免与众多电极压焊点相接触的工艺,导电粘附层层叠在半导体元件第一层绝缘粘附带上使得处理公共信号的电极压焊点电连接的工艺,为覆盖导电粘附层而层叠第二层绝缘粘附带的工艺,以及使得既没有导电粘附层又没有第二层绝缘粘附带覆盖其上的电极压焊点,通过跨接并接触第二层绝缘粘附带的键合引线与完成信号输入/输出的引脚相连的工艺。
在这个方法中,因为导电粘附层叠到做在半导体元件上以避免与众多电极压焊点接触的第一层绝缘粘附带上,并且导电粘附层与处理公共信号的电极压焊点电连接,以及第二层绝缘粘附带层叠在导电粘附层的表面,所以被绝缘部分包裹的导电粘附层可以作为公用线。此外,通过以跨接在第二层绝缘粘附带两边并与第二层绝缘粘附带接触的方式来放置键合线,使得键合线被第二层绝缘粘附带支撑着。
图1是示意第一种实施方式的简图;
图2是示意制做导电粘附层的截面简图;
图3是示意第二种实施方式的简图;
图4是示意第三种实施方式的简图;
图5是示意第三种实施方式的简图;
图6是示意现有技术中一个实例的简图;以及
图7是示意现有技术中一个实例的简图。
本发明的优选实施方式
下面是对根据本发明提出的半导体器件和它的制造方法的有关实施方式的解释。图1是示意第一种实施方式的简图。正象图1(a)中平面简图所示,第一种实施方式的半导体器件具有一个LOC结构,并配有一个片上半导体元件1,众多引脚L和公用线2a和2b通过半导体元件1上的绝缘带T相连,为衬底1a上的众多电极压焊点中处理公共信号的电极压焊点提供电连接,以及将电极压焊点与引脚L电连接的键合线W。
在这个半导体器件中,公用线2a通过与接电源的电极压焊点P1电连接构成电源线,而公用线2b则通过与接地的电极压焊点P2电连接构成地线。
另外,公用线2a也与电极压焊点Pa和Pb电连接,使它们加电源,而公用线2b也与电极压焊点Pc,Pd,Pe和Pf电连接,使它们接地。要注意的是其余电极压焊点通过横跨公用线2a和2b的键合线W与引脚L相连。
图1(b)是图1(a)中区域A的放大图,图1(c)是从箭头指示的方向看过去的图1(b)中直线B-B截面图。如图中所示,第一种实施方式中的公用线2a和2b,每条都有一个3层的相叠结构。即,构成最底层的第一层绝缘粘附带21,构成中间层的导电粘附层22,以及构成最上层第二层绝缘粘附带23。要注意的是图1(b)表示只有导电粘附层22形成在构成最底层的第一层绝缘粘附带21上的情形。
通过在带上采用热塑粘附剂来形成的第一层绝缘粘附带21被做在衬底1a上,带中有孔,这些孔与电极压焊点的位置重合,以便电极压焊点可以与衬底1a上的公用线2a或2b相接触。另外,导电粘附层22是热固性粘附剂,通过第一层绝缘粘附带21中的孔与电极压焊点接触。
另外,象第一层绝缘粘附带21一样,通过在带上采用热塑粘附剂来形成的第二层绝缘粘附带23被用来至少覆盖导电粘附层22的表面。
例如,在公用电源线2a上,孔做在构成较底层的第一层绝缘粘附带21中,它们与电极压焊点P1和电极压焊点Pa及Pb位置重合,并且接电源的电连接走线由进入这些孔,同时也做在第一层绝缘粘附带21上的导电粘附层22构成。另外,因为第二层绝缘粘附带至少覆盖着导电粘附层22,于是就在导电粘附层22和键合线W之间得到绝缘。
此外,在公用接地线2b上,孔做在构成较底层的第一层绝缘粘附带21中,它们与电极压焊点P2和电极压焊点Pc,Pd,Pe及Pf位置重合,并且接地的电连接走线由进入这些孔,同时也做在第一层绝缘粘附带21上的导电粘附层22构成。因为第二层绝缘粘附带至少覆盖着导电粘附层22,于是就在导电粘附层22和键合线W之间得到绝缘。
每条公用线2a和2b的厚度大约为45~50微米(第一层绝缘粘附带21和第二层绝缘粘附带23每层厚度大约20微米,而导电粘附层厚度大约5微米),通过这样设置这些尺寸,跨接这些线的键合线W的弯曲高度与现有技术相比可以减少。此外,因为有形成在表面上的第二层绝缘粘附带23,即使键合线W与公用线2a和2b接触也不会发生短路。
下面介绍该半导体器件的制造方法。首先,在加热和加压的条件下做成第一层绝缘粘附带21,上面有着与半导体元件上处理电源信号的电极压焊点P1,Pa和Pb位置重合的孔,同时在加热和加压的条件下做成第一层绝缘粘附带21,上面有着与半导体元件上处理地信号的电极压焊点P2,Pa和Pb位置重合的孔。其次,导电粘附层22做在第一层绝缘粘附带21之上,同时保证导电粘附层22进入孔。在这点上,导电粘附层22宽度应做得比第一层绝缘粘附带21的要窄。
图2是示意导电粘附层制做的截面图。图2(a)示意一个使用调和机D的例子,在这个例子中,导电粘附层22通过在半导体元件1第一层绝缘粘附带(没有画出)上移动调和机D来做在预定位置,导电粘附剂从调和机D的顶头流出。
图2(b)示意出一个使用冲压机的例子。在这个例子中,导电粘附层22粘附在有特定形状的冲压机底面,并通过冲压将它层叠在半导体元件1第一层绝缘粘附带(没有画出)上。
图2(c)示出一个使用丝网印刷的例子。在这个例子中,丝网SC放置在半导体元件1上,并通过使用一个涂刷器K把导电粘附层22涂在丝网SC上,导电粘附层22通过丝网SC上特定形状的开口层叠在半导体元件1第一层绝缘粘附带(没有画出)上。
在采用上述方法之一做完导电粘附层22后,再做第二层绝缘粘附带,以使导电粘附层完全被覆盖。随后,加热到一定的温度,使得导电粘附层22热致成具有3层结构的公用线2a和2b。
接下来,与公用线2a或2b不相连的电极压焊点通过键合引线W与引脚L连接。在这些线中,键合线W跨接在公用线2a和2b两边,被公用线2a和2b表面上的第二层粘附带23所支撑并与之接触。这就使到键合线W得到较低的弯曲高度,同时也有足够的形状保持强度。
键合线W连接后,半导体元件1的整体用压模树脂(没有画出)包在封装里。在这个实施方式中,因为键合线W的弯曲高度可以比现有技术低,所以压模树脂的厚度也能减少。
要注意的是,虽然关于以上描述的制造方法,已给出了一个例子的解释,在这个例子中第一层绝缘粘附带21是在半导体元件1形成后(被划开)做成的,但是第一层绝缘粘附带21也可能在圆片被划成半导体元件1之前就已做好。
接下来,阐述本发明的第二种实施方式。图3是第二种实施方式的简图,其中图3(a)表示平面简图,图3(b)表示图3(a)中区域A′的放大图,图3(c)表示一个从箭头指向的方向看过去的图3(b)中线B-B截面图。
正象图3(a)所示,第二种实施方式的半导体器件具有一个LOC结构,并配有一个片上半导体元件1,在半导体元件1的衬底1a上通过绝缘带T连接的众多引脚L,为衬底1a上众多电极压焊点中处理公共信号电极压焊点提供电连接的公用线2a和2b,以及将电极压焊点与引脚L电连接的键合线W。
另外,在第二种实施方式中,与加电源的电极压焊点Pa和Pb电连接的公用线2a以及与接地的电极压焊点Pc,Pd,Pe和Pf电连接的公用线2b都由3层结构组成(第一层绝缘粘附带21,铜箔层22a,第二层绝缘粘附带23),铜箔层22a和电极压焊点通过金属凸点BP相连接(见图3(a)和3(b))。要注意的是,3(b)示意出只有铜箔层22a形成在构成最底层的第一层绝缘粘附带21上的情形。
通过在带上采用热塑粘附剂来形成的第一层绝缘粘附带21被做成一种形式,在这种形式中,绝缘粘附带21上的孔形成在与电极压焊点重合的位置,以便电极压焊点可以与衬底1a上的公用线2a或2b相接触。另外,铜箔22a通过位于孔处的金属凸点BP层叠在第一层绝缘粘附带21上。此外,第二层绝缘粘附带23,象第一层绝缘粘附带21一样,是通过在带上采用热塑粘附剂而形成的,它被用于覆盖铜箔22a的表面。
在电源公用线2a上,孔做在构成较底层的第一层绝缘粘附带21中与电极压焊点P1和电极压焊点Pa及Pb相重合的位置,并且接电源的电连接走线由通过位于那些孔处的金属凸点BP的铜箔22a构成。另外,因为第二层绝缘粘附带至少覆盖着导电粘附层22,于是就在导电粘附层22和键合线W之间得到绝缘。
此外,在接地公用线2b上,孔做在构成较底层的第一层绝缘粘附带21中与电极压焊点P2和电极压焊点Pc,Pd,Pe及Pf重合的位置,并且电连接的地线由通过位于那些孔处的金属凸点BP的铜箔22a构成。通过第二层绝缘粘附带至少覆盖着铜箔22a的表面,铜箔22a与键合线W相绝缘。
每条公用线2a和2b的厚度大约为45~50微米(第一层绝缘粘附带21和第二层绝缘粘附带23每层厚度大约20微米,而铜箔22a厚度大约5微米),通过这样设置这些尺寸,跨接这些线的键合线W的弯曲高度与现有技术相比可以减少。此外,因为有形成在表面上的第二层绝缘粘附带23,即使键合线W与公用线2a和2b接触也不会发生短路。
接下来阐述制造这种半导体器件的方法。首先,上下表面都有热致粘附剂的第一层绝缘粘附带21在加热和加压下做在衬底1a上,对于公用线2a来说,第一层绝缘粘附带21做成上面带有与半导体元件上处理电源信号的电极压焊点P1,Pa和Pb位置重合的孔,而对于公用线2b来说,第一层绝缘粘附带21做成上面带有与半导体元件上处理电源信号的电极压焊点P2,Pc,Pd,Pe和Pf位置重合的孔。要注意的是,这里假定了孔中每个电极压焊点上都有金属压焊点BP。
铜箔22a然后在加压下粘附在第一层绝缘粘附带21上。下表面带有热致粘附剂的第二层绝缘粘附带23,在加压下粘附在铜箔22a上。粘附的铜箔22a的宽度应比第一层绝缘粘附带21和第二层绝缘粘附带23的宽度要窄。
随后,从第二层绝缘粘附带23上方加热和加压。通过这种方式,就得到一种铜箔22a和金属凸点BP接触的情形。接着,在这种情形中,对半导体元件1进行加热。通过加热,用于第一层绝缘粘附带21和第二层绝缘粘附带23的热致粘附剂就会固化和收缩,以致使铜箔22a和金属压焊点BP非常牢固地相接触。
接下来,与公用线2a或2b不相连的电极压焊点通过键合引线W与引脚L电连接。在这些线中,键合线W跨接在公用线2a和2b两边,被公用线2a和2b表面上的第二层绝缘粘附带23所支撑并与之接触。这就使得键合线W得到较低的弯曲高度,同时也有足够的形状保持强度。
键合线W连接后,半导体元件1的整体用压模树脂(没有画出)包在封装里。在这个器件结构中,因为键合线W的弯曲高度与现有技术相比要低,所以压模树脂的厚度也能减少。
此外,因为铜箔22a被用来构成公用线2a和2b的电连接区域,所以在电性能方面有可能提高,因为电连接走线会有低的电阻。
接下来,阐述本发明的第三种实施方式。图4和5是第三种实施方式中器件结构的简图,其中图4(a)表示平面简图,图4(b)表示图4(a)中区域C的放大图,图5(a)表示第一层导电粘附层的形状,图5(b)表示一个从箭头指向的方向看过去的图4(b)中直线D-D截面图,图5(c)表示封装形式的截面简图。
图4(a)示意出第三种实施方式的半导体器件具有一个LOC结构,并配有一个片上半导体元件1,在半导体元件1的衬底1a上通过绝缘带T连接的众多引脚L,为衬底1a上众多电极压焊点中处理公共信号电极压焊点提供电连接的公用线2a和2b,以及将电极压焊点与引脚L电连接的键合线W。
特别是,第三种器件结构的特点表现在与加电源的电极压焊点Pa和Pb电连接的走线以及与接地的电极压焊点Pc,Pd,Pe和Pf电连接的走线都是由5层结构组成。
正象图4(b)和图5(b)所示,该层结构是按以下顺序层叠形成的:构成最底层的第一层绝缘粘附带21,较底层的第一层导电粘附层22,构成中间层的第二层绝缘粘附带23,较高层的第二层导电粘附层24和构成最上一层的第三层绝缘粘附带25。
通过在带上采用热塑粘附剂来形成的第一层绝缘粘附带21被做成带有与电源电极压焊点的位置重合的孔(包括在下面阐述中与这些电极压焊点相接的其它电极压焊点),并带有与接地电极压焊点的位置重合的孔(包括在下面阐述中与这些电极压焊点相接的其它电极压焊点)。下面的阐述中第二层粘附带也有同样的连接应用。
另外,制做第一层导电粘附层22,使它进入第一层绝缘粘附带21上相应于电源电极压焊点位置的孔(例如,电极压焊点Pa),同时避开其它电极压焊点P的位置(见图5(a))。
通过在带上采用热塑粘附剂而形成的第一层绝缘粘附带21,被用来覆盖在第一层导电粘附层22的表面。要注意的是,孔形成在第二层绝缘粘附带23中与接地和其它电极压焊点(除了那些电源或接地电极压焊点以外的电极压焊点)相应的位置上。
制做第二层导电粘附层24,使它进入第二层绝缘粘附带23上相应于接地电极压焊点位置的孔(例如,电极压焊点Pa),同时避开其它电极压焊点P的位置(除了那些电源或接地电极压焊点以外的电极压焊点)。
此外,通过在带上采用热塑粘附剂而形成的第三层绝缘粘附带25,被用来覆盖在第二层导电粘附层24的表面。孔形成在第三层绝缘粘附带25与那些电源或接地电极压焊点以外的电极压焊点相应的位置上。
作为结果,对于这些5层公用线,较底层的第一层导电粘附层22构成接电源的连接走线,而较高层的第二层导电粘附层24构成接地的连接走线。另外,对于形成一个层叠结构的第一层导电粘附层22和第二层导电粘附层24,它们每条都覆盖着电极压焊点的两个侧边。
此外,对于形成在公用线2中那些电源或接地电极压焊点以外的电极压焊点上的孔,键合线W在这些孔处连接,与引脚L电连接。
因为第三层绝缘粘附带25附着在公用线2的表面,所以即使当键合线W与第一层导电粘附层22和第二层导电粘附层24相接触时也可以避免键合线W与它们短路。
下面阐述制造这种半导体器件的方法。首先,带有形成在与各个电极压焊点重合位置的孔的第一层绝缘粘附带21在加热和加压下被粘附。
然后,第一层导电粘附层22被做在第一层绝缘粘附带21上。制做第一层导电粘附层22,使得它通过每个电极压焊点的两边,并只进入形成在处理电源信号的电极压焊点P1,Pa和Pb上的孔(见图5(a))。就象第一种器件结构,第一层导电粘附层22的形成也是通过采用图2(a)~2(c)所示的方法之一完成的。
这之后,第二层绝缘粘附带23在加热和加压下被粘附在第一层导电粘附层22上。要注意的是,孔形成在第二层绝缘粘附带23上与接地电极压焊点P2,Pc,Pd,Pe和Pf以及其它电极压焊点(除了那些电源或接地电极压焊点以外的电极压焊点)重合的位置。
接着,第二层导电粘附层24被做在第二层绝缘粘附带23上。制做第二层导电粘附层24,以使得它覆盖每个电极压焊点的两个侧边,并只进入形成在处理地信号的电极压焊点P2,Pc,Pd,Pe和Pf上的孔。就象第一层导电粘附层22,第二层导电粘附层24的形成也是通过采用图2(a)~2(c)所示的方法之一完成的。
第三层绝缘粘附带2 5在加热和加压下被粘附在如此制做的第二层导电粘附层24上。第三层绝缘粘附带25覆盖着第二层导电粘附层24。要注意的是,孔形成在第三层绝缘粘附带25上与除了那些电源或接地电极压焊点以外的电极压焊点重合的位置。
在通过层叠形成5层公用线2之后,半导体元件1被加热。通过这种加热,热塑粘附剂被固化,于是把各层键合在一起。
随后,没有与公用线2连接的电极压焊点通过键合线W与引脚L电连接。通过这种引线,键合线W形成一种方式,在这种方式中,键合线W跨接在公用线2的两边,被公用线2表面的第三层绝缘粘附带25支撑并与之接触。这样,对于键合线W就得到较低的弯曲高度,同时,达到足够的形状保持强度。
键合线W连接后,半导体元件1的整体用压模树脂密封封装里形成封装PC,如图5(c)所示。因为在这个器件结构中键合线W的弯曲高度与现有技术相比要低,所以封装PC的厚度可减少到图中用2条点划线指示的位置。
在第三种器件结构中,通过形成作为5层结构的公用线2,就形成一种方式,在这种方式中,独立的连接走线独自通过电极压焊点的两边,因此增加了整个宽度(粘附的区域)。这样,有可能通过各层中键合力的增加在可靠性方面有所提高。特别是,当各个电极压焊点的间距变得越小时,这个效果更明显。
虽然优选的根据本发明的半导体器件的实施方式和它的制造方法参照附图已被阐述,但本发明并不局限于这些例子,那些本领域的技术人员会知道,在结构和细部方面可以做各种变化和调整,而不偏离本发明的实质,范围和阐述。
例如,虽然在以上所有阐述的器件结构中,接电源的电源线和接地的地线构成公用线,但本发明不局限于这些例子,并且任何给处理公共信号的众多电极压焊点进行电连接的走线都可以构成公用线。换句话说,半导体元件内部的铝线或类似导线都可用作公用线。
另外,当将公用线和键合线W互相接触时,精确的支撑通过将键合线W放置成多边形的形状而得到(例如,不规则四边形的形状),使得键合线在它几乎水平的区域与公用线成行接触,并形成了多边形的上边。
正象所阐述的,根据本发明的半导体器件和它的制造方法具有下面的优点。即,即使当键合线跨越公用线连接时,也没有必要考虑公用线和键合线间电接触的可能性,因此,有可能减少键合线弯曲的高度。这样,使得半导体器件得到更薄的封装。
另外,当放置键合线时,通过将键合线与做在公用线表面的绝缘粘附带接触放置,就可以支撑键合线,从而防止键合线被压扁或变形,为半导体器件提供高水平的可靠性。

Claims (15)

1.一种半导体器件,包括:
半导体元件上众多电极压焊点;
通过键合线与所述电极压焊点连接的引脚;
所述半导体元件上提供的公用线,这些公用线为所述众多电极压焊点中处理公共信号的电极压焊点提供电连接;以及
至少做在所述公用线表面的绝缘部分。
2.一种根据权利要求1的半导体器件,其中:
电源公用线和接地公用线相互独立地形成在所述半导体元件上,以构成所述公用线。
3.一种根据权利要求1的半导体器件,其中:
所述键合线跨接在所述公用线的两边,并与做在所述公用线的所述表面上的所述绝缘部分接触放置。
4.一种根据权利要求1的半导体器件,其中:
所述公用线每条都包括粘附在所述半导体元件上的第一层绝缘粘附带,层叠在所述第一层绝缘粘附带上的一层导电部分,以及层叠在所述导电部分上的第二层绝缘粘附带。
5.一种根据权利要求1的半导体器件,其中:
所述公用线通过在所述半导体元件上交替层叠绝缘粘附带和导电粘附层而形成,它的最上一层是一层绝缘粘附带。
6.一种根据权利要求4的半导体器件,其中:
孔提供在所述第一层绝缘粘附带与各个处理所述公共信号的电极压焊点重合的位置处,而且所述的各个电极压焊点通过镶嵌在所述孔中的导电部分和所述的导电部分电连接。
7.一种根据权利要求4的半导体器件,其中:
所述导电部分由一层导电粘附层组成。
8.一种根据权利要求4的半导体器件,其中:
所述导电部分由一层金属箔组成。
9.一种根据权利要求5的半导体器件,其中:
所述的公用线包括粘附在所述半导体元件上的第一层绝缘粘附带,层叠在所述第一层绝缘粘附带上的第一层导电粘附层,层叠在所述第一层导电粘附层上的第二层绝缘粘附带,层叠在所述第二层绝缘粘附带上的第二层导电粘附层,以及层叠在所述第二层导电粘附层上的第三层绝缘粘附带。
10.一种根据权利要求5的半导体器件,其中:
所述公用线覆盖相应于处理所述公共信号的各个电极压焊点以外的电极压焊点位置的两个侧边。
11.一种根据权利要求5的半导体器件,其中:
所述第一层导电粘附层或所述第二层导电粘附层构成所述半导体元件中的电源线,而所述第二层导电粘附层或所述第一层导电粘附层也构成所述半导体元件中的地线。
12.一种根据权利要求8的半导体器件,其中:
孔提供在所述第一层绝缘粘附带相应于各个处理所述公共信号的电极压焊点的位置,而且所述的各个电极压焊点通过所述孔中的金属凸点和所述的金属箔电连接。
13.一种制造半导体器件的方法包括:
一种第一层绝缘粘附带避开众多电极压焊点粘附在半导体元件上的步骤;
一种导电粘附层层叠在所述第一层绝缘粘附带上,同时所述导电粘附层与所述半导体元件上处理公共信号的电极压焊点电连接的步骤;
一种第二层绝缘粘附带层叠覆盖在所述导电粘附层表面上的步骤;以及
一种没有与所述导电粘附层或所述第二层绝缘粘附带相叠的电极压焊点与引脚电连接,通过把所述键合线跨接在所述第二层绝缘粘附带和将键合线与所述第二层绝缘粘附带接触放置,完成片外信号经由键合线输入和输出的步骤。
14.一种制造半导体器件的方法包括:
一种第一层绝缘粘附带避开众多电极压焊点粘附在半导体元件上的步骤;
一种第一层导电粘附层层叠在所述第一层绝缘粘附带上,同时所述导电粘附层与所述半导体元件上处理电源信号的电极压焊点电连接的步骤;
一种第二层绝缘粘附带层叠覆盖在所述第一层导电粘附层表面上的步骤;
一种第二层导电粘附层层叠在所述第二层绝缘粘附带上,同时所述导电粘附层与所述半导体元件上接地的电极压焊点电连接的步骤;
一种第三层绝缘粘附带层叠覆盖在所述第二层导电粘附层表面上的步骤;以及
一种没有被所述第一层导电粘附层,所述第二层导电粘附层,所述第二层绝缘粘附带和所述第三层绝缘粘附带层叠的电极压焊点与引脚电连接,通过把所述键合线跨接在所述第三层绝缘粘附带和将键合线与所述第三层绝缘粘附带接触放置,完成片外信号经由键合线输入和输出的步骤。
15.一种制造半导体器件的方法包括:
一种第一层绝缘粘附带避开众多电极压焊点粘附在半导体元件上的步骤;
一种金属箔层叠在所述第一层绝缘粘附带上,同时所述金属箔与所述半导体元件上处理公共信号的电极压焊点上凸点电连接的步骤;
一种第二层绝缘粘附带层叠覆盖在所述金属箔上的步骤;以及
一种没有被所述金属箔或所述第二层绝缘粘附带层叠的电极压焊点与引脚连接,通过把所述键合线跨接在所述第二层绝缘粘附带和将键合线与所述第二层绝缘粘附带接触放置,完成片外信号经由键合线输入和输出的步骤。
CNB971141134A 1997-03-28 1997-11-28 半导体器件及其制造方法 Expired - Fee Related CN1147931C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP07678097A JP3627949B2 (ja) 1997-03-28 1997-03-28 半導体装置およびその製造方法
JP076780/97 1997-03-28
JP076780/1997 1997-03-28

Publications (2)

Publication Number Publication Date
CN1195191A true CN1195191A (zh) 1998-10-07
CN1147931C CN1147931C (zh) 2004-04-28

Family

ID=13615121

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB971141134A Expired - Fee Related CN1147931C (zh) 1997-03-28 1997-11-28 半导体器件及其制造方法

Country Status (6)

Country Link
US (1) US6137166A (zh)
EP (1) EP0867938A3 (zh)
JP (1) JP3627949B2 (zh)
KR (1) KR100366114B1 (zh)
CN (1) CN1147931C (zh)
TW (1) TW392260B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100339980C (zh) * 2000-05-26 2007-09-26 奥斯兰姆奥普托半导体有限责任公司 具有表面金属敷层的半导体器件

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100561549B1 (ko) * 1999-10-07 2006-03-17 삼성전자주식회사 패드 온 칩형 반도체 패키지
US7626262B2 (en) * 2006-06-14 2009-12-01 Infineon Technologies Ag Electrically conductive connection, electronic component and method for their production
TW201205098A (en) * 2010-07-16 2012-02-01 Chroma Ate Inc Inspection fixture for semiconductor die test maintaining flatness of carrier portion

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4034399A (en) * 1976-02-27 1977-07-05 Rca Corporation Interconnection means for an array of majority carrier microwave devices
JPH04348045A (ja) * 1990-05-20 1992-12-03 Hitachi Ltd 半導体装置及びその製造方法
US5227232A (en) * 1991-01-23 1993-07-13 Lim Thiam B Conductive tape for semiconductor package, a lead frame without power buses for lead on chip package, and a semiconductor device with conductive tape power distribution
JPH05114622A (ja) * 1991-10-23 1993-05-07 Hitachi Ltd 半導体装置
JPH06283659A (ja) * 1993-03-25 1994-10-07 Mitsubishi Electric Corp 半導体装置
JPH06286659A (ja) 1993-03-31 1994-10-11 Suzuki Motor Corp ペダルブラケットの構造

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100339980C (zh) * 2000-05-26 2007-09-26 奥斯兰姆奥普托半导体有限责任公司 具有表面金属敷层的半导体器件

Also Published As

Publication number Publication date
EP0867938A3 (en) 1999-03-10
US6137166A (en) 2000-10-24
KR100366114B1 (ko) 2003-02-19
EP0867938A2 (en) 1998-09-30
KR19980079528A (ko) 1998-11-25
JPH10270491A (ja) 1998-10-09
TW392260B (en) 2000-06-01
JP3627949B2 (ja) 2005-03-09
CN1147931C (zh) 2004-04-28

Similar Documents

Publication Publication Date Title
JP4322844B2 (ja) 半導体装置および積層型半導体装置
JP5032623B2 (ja) 半導体記憶装置
CN1266764C (zh) 半导体器件及其制造方法
JP3913481B2 (ja) 半導体装置および半導体装置の製造方法
KR100204753B1 (ko) 엘오씨 유형의 적층 칩 패키지
US7229850B2 (en) Method of making assemblies having stacked semiconductor chips
JP4501279B2 (ja) 集積型電子部品及びその集積方法
JP2005020004A (ja) 複数のフリップチップを有するマルチチップパッケージ及びその製造方法
TW201230286A (en) Semiconductor device and method for manufacturing same
CN1591841A (zh) 带式电路基板及使用该带式电路基板的半导体芯片封装
WO2022021799A1 (zh) 半导体封装方法及半导体封装结构
JP4945682B2 (ja) 半導体記憶装置およびその製造方法
CN1147931C (zh) 半导体器件及其制造方法
JP3684434B2 (ja) チップサイズ半導体パッケージ及びその製造方法
JP3951462B2 (ja) 電子部品実装体及びその製造方法
JP3200488B2 (ja) 樹脂封止型半導体装置及びその製造方法
TWI286456B (en) Multi-layer circuit board integrated with electronic elements and method for fabricating the same
JP2004335970A (ja) 複合電子部品
TWI250597B (en) Method for manufacturing multi-chip package having encapsulated bond-wires between stack chips
JP2005167159A (ja) 積層型半導体装置
US6246109B1 (en) Semiconductor device and method for fabricating the same
JP4166097B2 (ja) 混成集積回路装置
JP3041849B2 (ja) 半導体装置及びその製造方法
JP2000174442A (ja) 電子部品の実装方法、及び半導体装置
JPH06342818A (ja) 半導体装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: OKI SEMICONDUCTOR CO., LTD.

Free format text: FORMER OWNER: OKI ELECTRIC INDUSTRY CO., LTD.

Effective date: 20090508

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20090508

Address after: Tokyo, Japan, Japan

Patentee after: OKI Semiconductor Co., Ltd.

Address before: Tokyo, Japan, Japan

Patentee before: Oki Electric Industry Co., Ltd.

C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20040428

Termination date: 20101128