CN1187826C - 半导体集成电路 - Google Patents

半导体集成电路 Download PDF

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CN1187826C
CN1187826C CN02143821.8A CN02143821A CN1187826C CN 1187826 C CN1187826 C CN 1187826C CN 02143821 A CN02143821 A CN 02143821A CN 1187826 C CN1187826 C CN 1187826C
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circuit
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CN1411065A (zh
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龜井貴之
浦川幸宏
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Toshiba Corp
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    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
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Abstract

本发明揭示一种半导体集成电路,包括作为测试对象的相互结构相同的多个测试对象电路,设置在各测试对象电路上的测试通路,以及通过对应的测试通路接受各测试对象电路的测试输出,并比较所述多个测试对象电路的测试输出是否一致的比较器。

Description

半导体集成电路
技术领域
本发明涉及具有扫描通路的半导体集成电路。
背景技术
过去,如图8所示,在安装有多个相同的逻辑电路3a,3b,3c,3d的半导体集成电路30中,考虑到要给上述逻辑电路3a,3b,3c,3d做测试时,就要设置测试通路(扫描通路)35,图解信息处理器是由这种测试通路使上述逻辑电路3a,3b,3c,3d的自锁电路(未图示)珠串连接而构成。测试时首先使测试图案串行化。然后,从半导体集成电路30的测试输入端子31输入这种测试图案,自锁电路设定值以后,脉冲进1,改变自锁电路的值。然后从半导体集成电路30的测试输出端子37输出其后的自锁电路的值,与期待值比较。当与期待值不同时即检测出半导体集成电路30的不良。根据这样,用很少的测试用端子31,37可以测试,输入图与期待值可自动生成。
但是,随着作为测试对象的逻辑电路的电路规模的增大,全部自锁电路用一条测试通路连接,测试不仅需要时间且随着测试图案和期待值的规模增大,就会压迫测试装置中收藏测试图案的存储器的容量。所以,如图9所示的半导体集成电路40考虑了设置通过逻辑电路3a,3b,3c,3d的从测试输入端子41到测试输出端子47的测试通路45a,45b分别分开到逻辑电路3a,3b,3c,3d的同时选择各逻辑电路的测试输出从测试输出端子47输出的选择器44的结构。这种半导体集成电路40在测试时,根据到选择器44的选择信号来切换测试哪一条通路,然后输入测试图案。
图9所示的半导体集成电路40中,因为只要给每个测试通路(即每个逻辑电路)准备测试图案和期待值就行,所以减小了测试图案的规模,也可以减少收藏测试图案的存储器的必要容量。
但是,图9所示的半导体集成电路中,所有电路必须依次进行测试,因此不能减少测试所需的时间。
发明内容
本发明的半导体集成电路,包括
作为测试对象的相同结构的多个测试对象电路,
设置在每个测试对象电路上的测试通路,以及
通过对应的测试通路接受各个测试对象电路的测试输出,比较上述多个测试对象电路的测试输出是否一致的比较器,其中,所述比较器将所述多个测试对象电路的规定的一个测试对象电路的测试输出原样输出到与将所述比较结果输出到外部的端子不同的端子。
附图说明
图1表示根据本发明第1实施形态的半导体集成电路的结构方块图。
图2表示根据本发明第2实施形态的半导体集成电路的结构方块图。
图3表示根据本发的第3实施形态的半导体集成电路的结构方块图。
图4表示根据本发明第4实施形态的半导体集成电路的结构方块图。
图5表示与第4实施形态相关的半导体集成电路的比较器结构的电路图。
图6表示根据本发明第5实施形态的半导体集成电路的结构方块图。
图7表示根据本发明第6实施形态的半导体集成电路的结构方块图。
图8表示以往的半导体集成电路结构方块图。
图9表示以往的半导体集成电路的其他结构方块图。
具体实施形态
以下参照附图具体说明关于本发明的实施形态。
(第1实施形态)
图1表示根据本发明第1实施形态的半导体集成电路结构。这种实施形态的半导体集成电路1包括测试输入端子2,作为测试对象的结构相同的如逻辑电路3a,3b,3c,3d,比较器5,测试输出端子7和测试通路4a,4b。测试输入端子2输入的测试图案通过测试通路4a送到各逻辑电路3a,3b,3c,3d。然后通过测试通路4b将各逻辑电路3a,3b,3c,3d的测试输出送到比较器5。所以测试通路是被每个逻辑电路3a,3b,3c,3d分割的结构。
比较器5是根据比较模式输入选择逻辑电路3a,3b,3c,3d的测试通路4b输入的测试输出的比较结果或直接输出哪一个的测试通路4b。比较器5的输出通过半导体集成电路1的测试输出端子7输出到外部。
接着,说明根据本实施形态的半导体集成电路1的测试时的动作。首先使输入到比较器5的比较模式置于“选择哪一个的测试通路即输出被选择的测试通路的输出”的状态。然后进行如图9所示的与以往的半导体集成电路相同的测试。即在外部比较输出端子输出的测试输出与输出期待值。这样测试被选择的一个测试通路(逻辑电路)。根据这种测试,可判定上述被选择的一个测试通路(逻辑电路)是否正常。在这里被判定为缺陷的,半导体集成电路也就被判定为不良品。被判定为正常时要进行以下的测试。
使上述比较模式处于“比较结果输出”的状态,输入测试图案。因为各测试通路4a,4b被分到各逻辑电路3a,3b,3c,3d上,当各逻辑电路3a,3b,3c,3d正常的话,对于半导体集成电路1的测试输入端子2输入的测试图案,各逻辑电路3a,3b,3c,3d的测试通路输出完全相同。所以把各逻辑电路3a,3b,3c,3d的测试通路输出送入比较器,检测出是否相同,就不必将所有测试通路与期待值比较。
这样,有多个相同结构的电路(例如逻辑电路)时,与测试两个电路(例如逻辑电路)相同的时间可测试所有的电路(例如逻辑电路)。而且,作比较模式的时候不必准备期待值的输出,可节约收藏测试图案的存储器的容量。
(第2实施形态)
图2表示根据本发明第2实施形态的半导体集成电路结构。这种实施形态的半导体集成电路1A,具有将图1所示第1实施形态的半导体集成电路1中的比较器5置换成比较器5A的结构。比较器5A的结构是同时比较输入的输出期待值和各逻辑电路3a,3b,3c,3d的测试输出是否一致并输出其结果。各逻辑电路3a,3b,3c,3d的测试输出时,对于比较器5A可同时根据输入的测试图案一次进行全部的逻辑电路3a,3b,3c,3d的试验。这样,相对第1实施形态,可进一步减少测试时间。而且,节约收藏测试图案的存储器的容量也是不言而喻的。
(第3实施形态)
图3表示根据本发明第3实施形态的半导体集成电路结构。这种实施形态的半导体集成电路1B,具有将图1所示第1实施形态的半导体集成电路1中的比较器5置换成比较器5B的同时,新设置有比较输出端子9的结构。这种比较器具有,将预先选择的一个逻辑电路(图3中是逻辑电路3a)的测试通路的输出直接由测试输出端子7输出的同时,比较各逻辑电路3a,3b,3c,3d的测试输出,将这种比较结果通过比较输出端子9输出到外部的结构。
这种实施形态的半导体集成电路1B,在外部的测试装置可以进行对测试通路的输出与期待值的比较并监视比较输出。这样,在第1实施形态中要进行的两次测试可减为一次,可进一步减少测试时间。而且,节约收藏测试图案的存储器的容量也是不言而喻的。
(第4实施形态)
图4表示根据本发明第4实施形态的半导体集成电路结构。这种实施形态的半导体集成电路1C,具有将图1所示第1实施形态的半导体集成电路1中的比较器5置换成比较器5C的同时,新设置有存储电路6且在逻辑电路3a,3b,3c,3d上分别设有切换电路8a,8b,8c,8d的结构。比较器5C与第2实施形态的比较器5A相同,比较输出期待值和逻辑电路3a,3b,3c,3d的测试输出是否全部一致并由输出端子7输出其比较结果到外部。进而比较器5C让存储电路6存储上述比较结果。图5表示这种比较器5C的一个具体例子的结构图。如图5所示,这种具体例子的比较器5C,具有异或门21a,21b,21c,21d,或门23。异或门21i(I=a,b,c,d)决定输出期待值与逻辑电路3i的测试输出是否不一致。这种异或门21a,21b,21c,21d的输出送到或门23的同时送到存储电路6。而且,或门23的输出要送到测试输出端子7。
第1到第3实施形态中,比较的结果只能检测出是否全部一致,只要有一个故障,芯片整个就会被判定为不良。
为了解决这种问题,本实施形态设置了存储电路6和切换电路8a,8b,8c,8d。存储电路6是不易消存储器,进行测试的时候可监视比较器5A送来的信号,存储各逻辑电路3a,3b,3c,3d每个是否发生不一致(即故障的有无)。而且,在测试结束后将存储电路6存储的内容输出到设在逻辑电路3a,3b,3c,3d上的切换电路8a,8b,8c,8d。切换电路8a,8b,8c,8d收到存储电路6输出的故障有无的情报,使对应的逻辑电路发生故障时对应的逻辑电路无效化。无效化的方法是停止供给脉冲到对应的逻辑电路,使其不动作。
第1到第3实施形态中只要有故障,芯片整个就会被判定为不良,而本实施形态是可以仅使含故障部位的逻辑电路不能使用的半导体集成电路。所以本实施形态的半导体集成电路1C,作为测试对象的电路(例如逻辑电路)不是单一,可用其他电路代替使之有效。
这种实施形态的半导体集成电路也与第1实施形态相同,减少测试时间的同时节约收藏测试图案的存储器容量。
(第5实施形态)
图6表示根据本发明第5实施形态的半导体集成电路结构。这种实施形态的半导体集成电路1D,由在图4所示的第4实施形态的半导体集成电路1C中冗余地设置作为测试对象的逻辑电路3r而构成。冗余设置的逻辑电路3r在逻辑电路3a,3b,3c,3d无故障时动作无效。与图4所示的第4实施形态相同的测试的结果,当逻辑电路3a,3b,3c,3d中的一个如逻辑电路3a故障时,存储电路6使检测出故障的逻辑电路3a无效,另一方面使冗余设置的逻辑电路3r有效地存储。测试结束后实际动作时,使冗余设置的逻辑电路3r有效,代替发生故障的逻辑电路3a动作。
在图4所示的第4实施形态中,作为测试对象的电路发生故障时,会使半导体集成电路的性能低下,在图6所示的第5实施形态中,因为让冗余的逻辑电路3r代替,所以有一个逻辑电路故障时半导体集成电路不会性能低下。
而且,这种实施形态也在减少测试时间的同时节约收藏测试图案的存储器容量。
(第6实施形态)
图7表示根据本发明第6实施形态的半导体集成电路结构。这种实施形态的半导体集成电路1E,具有在图1所示的第1实施形态的半导体集成电路中,在作为测试对象的逻辑电路3a,3b,3c,3d上追加了当这些逻辑电路间有接续信号线时,使测试动作中测试对象间的信号逻辑切断的切断电路10的结构。
作为测试对象的逻辑电路3a,3b,3c,3d间有信号线且这些信号线的连接在上述逻辑电路间为不同时,根据输入的测试图案,会有作为测试对象的各逻辑电路动作迥异的情况。例如在图7中,逻辑电路3a和逻辑电路3b间,逻辑电路3c和逻辑电路3d间是相同连接,逻辑电路3b和逻辑电路3c间连接不同时,输入同样的测试图案到各逻辑电路时,虽然作为测试对象的逻辑电路没有故障,但因为输出结果不同,所以不能象第1实施形态一样做单纯的比较。
所以,如图7所示,设置逻辑切断作为测试对象的各逻辑电路间的连接的切断电路10,使测试动作中作为测试对象的逻辑电路3a,3b,3c,3d间逻辑独立,对于相同的测试图案的输入,如果没有故障则得到相同输出,可以比较。而且,在第2至第5实施形态的半导体集成电路的结构中,也可以与本实施形态同样地插入切断电路8。
而且,上述第1至第6的实施形态说明了作为测试对象的电路为逻辑电路的情况,本发明也可适用于测试对象电路不限于逻辑电路的其他电路的情况。
如前所述,根据本发明,比以往可以缩短测试所需时间。

Claims (6)

1.一种半导体集成电路,其特征在于,包括
作为测试对象的相互结构相同的多个测试对象电路,
设置在各测试对象电路上的测试通路,
通过对应的测试通路接受各测试对象电路的测试输出,并比较所述多个测试对象电路的测试输出是否一致的比较器,
其中,所述比较器将所述多个测试对象电路的规定的一个测试对象电路的测试输出原样输出到与将所述比较结果输出到外部的端子不同的端子。
2.如权利要求1中记载的半导体集成电路,其特征在于,
所述比较器具有根据模式信号、选择所述多个测试对象电路内的一个测试对象电路,原样输出对应该选择的测试对象电路的测试通路的输出的功能。
3.如权利要求1中记载的半导体集成电路,其特征在于,
所述比较器比较所述多个测试对象电路的测试输出与期待值是否一致。
4.如权利要求3中记载的半导体集成电路,其特征在于,包括
存储电路,存储比较所述多个测试对象电路的测试输出与期待值是否一致的所述比较器的比较结果,
在每个测试对象电路上设置切换电路,根据所述存储电路的输出,判定所述多个测试对象电路中至少一个是否不良,在有不良的情况下,使测试结束后切换成所述不良的测试对象电路的动作无效。
5.如权利要求4中记载的半导体集成电路,其特征在于,包括
与所述测试对象电路相同结构的冗余电路,
在测试动作中,用所述冗余电路代替判定为故障的测试对象电路。
6.如权利要求1~3中任意一项记载的半导体集成电路,其特征在于,包括
切断电路,在测试动作中逻辑切断所述多个测试对象电路间的信号线的连接。
CN02143821.8A 2001-09-25 2002-09-25 半导体集成电路 Expired - Fee Related CN1187826C (zh)

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CN1411065A (zh) 2003-04-16
US20030061555A1 (en) 2003-03-27
DE60203032D1 (de) 2005-03-31

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