WO1999031727A1 - Systeme de controle de dispositifs electroniques et procede de fabrication de dispositifs electroniques utilisant celui-ci - Google Patents

Systeme de controle de dispositifs electroniques et procede de fabrication de dispositifs electroniques utilisant celui-ci Download PDF

Info

Publication number
WO1999031727A1
WO1999031727A1 PCT/JP1998/005125 JP9805125W WO9931727A1 WO 1999031727 A1 WO1999031727 A1 WO 1999031727A1 JP 9805125 W JP9805125 W JP 9805125W WO 9931727 A1 WO9931727 A1 WO 9931727A1
Authority
WO
WIPO (PCT)
Prior art keywords
processed
defect
inspection
processing step
electronic device
Prior art date
Application number
PCT/JP1998/005125
Other languages
English (en)
Japanese (ja)
Inventor
Shuichi Horisaki
Seiji Ishikawa
Isao Miyazaki
Jun Nakazato
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Publication of WO1999031727A1 publication Critical patent/WO1999031727A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

Definitions

  • the present invention relates to an electronic device inspection system applied to an electronic device manufacturing line and a manufacturing method using the inspection system, and in particular, to an electronic device that performs analysis processing using inspection data collected using various inspection devices.
  • This is a technology related to a device system and a manufacturing method using the inspection system.
  • Conventional electronic devices are formed by repeating a plurality of processing steps such as exposure, development, and etching on a wafer.
  • the wafer processed in a predetermined processing step of the plurality of processing steps is inspected by a foreign substance inspection apparatus or an external inspection apparatus as necessary, and the number and type of foreign substances and appearance defects adhering to the wafer are determined. , Size, etc. are detected.
  • the foreign matter to be detected by the foreign matter inspection device and the appearance defect to be detected by the appearance inspection device are collectively referred to as a defect.
  • this inspection result was analyzed as necessary, and the electronic device manufacturing line was managed based on the analysis result. For example, as disclosed in Japanese Patent Application Laid-Open No.
  • the present invention has been made in order to solve the conventional problems, and has as its object to provide an electronic device inspection system that uses a completely new information to reliably notify the occurrence of an abnormality in a production line. .
  • the present invention manages a manufacturing line based on the number of defects detected over a plurality of processes at the same location on the same wafer.
  • the same wafer refers to a wafer having a unique identification number, which has been processed in each processing step. Means something in a state.
  • a plurality of workpieces that are processed into electronic devices by being processed in a plurality of processing steps are processed in at least the first and second processing steps of the plurality of processing steps.
  • An inspection apparatus for detecting the same peak defect a storage means for storing the inspection data detected by the inspection apparatus, and a first processing step using the stored inspection data.
  • the above object is attained by providing an analyzing apparatus having an output means for outputting the work processed in the step or the second processing step in chronological order in the order of the workpieces processed by the second processing step. This makes it possible to manage the production line using information that is more likely to fail bits than in the past.
  • an inspection device for inspecting a defect of the work processed in the first processing step may be different from an inspection device for inspecting a defect of the work processed in the second processing step.
  • the analysis device may be constituted by at least a server having the storage means, and at least a personal computer having the output means, and the server or the personal computer may have the calculation means.
  • An inspection device for inspecting a bit-by-bit electrical characteristic of a chip formed on the workpiece with respect to the workpiece processed in the plurality of processing steps; and an inspection apparatus processed in the first processing step.
  • the defect where the position of the defective defect and the position of the defect processed in the second processing step are substantially the same and the ratio of the position of the bit where the electrical characteristic is defective is substantially the same.
  • calculating means for calculating, based on the ratio. It is possible to select a process in which a defect detected over a number of processes is likely to be a defective bit, and it is possible to efficiently manage a manufacturing line based on information that is likely to be a defective bit.
  • the present invention provides a method for processing a work which becomes an electronic device by being processed in a plurality of processing steps, wherein at least one of the plurality of processing steps has the same work processed in the first and second processing steps.
  • the number of defects where the position of the defect in the workpiece processed in the first processing step and the position of the defect in the workpiece processed in the second processing step are substantially the same is managed. Meanwhile, the above object can also be achieved by processing the work in the plurality of processing steps.
  • the electrical characteristics in bits of a chip formed on the work are inspected, and the chip having the work processed in the first processing step is provided.
  • the ratio of the position of the defect where the position of the defect and the position of the defect of the workpiece processed in the second processing step are substantially the same as the position of the bit where the electrical characteristics are defective are almost the same.
  • the first and second processing steps in which the work to be inspected by the inspection device has been processed may be selected using the calculated ratio.
  • Figure 1 shows the relationship between defects and fail bits that exist over multiple steps at the same location on the wafer.
  • the number of detected defects and the positions of the defects and the fail bits match.
  • the ratio to numbers is expressed as the F.B. (fail bit) correspondence rate.
  • F.B. correspondence ratio The higher the F.B. correspondence ratio, the higher the probability of failure due to defects.
  • a file bit means a bit that does not ultimately satisfy the electrical characteristics.
  • FIG. 1 is a diagram illustrating the principle of the present invention.
  • FIG. 2 shows one embodiment of the present invention. It is a system diagram showing the configuration of the embodiment.
  • FIG. 3 is a diagram showing inspection data according to an embodiment of the present invention.
  • FIG. 4 is a flowchart showing a process according to an embodiment of the present invention.
  • FIG. 5 is a diagram showing an output example according to the embodiment of the present invention.
  • FIG. 6 is a system diagram showing a configuration of an embodiment of the present invention.
  • FIG. 7 is a diagram showing an inspection data according to an embodiment of the present invention.
  • FIG. 8 is a flowchart showing a process according to the embodiment of the present invention.
  • FIG. 9 is a diagram showing an output example of one embodiment of the present invention.
  • FIG. 10 is a diagram showing an output example of one embodiment of the present invention.
  • FIG. 2 is a diagram showing the entire configuration of the inspection system of the present invention.
  • reference numeral 201 denotes a manufacturing process for processing a wafer
  • 202 denotes various inspection apparatuses such as a foreign substance inspection apparatus and a visual inspection apparatus for inspecting a wafer being manufactured
  • 203 denotes various inspection apparatuses.
  • 2 is a database that stores the results of inspections
  • 204 is an analysis device that performs analysis processing using the stored inspection results
  • 205 is an inspection device 202, a database 203, and an analysis device. This is a network connected to 204.
  • the collected inspection data is transmitted to the database 203 via the network 205 and stored in a data format as shown in FIG.
  • the analysis device 204 extracts the inspection data stored in the database 203 and performs an analysis process.
  • FIG. 4 is a flowchart showing the analysis processing in the analysis device 204.
  • Fig. 4 shows an example in which a run-in defect considered to have existed from the n-th process to the m-th process was analyzed.
  • the process group to be analyzed is selected in particular, in which it is considered that the flow-in defect is likely to cause a defective bit. The method of selecting this will be described later.
  • the inspection data detected in the n-th step and the m-th step (n ⁇ m) for the same wafer is extracted from the database 203 (step 40).
  • step 402 it is determined whether or not the positions of the defects detected in the n-th step and the m-th step match each other (step 402). For example, assuming that the position of a defect appearing in the n process is N (Xn, Yn) and the position of the defect in the m process is (Xm, Ym), the distance between these two points R mn force is less than a predetermined value R Determine whether or not. Then, for a defect that is equal to or smaller than the predetermined value R, it is determined that the position of the defect in the n-th process matches the position of the defect in the m-th process. That is, it is determined as a pouring defect. Note that R mn is as shown in Equation 1. [Equation 1]
  • steps 401 to 403 is performed for each wafer required for analysis.
  • the number of inflow defects obtained by the above processing is plotted in the order of the wafers processed in the manufacturing process 61 as shown in FIG. 5, and the transition of the number of inflow defects is displayed (step 404).
  • the transition of the number of inflow defects can be grasped. If the number of inflow defects does not satisfy the predetermined value, it is determined that there is an abnormality in the manufacturing process 601, and inspection and examination of manufacturing equipment and manufacturing conditions are performed and measures are taken. It becomes possible.
  • the management of the manufacturing process due to inflow defects has a higher probability of becoming a file bit than conventional management, and can be handled as more reliable information. That is, since management using information having a stronger causal relationship with the fail bit than in conventional management can be realized, unnecessary analysis and countermeasures can be reduced, and as a result, the throughput of the production line can be improved. In addition, since it is possible to analyze and take countermeasures at an early stage so as to reduce inflow defects, the yield is improved as compared with the conventional case.
  • Figure 6 shows the overall configuration of the inspection system.
  • reference numeral 61 denotes a manufacturing process for processing a wafer
  • reference numeral 62 denotes various inspection devices such as a foreign substance inspection device and an external inspection device for inspecting a wafer being manufactured
  • reference numeral 603 denotes a various inspection device for a wafer inspection process.
  • the first database that stores the inspection results, 604 is the inspection that is stored in the first database
  • the first analysis device that performs the analysis process using the results 605 is the inspection device 602, the first database 603, the network connected to the analysis device 604, and 606 is the manufacturing process 6
  • a test process for inspecting the electrical characteristics of the chips formed on the wafer after the processing in 01 607 is a tester for inspecting the electrical characteristics
  • 608 is a test result for the tester 607
  • a second database 609 to be stored is a second analyzer for performing an analysis process using the test results stored in the second database.
  • the tester 607 and the second database 608 are also connected to the network 605.
  • FIG. 8 is a flowchart showing a method of selecting the n-th step to the m-th step to be analyzed.
  • the first analysis terminal 604 or the second analysis terminal 609 obtains inspection data from the first database (step 801), and judges a flowing defect (step 802). Specifically, defect coordinates between each process, such as process A and process B, process A and process C, process ⁇ and process ⁇ , process C and process C, process D and process D, etc. Whether or not is located is determined for all combinations of processes, and the matched processes are determined as the first process in which a flow-in defect has occurred and the last process completed. It should be noted that whether or not the defect coordinates match is calculated in the same manner as in the method using Equation 1 described above. The process in which the defect was first detected It is also possible to determine the presence or absence of a defect having the same coordinates from the above, and determine a process continuously detected as a defect having the same coordinates as a process in which a flow-in defect has occurred.
  • the first analysis terminal 604 or the second analysis terminal 609 that has performed this determination process obtains the fail bit data of the corresponding wafer from the second database (step 804),
  • the position of the defect determined as the inflow defect is compared with the position of the fail bit stored in the second database (step 805). Also in this collation, calculation is performed in the same manner as in the method using Equation 1 described above. Then, it is determined whether or not the flow-in defect attached to the wafer causes a file bit, and the probability (the fatal rate) that the flow-in defect becomes a fail bit is calculated (step 806).
  • the calculation result is output in a format as shown in FIG. 9 (step 807).
  • the vertical axis represents the first step in which the flow of defects was detected, and the horizontal axis represents the last step in which the flow of defects was detected.
  • the numerical values in the table represent the probability of fail bits when the corresponding inflow defects are attached. For example, FIG. 9 shows that the probability of a file bit when the inflow defect is confirmed from the process B to the process D is 10%.
  • a process in which the probability of becoming a file bit is equal to or more than a predetermined value is selected as a process to be particularly controlled (step 808).
  • the calculation results as shown in Fig. 9 are used when a product change is performed. It is preferable to change it next.
  • the inspection system shown in FIG. 6 it is also possible to calculate the number of non-defective chips (yield) formed on the wafer using the tester 607. It is preferable to determine the correlation between the defects and determine the number of inflow defects to obtain the required yield, and use it as a management standard as shown in FIG.
  • the method of comparing the n-th process and the m-th process is not limited to the method described in Equation 1, and the same effect can be obtained by any method as long as it can be determined whether or not the defect positions match. It goes without saying that you can get it.
  • the flow-in defect was determined by comparing the n-th process to be analyzed with the m-th process, but all inspection data included from the n-th process to the m-th process were compared. Needless to say, the same effect can be obtained.
  • the analysis processing described so far may be performed by the server or by distributing the processing between the server and the analysis terminal.
  • the present invention by managing the number of inflow defects, it is possible to notify the occurrence of an abnormality in the production line with high reliability. In addition, by notifying the occurrence of the abnormality with high reliability, it becomes possible to improve the throughput and yield of the production line.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

L'invention concerne un système de contrôle de dispositifs électroniques pouvant résoudre un problème classique par une notification hautement fiable d'anormalités sur une ligne de production à l'aide d'informations innovatrices. Le système de contrôle est équipé d'un analyseur comportant un dispositif de contrôle qui permet de détecter un défaut d'un même travail effectué en au moins une première et une deuxième étapes de traitement comprises dans plusieurs étapes de traitement, parmi plusieurs travaux effectués sur un dispositif électronique au cours de ces étapes de traitement; un dispositif de stockage servant à stocker les données de contrôle détectées au moyen du dispositif de contrôle; un dispositif de calcul servant à calculer, au moyen des données de contrôle stockées, le nombre de défauts apparaissant presque aux mêmes positions sur un travail effectué au cours de la première étape de traitement que sur un travail effectué au cours de la deuxième étape de traitement; et un dispositif de sortie qui produit par séries temporelles les résultats calculés par le dispositif de calcul dans l'ordre des travaux traités au cours de la première ou de la deuxième étape de traitement.
PCT/JP1998/005125 1997-12-12 1998-11-13 Systeme de controle de dispositifs electroniques et procede de fabrication de dispositifs electroniques utilisant celui-ci WO1999031727A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP34249897A JP3307304B2 (ja) 1997-12-12 1997-12-12 電子デバイス検査システムおよびそれを用いた電子デバイスの製造方法
JP9/342498 1997-12-12

Publications (1)

Publication Number Publication Date
WO1999031727A1 true WO1999031727A1 (fr) 1999-06-24

Family

ID=18354220

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1998/005125 WO1999031727A1 (fr) 1997-12-12 1998-11-13 Systeme de controle de dispositifs electroniques et procede de fabrication de dispositifs electroniques utilisant celui-ci

Country Status (2)

Country Link
JP (1) JP3307304B2 (fr)
WO (1) WO1999031727A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100335491B1 (ko) * 1999-10-13 2002-05-04 윤종용 공정 파라미터 라이브러리를 내장한 웨이퍼 검사장비 및 웨이퍼 검사시의 공정 파라미터 설정방법
JP5095278B2 (ja) 2006-08-10 2012-12-12 株式会社日立製作所 半導体デバイス歩留り予測システムおよび方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04253350A (ja) * 1991-01-28 1992-09-09 Hitachi Electron Eng Co Ltd 異物検査データのマップ表示方法
JPH06275688A (ja) * 1993-03-19 1994-09-30 Hitachi Ltd 半導体ウエハ等の不良解析方法および装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04253350A (ja) * 1991-01-28 1992-09-09 Hitachi Electron Eng Co Ltd 異物検査データのマップ表示方法
JPH06275688A (ja) * 1993-03-19 1994-09-30 Hitachi Ltd 半導体ウエハ等の不良解析方法および装置

Also Published As

Publication number Publication date
JP3307304B2 (ja) 2002-07-24
JPH11176892A (ja) 1999-07-02

Similar Documents

Publication Publication Date Title
JP4694618B2 (ja) 欠陥分布分類方法およびシステム、原因設備特定方法およびシステム、コンピュータプログラム、並びに記録媒体
US6701204B1 (en) System and method for finding defective tools in a semiconductor fabrication facility
JP2002071575A (ja) 欠陥検査解析方法および欠陥検査解析システム
JP2009010405A (ja) 局所的外れ値の検出のための方法および装置
JPH10173021A (ja) 製造ライン解析方法及び製造ライン解析装置
JP2006518101A (ja) データ分析用の装置および方法
JP2002057078A (ja) 半導体製造施設で集積欠陥を引き起こす動作／ツールを見つけるシステム及び方法
US7991497B2 (en) Method and system for defect detection in manufacturing integrated circuits
KR20030051064A (ko) 순수 디펙트에 의한 페일 발생 확률 측정방법, 순수디펙트에서 추출한 패턴 파라미터의 분류를 이용한 디펙트제한 수율 측정 방법 및 순수 디펙트에 의한 페일 발생확률 및 디펙트 제한 수율을 측정하기 위한 시스템
CN114839464B (zh) 一种指数寿命型产品的快速检验方法、系统、设备及终端
JPH10214866A (ja) 不良解析方法および装置
JP2000269276A (ja) 欠陥解析システムおよびその方法
JP2000223385A (ja) 電子デバイスの品質管理方法
WO1999031727A1 (fr) Systeme de controle de dispositifs electroniques et procede de fabrication de dispositifs electroniques utilisant celui-ci
US20230081224A1 (en) Method and system for evaluating test data, wafer test system, and storage medium
JP4866263B2 (ja) 電子デバイスの品質管理方法および電子デバイスの品質管理システム
Elliott et al. Critical dimension sample planning for sub-0.25 micron processes
JP3916771B2 (ja) 半導体装置の製造方法
US7421357B2 (en) Inspection data analysis program, inspection tools, review apparatus and yield analysis apparatus
JP3324447B2 (ja) 歩留阻害要因推定方法
TW200421518A (en) LSI inspection method and defect inspection data analysis apparatus
JP3808575B2 (ja) 歩留まり解析方法及びその装置
JPH11176899A (ja) 欠陥警告方法及び欠陥警告システム
JPH1116973A (ja) 半導体装置製造方法及びその半導体装置製造方法で製造された半導体装置
JPH0927531A (ja) 歩留まり統計解析方法および装置

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CN KR SG US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: KR

122 Ep: pct application non-entry in european phase