CN1187824C - 半导体存储装置及其制造方法 - Google Patents

半导体存储装置及其制造方法 Download PDF

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Publication number
CN1187824C
CN1187824C CNB021161240A CN02116124A CN1187824C CN 1187824 C CN1187824 C CN 1187824C CN B021161240 A CNB021161240 A CN B021161240A CN 02116124 A CN02116124 A CN 02116124A CN 1187824 C CN1187824 C CN 1187824C
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CN
China
Prior art keywords
mentioned
wiring
magneto
effect device
resistance effect
Prior art date
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Expired - Fee Related
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CNB021161240A
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English (en)
Chinese (zh)
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CN1383208A (zh
Inventor
梶山健
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Toshiba Corp
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Toshiba Corp
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Publication date
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Publication of CN1383208A publication Critical patent/CN1383208A/zh
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Publication of CN1187824C publication Critical patent/CN1187824C/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)
  • Semiconductor Memories (AREA)
CNB021161240A 2001-04-20 2002-04-19 半导体存储装置及其制造方法 Expired - Fee Related CN1187824C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP122882/2001 2001-04-20
JP2001122882A JP4488645B2 (ja) 2001-04-20 2001-04-20 磁気記憶装置

Publications (2)

Publication Number Publication Date
CN1383208A CN1383208A (zh) 2002-12-04
CN1187824C true CN1187824C (zh) 2005-02-02

Family

ID=18972525

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB021161240A Expired - Fee Related CN1187824C (zh) 2001-04-20 2002-04-19 半导体存储装置及其制造方法

Country Status (5)

Country Link
US (3) US6617658B2 (https=)
JP (1) JP4488645B2 (https=)
KR (1) KR100470848B1 (https=)
CN (1) CN1187824C (https=)
TW (1) TW543086B (https=)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6689661B2 (en) * 2001-04-10 2004-02-10 Micron Technology, Inc. Method for forming minimally spaced MRAM structures
JP3884312B2 (ja) * 2002-03-28 2007-02-21 株式会社東芝 磁気記憶装置
US6897532B1 (en) * 2002-04-15 2005-05-24 Cypress Semiconductor Corp. Magnetic tunneling junction configuration and a method for making the same
US6828639B2 (en) * 2002-07-17 2004-12-07 Micron Technology, Inc. Process flow for building MRAM structures
JP4509467B2 (ja) * 2002-11-08 2010-07-21 シャープ株式会社 不揮発可変抵抗素子、及び記憶装置
US7221584B2 (en) * 2004-08-13 2007-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. MRAM cell having shared configuration
US7319262B2 (en) * 2004-08-13 2008-01-15 Taiwan Semiconductor Manufacturing Company, Ltd. MRAM over sloped pillar
US7088612B2 (en) * 2004-08-20 2006-08-08 Infineon Technologies Ag MRAM with vertical storage element in two layer-arrangement and field sensor
US7416905B2 (en) * 2005-10-17 2008-08-26 International Busniess Machines Corporation Method of fabricating a magnetic shift register
US8679860B1 (en) * 2006-08-07 2014-03-25 Sandia Corporation Lateral electrodeposition of compositionally modulated metal layers
JP4343940B2 (ja) * 2006-10-31 2009-10-14 Ｔｄｋ株式会社 磁気抵抗効果素子、薄膜磁気ヘッド、ヘッドジンバルアセンブリ、ハードディスク装置および磁気抵抗効果素子の製造方法
US7919794B2 (en) * 2008-01-08 2011-04-05 Qualcomm, Incorporated Memory cell and method of forming a magnetic tunnel junction (MTJ) of a memory cell
US7579197B1 (en) * 2008-03-04 2009-08-25 Qualcomm Incorporated Method of forming a magnetic tunnel junction structure
US8634231B2 (en) * 2009-08-24 2014-01-21 Qualcomm Incorporated Magnetic tunnel junction structure
US7781231B2 (en) * 2008-03-07 2010-08-24 Qualcomm Incorporated Method of forming a magnetic tunnel junction device
US7885105B2 (en) * 2008-03-25 2011-02-08 Qualcomm Incorporated Magnetic tunnel junction cell including multiple vertical magnetic domains
US9614003B1 (en) * 2015-10-21 2017-04-04 Globalfoundries Inc. Method of forming a memory device structure and memory device structure
US20190140167A1 (en) * 2017-11-07 2019-05-09 Everspin Technologies, Inc. Angled surface removal process and structure relating thereto
WO2023026481A1 (ja) * 2021-08-27 2023-03-02 Tdk株式会社 磁気抵抗効果素子及び磁気メモリ
TWI809966B (zh) * 2022-05-17 2023-07-21 南亞科技股份有限公司 具有氟捕捉層的半導體元件結構
US12308319B2 (en) 2022-05-17 2025-05-20 Nanya Technology Corporation Semiconductor device structure with fluorine-catching layer
US12308290B2 (en) 2022-05-17 2025-05-20 Nanya Technology Corporation Method for preparing semiconductor device structure with fluorine-catching layer

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5640343A (en) * 1996-03-18 1997-06-17 International Business Machines Corporation Magnetic memory array using magnetic tunnel junction devices in the memory cells
US5835314A (en) 1996-04-17 1998-11-10 Massachusetts Institute Of Technology Tunnel junction device for storage and switching of signals
US5920500A (en) * 1996-08-23 1999-07-06 Motorola, Inc. Magnetic random access memory having stacked memory cells and fabrication method therefor
JP3593652B2 (ja) * 2000-03-03 2004-11-24 富士通株式会社 磁気ランダムアクセスメモリ装置
US6515341B2 (en) * 2001-02-26 2003-02-04 Motorola, Inc. Magnetoelectronics element having a stressed over-layer configured for alteration of the switching energy barrier

Also Published As

Publication number Publication date
US20050002248A1 (en) 2005-01-06
JP4488645B2 (ja) 2010-06-23
US20040105320A1 (en) 2004-06-03
US6967864B2 (en) 2005-11-22
KR100470848B1 (ko) 2005-03-08
US6617658B2 (en) 2003-09-09
CN1383208A (zh) 2002-12-04
KR20030009107A (ko) 2003-01-29
JP2002319663A (ja) 2002-10-31
TW543086B (en) 2003-07-21
US6764865B2 (en) 2004-07-20
US20020153547A1 (en) 2002-10-24

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Granted publication date: 20050202

Termination date: 20130419